CN102779745B - The method controlling trench transistor gate dielectric layer thickness - Google Patents
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- CN102779745B CN102779745B CN201210256677.2A CN201210256677A CN102779745B CN 102779745 B CN102779745 B CN 102779745B CN 201210256677 A CN201210256677 A CN 201210256677A CN 102779745 B CN102779745 B CN 102779745B
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Abstract
A kind of method controlling trench transistor gate dielectric layer thickness, including: providing test substrate, test substrate has the Cutting Road between device region and adjacent devices district；Forming the first groove in the device region of test substrate, form the second groove in the Cutting Road of test substrate, the sidewall crystal orientation of the second groove deflects 45 degree of angles relative to the first groove；In the first groove and the second groove, the first oxide layer and the second oxide layer is formed respectively with thermal oxidation technology；Obtain the technological parameter of the second oxide layer forming preset thickness；Thering is provided epitaxial substrate, the crystal orientation of epitaxial substrate wafer notch becomes 45 degree of angles relative to test substrate wafer notch, and epitaxial substrate has device region；In the device region of epitaxial substrate, the 3rd groove is formed with the position of the first groove and technological parameter；The identical thermal oxidation technology of the second oxide coating process parameter adopted and form preset thickness, formation the 3rd oxide layer in the 3rd groove.The gate dielectric layer thickness obtaining epitaxial substrate device region is easily controlled.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of method controlling trench transistor gate dielectric layer thickness.
Background technology
At present, transistor is widely used as a kind of basic semiconductor device.And in various transistors, trench metal-Oxide-Semiconductor Field effect transistor (TrenchMetal-Oxide-SiliconTransistors, TrenchMOS) as a kind of power device, it is widely used in integrated circuit and discrete device circuit.
The cross-sectional view of the forming process of existing trench transistor, as shown in Figures 1 to 4, including:
Refer to Fig. 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 includes: the epitaxial layer of silicon substrate and above-mentioned surface of silicon, has groove 101 in the epitaxial layer of described Semiconductor substrate 100, and the sidewall of described groove 101 is vertical with Semiconductor substrate 100 surface.
Refer to Fig. 2, sidewall and lower surface described groove 101 (such as Fig. 1) form gate dielectric layer 102, and the material of described gate dielectric layer 102 is silicon oxide, and the formation process of described gate dielectric layer 102 is thermal oxidation technology；The gate electrode layer 103 filling full described groove 101 is formed on described gate dielectric layer 102 surface.
Refer to Fig. 3, after forming gate electrode layer 103, form mask layer 104 on described Semiconductor substrate 100 surface, described mask layer 104 exposes gate electrode layer 103 and part semiconductor substrate 100 surface；
Refer to Fig. 4, with described mask layer 104 for mask, in described Semiconductor substrate 100, ion implanting forms body district 107；
Refer to Fig. 5, after forming body district 107, form mask layer 106 at described gate electrode layer 103 and gate dielectric layer 102 surface；With mask layer 104 and mask layer 106 for mask, in Semiconductor substrate 100, ion implanting forms source region 105.
But, the thickness of the gate dielectric layer in existing trench transistor cannot accurately control, and causes that the parameter such as cut-in voltage of the trench metal formed-Oxide-Semiconductor Field effect transistor has deviation with designing requirement.
More trench transistors refer to the Chinese patent document that publication number is CN102110687A.
Summary of the invention
The problem that this invention address that is to provide a kind of method controlling trench transistor gate dielectric layer thickness, make the gate dielectric layer thickness of the epitaxial substrate device region formed control and adjust can be more accurate, lower in cost, the device performance of formation is more preferably.
For solving the problems referred to above, the present invention provides a kind of method controlling trench transistor gate dielectric layer thickness, including: providing test substrate, described test substrate has some device regions, having Cutting Road district between described adjacent devices district, the edge of described test substrate has wafer notch；Some the first grooves being parallel to each other are formed in the device region of described test substrate, in the Cutting Road district of described test substrate, form some the second grooves being parallel to each other simultaneously, the crystal orientation of described second trenched side-wall deflects 45 degree of angles relative to the crystal orientation of described first trenched side-wall, when the shape of described first groove reaches preset shape, obtain the technological parameter forming described first groove；Thermal oxidation technology is adopted to form the first oxide layer in sidewall and the lower surface of described first groove, sidewall and lower surface at described second groove concurrently form the second oxide layer, when the thickness of described second oxide layer reaches preset thickness, obtain the formation process parameter of described second oxide layer；Thering is provided epitaxial substrate, described epitaxial substrate has some device regions, and the edge of described epitaxial substrate has wafer notch, and the crystal orientation of described epitaxial substrate wafer notch becomes 45 degree of angles relative to the crystal orientation of test substrate wafer notch；Adopt the technological parameter of described first groove, in the device region of described epitaxial substrate, form some the 3rd grooves being parallel to each other；Adopting thermal oxidation technology to form the 3rd oxide layer in sidewall and the lower surface of described 3rd groove, the parameter of described thermal oxidation technology is identical with the technological parameter of the second oxide layer forming preset thickness.
Alternatively, it it is 100 angstroms～1000 angstroms in described preset thickness.
Alternatively, the preset shape of described first groove includes: the degree of depth of described first groove is 0.8～2 micron, and the bottom of described first groove is round and smooth to test substrate sunken inside and surface.
Alternatively, the forming step of described first groove and the second groove is: with the first mask blank, forms the first photoresist layer at test substrate surface；With described first photoresist layer for mask, adopt etching technics to form some the first grooves being parallel to each other in the device region of described test substrate simultaneously, in the Cutting Road district of described test substrate, form some the second grooves being parallel to each other.
Alternatively, the step of described 3rd groove is: with the first mask blank, form the second photoresist layer at extension substrate surface；With described second photoresist layer for mask, etching technics is adopted to form some the 3rd grooves being parallel to each other in the device region of described epitaxial substrate；While forming described 3rd groove, in the Cutting Road district of described epitaxial substrate, form some the 4th grooves being parallel to each other.
Alternatively, the technological parameter of described first groove includes: the position of etching gas, etch period, etching bias and described first groove.
Alternatively, the technological parameter of the second oxide layer of described formation preset thickness includes: reacting gas, response time and reaction temperature.
Alternatively, the step obtaining described second oxidated layer thickness is: described second oxide layer is cut into slices；Section measurement to described second oxide layer section, obtains the thickness of described second oxide layer.
Alternatively, also include: after forming the first oxide layer and the second oxide layer, in described first groove, form the first gate electrode layer filling full described first groove, in described second groove, form the second gate electrode layer filling full described second groove；Obtain being formed the technological parameter of described first gate electrode layer and second gate electrode layer.
Alternatively, to form the technological parameter of described first gate electrode layer and second gate electrode layer, in described 3rd groove, form the 3rd gate electrode layer filling full described 3rd groove.
Alternatively, the material of described first gate electrode layer, second gate electrode layer and the 3rd gate electrode layer is polysilicon.
Alternatively, described epitaxial substrate also includes: the Cutting Road district between adjacent devices district.
Alternatively, described epitaxial substrate includes: silicon substrate and be positioned at the epitaxial layer of described surface of silicon.
Alternatively, described test substrate is silicon substrate.
Alternatively, the crystal orientation of the wafer notch of described test substrate or epitaxial substrate is identical with the direction of the diameter wafer by described wafer notch.
Alternatively, the notch crystal orientation of described epitaxial substrate is<100>.
Alternatively, the notch crystal orientation of described test substrate is<110>.
Compared with prior art, technical scheme has the advantage that
In the Cutting Road district of test substrate, form the second groove, adopt thermal oxidation technology to form the second oxide layer in sidewall and the lower surface of described second groove, and when the thickness of described second oxide layer reaches preset thickness, record technological parameter；And in the 3rd groove, form the 3rd oxide layer with described technological parameter, described 3rd groove is formed in the device region of epitaxial substrate, and position in the device region of test substrate of position and shape and the first groove and shape identical；Owing to the crystal orientation of described epitaxial substrate wafer notch becomes 45 degree of angles relative to the crystal orientation of test substrate wafer notch, therefore the crystal face of the 3rd trenched side-wall becomes 45 degree of angles relative to the crystal face of described first trenched side-wall；When the crystal orientation of described second trenched side-wall deflects 45 degree of angles relative to the crystal orientation of described first trenched side-wall, the described sidewall of the second groove is identical with the indices of crystallographic plane of the 3rd groove with the indices of crystallographic plane of lower surface, the sidewall of described second groove is also identical with the covalent bond density of the sidewall of described 3rd groove and lower surface with the covalent bond density of lower surface, therefore adopts the second oxide layer that identical thermal oxidation technology is formed identical with the 3rd oxidated layer thickness；When forming the second oxide layer reaching preset thickness in the second groove testing substrate, record thermal oxidation technology parameter at that time, and in the 3rd groove, forming the 3rd oxide layer with identical thermal oxidation technology, the 3rd oxide layer formed can reach preset thickness too；Control and the adjustment of the gate dielectric layer thickness of the epitaxial substrate device region formed when described 3rd oxide layer is as the gate dielectric layer of trench transistor can be more accurate, lower in cost, and the device performance of formation is more preferably.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the cross-sectional view of the forming process of existing trench transistor；
Fig. 6 is the structural representation of (110) crystal face and (100) crystal face；
Fig. 7 is the schematic flow sheet of the method for the control trench transistor gate dielectric layer thickness of the embodiment of the present invention；
Fig. 8 to Figure 10, Figure 13 are the plan structure schematic diagram of the process of the control trench transistor gate dielectric layer thickness of the embodiment of the present invention to 15；
Figure 11 is Figure 10 cross-sectional view on AA ' direction；
Figure 12 is Figure 10 cross-sectional view on BB ' direction；
Figure 16 is Figure 15 cross-sectional view on CC ' direction；
Figure 17 is Figure 15 cross-sectional view on DD ' direction.
Detailed description of the invention
As stated in the Background Art, the thickness of the gate dielectric layer in existing trench transistor cannot accurately control, and the parameter such as cut-in voltage causing the trench metal formed-Oxide-Semiconductor Field effect transistor has deviation.
Whether prior art, when forming trench transistor, first can form the required trench transistor formed on test substrate, suitable to determine the technological process parameter forming described trench transistor；Afterwards, with fixed technological process, in epitaxial substrate, forming trench transistor, thus avoiding the waste of epitaxial substrate, saving cost.
Owing to described test substrate is usually used in providing the use of the test of the various device of integrated circuit, therefore to saving cost, the silicon chip that generally unified use is relatively inexpensive, the crystal face of described silicon chip surface all identical (such as (100) crystal face), and described silicon chip has the crystal orientation of identical wafer notch, such as<110>crystal orientation, wherein, described wafer notch for determining the use in wafer direction in each technical process, and the crystal orientation of described wafer notch is consistent with by the diameter wafer direction of described notch；But needing the formal epitaxial substrate forming trench transistor, its wafer notch crystal orientation can be different according to requirement on devices, for instance<100>crystal orientation；Owing to the crystal orientation of trenched side-wall of the trench transistor of required formation is parallel to each other or vertical with the crystal orientation of described wafer notch, and identical with shape with the grooved position in epitaxial substrate in testing substrate；Specifically, when the wafer notch crystal orientation of silicon chip is<110>, when the wafer notch crystal orientation of epitaxial substrate is<100>, and the crystal orientation of trenched side-wall parallel with the crystal orientation of wafer notch time, the crystal face of the trenched side-wall being positioned at test substrate is (110), and the crystal face of the trenched side-wall in epitaxial substrate is (100)；Refer to Fig. 6, for the structural representation of (110) crystal face He (100) crystal face, it will be appreciated from fig. 6 that the crystal face of the trenched side-wall in described epitaxial substrate becomes 45 degree of angles relative to the crystal face of the trenched side-wall in described test substrate.
The present inventor finds through research, owing to the trenched side-wall crystal face of described test substrate and the trenched side-wall crystal face of described epitaxial substrate are different, when, respectively when the groove that test substrate is identical with the same position of epitaxial substrate formation shape, its sidewall is different with the covalent bond density of lower surface；When adopting identical thermal oxidation technology, respectively when the trenched side-wall tested in substrate and outer substrate and lower surface form gate dielectric layer, the thickness of the gate dielectric layer formed is different；Concrete, the repeatedly test through inventor obtains, and the gate dielectric layer formed in the groove of test substrate is than the gate medium thickness formed in the groove of epitaxial substrate.
Refer to table 1, for adopting identical thermal oxidation technology, be formed at the thickness of the gate dielectric layer of the trenched side-wall in test substrate and lower surface, and be formed at the test result synopsis of the thickness of the gate dielectric layer of the trenched side-wall in epitaxial substrate and lower surface.
Table 1
| Substrate | Test 1 (angstrom) | Test 2 (angstroms) | Test 3 (angstroms) |
| Test substrate | 937 | 937 | 937 |
| Epitaxial substrate | 714 | 718 | 716 |
As shown in Table 1, form the technological parameter of gate dielectric layer according in test substrate, in the groove of outer substrate, form gate dielectric layer, can cause that the thickness of gate dielectric layer formed is excessively thin, it is unable to reach technical specification, so that the transistor yield formed declines.
In order to solve the problems referred to above, the present inventor is after further research, the second groove is formed in Cutting Road district between test substrate devices district, and the crystal orientation of described second trenched side-wall is relative to 45 degree of angles of deflection, crystal orientation of test substrate devices district internal channel sidewall, the sidewall of the second groove formed is identical with the crystal face of the sidewall of the groove being formed in epitaxial substrate device region and bottom with the crystal face of bottom, thus the covalent bond density of the sidewall of the second groove formed and lower surface, with the groove being formed in epitaxial substrate device region, its sidewall is identical with the covalent bond density of lower surface；Therefore in described second groove, form the technique of oxide layer can be applied in the device region groove of epitaxial substrate formation oxide layer, and be formed at the oxidated layer thickness in epitaxial substrate device region groove and the oxidated layer thickness in the second groove is consistent；The described oxide layer being formed in epitaxial substrate device region groove is for the gate dielectric layer as trench transistor, it is possible to reaches accurately to control the purpose of trench transistor gate dielectric layer, makes the stable performance of the trench transistor formed.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 7 is the schematic flow sheet of the method for the control trench transistor gate dielectric layer thickness of the embodiment of the present invention, including step:
Step S101, it is provided that test substrate, described test substrate has some device regions, has Cutting Road district between described adjacent devices district, and the edge of described test substrate has wafer notch, and described test substrate surface has the first photoresist layer；
Step S102, with described first photoresist layer for testing substrate described in mask etching, some the first grooves being parallel to each other are formed in the device region of described test substrate, some the second grooves being parallel to each other are formed in the Cutting Road of described test substrate, the crystal orientation of described second trenched side-wall deflects 45 degree of angles relative to the crystal orientation of described first trenched side-wall, when the shape of described first groove reaches preset shape, obtain the technological parameter forming described first groove and the second groove；
Step S103, adopts thermal oxidation technology to form the first oxide layer in sidewall and the lower surface of described first groove, and sidewall and lower surface at described second groove concurrently form the second oxide layer；Test the thickness of described second oxide layer, when the thickness of described second oxide layer reaches preset thickness, obtain the formation process parameter of described second oxide layer；
Step S104, epitaxial substrate is provided, the edge of described epitaxial substrate has wafer notch, the crystal orientation of described epitaxial substrate wafer notch becomes 45 degree of angles relative to the crystal orientation of test substrate wafer notch, described epitaxial substrate has some device regions, having Cutting Road district between described adjacent devices district, described epitaxial substrate surface has the second photoresist layer, and the shape of described second photoresist layer is identical with the shape of described first photoresist layer；
Step S105, adopt the technological parameter forming described first groove and the second groove, with described second photoresist layer for epitaxial substrate described in mask etching, in the device region of described epitaxial substrate, form some the 3rd grooves being parallel to each other, in the Cutting Road district of described epitaxial substrate, form some the 4th grooves being parallel to each other；
Step S106, thermal oxidation technology is adopted to form the 3rd oxide layer in sidewall and the lower surface of described 3rd groove, sidewall and lower surface at described 4th groove form the 4th oxide layer, and the parameter of described thermal oxidation technology is identical with the technological parameter of the second oxide layer forming preset thickness.
Below with reference to accompanying drawing, the method for the control trench transistor gate dielectric layer thickness of the embodiment of the present invention is illustrated, Fig. 8 to Figure 10, Figure 13 are the plan structure schematic diagram of the process of the control trench transistor gate dielectric layer thickness of the embodiment of the present invention to 15, Figure 11 is Figure 10 cross-sectional view on AA ' direction, Figure 12 is Figure 10 cross-sectional view on BB ' direction, Figure 16 is Figure 15 cross-sectional view on CC ' direction, and Figure 17 is Figure 15 cross-sectional view on DD ' direction.
Refer to Fig. 8, thering is provided test substrate 200, described test substrate 200 has some device regions 201, has Cutting Road district 202 between described adjacent devices district 201, described test substrate 200 has wafer notch (not shown), and described test substrate 200 surface has the first photoresist layer 203.
Described test substrate 200 is for simulating the follow-up technological process forming trench transistor in epitaxial substrate, forming trench transistor on described test substrate 200 and can reflect that whether the technological process adopted is reasonable, whether the shape of the trench transistor formed, position and performance meet design standard；After defining, on described test substrate 200, the trench transistor meeting design standard, in epitaxial substrate, formally forming trench transistor with obtained technological process, thus avoiding the waste of epitaxial substrate, and improving the yield of the trench transistor formed；Described device region 201 is used for being formed trench transistor and other semiconductor device, and described Cutting Road district 202 is used for dividing device region 201, and carries out the region cut after the manufacture completing semiconductor device.
In the present embodiment, the material of described test substrate 200 is silicon, and the crystal face on described test substrate 200 surface is (100)；The silicon materials test substrate 200 that described crystal face is (100) is relatively inexpensive such that it is able to save cost；；The crystal orientation of the wafer notch of described test substrate 200 is<110>；Due to, follow-up needs formally form the wafer notch crystal orientation of the epitaxial substrate of trench transistor, different with described test substrate 200 according to concrete technological requirement；In the present embodiment, the wafer notch crystal orientation of the epitaxial substrate of follow-up employing is<100>, the wafer notch direction causing described test substrate 200 deflects 45 degree of angles relative to the crystal orientation of the wafer notch of described epitaxial substrate, so that being subsequently formed in test substrate 200 different from the crystal orientation of its sidewall surfaces of groove of same position same shape in epitaxial substrate, the described test substrate of final impact is for the result of simulation process flow process.
The wafer notch of described test substrate 200 is in described test substrate 200 edge, and it is perpendicular to the cutting mouth on described test substrate 200 surface, for determining the direction of described test substrate 200 in the technological process of each road, and make the described test substrate cannot be arbitrarily mobile in technical process；In the present embodiment, the crystal orientation of described wafer notch is identical with the direction of the diameter by described wafer notch.
Described first photoresist layer 203 exposes the position of follow-up the first groove needing to be formed and the second groove, and the formation process of described first photoresist layer 203 is: at described test substrate 200 surface coating photoresist thin film, and dry described photoresist film；With the first mask blank, described photoresist film is exposed, makes described photoresist film expose the correspondence position being subsequently formed the first groove in device region 201, and be formed at the correspondence position of second groove in Cutting Road district 202.
When the figure of the first photoresist layer 203 formed meets design standard, obtain the lithography layout for forming described first photoresist layer 203, and described lithography layout uses when being subsequently formed the second photoresist layer being positioned at epitaxial substrate surface.
Refer to Fig. 9, with described first photoresist layer 203 (such as Fig. 7) for testing substrate 200 as described in mask etching, some the first grooves 204 being parallel to each other are formed in the device region 201 of described test substrate 200, some the second grooves 205 being parallel to each other are formed in the Cutting Road district 202 of described test substrate 200, the crystal orientation of described second groove 205 sidewall deflects 45 degree of angles relative to the crystal orientation of described first groove 204 sidewall, when the shape of described first groove 204 reaches preset shape, obtain the technological parameter forming described first groove 204 and the second groove 205.
Described preset shape is described first groove 204 shape when meeting designing requirement, and described preset shape is had nothing in common with each other according to the difference of designing requirement；In the present embodiment, when described first groove 204 meets preset shape, described first groove 204 depth bounds is 0.8～2 micron, and the bottom of described first groove 204 is to test substrate sunken inside, and surface is round and smooth；When adopting the groove reaching to meet preset shape to form trench transistor, functional, and leakage current is less；In other embodiments, described first groove 204 can according to concrete technology percentage regulation, and the shape of sidewall and bottom.
In the present embodiment, described etching technics is anisotropic dry etching, described anisotropic dry etching, and etching gas is the mixing gas of chlorine, hydrogen bromide or chlorine and hydrogen bromide；Described respectively include to dry etch process parameter: the flow of hydrogen bromide is 200～800sccm, and the flow of chlorine is 20～100sccm, and the flow of noble gas is 50～1000sccm, and the pressure of etching cavity is 2～200mTorr, and etch period is 15～60 seconds.
After described anisotropic dry etch process, the lower surface of the first groove 204 formed and the second groove 205 is carried out isotropic dry etch process, make the bottom of described first groove 204 and the second groove 205 to test substrate 200 sunken inside, and surface is round and smooth；The drift angle bottom the first groove 204 formed and the second groove 205 is avoided to produce point effect and produce leakage current.
Record when the first groove 204 formed meets preset shape, the technological parameter such as described anisotropic dry etch process and the etching gas kind of isotropic dry etch process, each gas flow, etching cavity pressure and etch period；Obtained technological parameter uses when the 3rd groove being subsequently formed in epitaxial substrate and four grooves.
Described second groove 205 is formed in Cutting Road district 202, after subsequent technique forms fourth groove identical with shape with described second groove 205 position in the Cutting Road district of epitaxial substrate, described 4th groove can in completing the scribing process after semiconductor device manufactures, together with the Cutting Road district of epitaxial substrate cut, thus without affecting device performance.
In the present embodiment, the crystal orientation of described first groove 204 sidewall is parallel with the wafer notch crystal orientation of described test substrate 200, and therefore the crystal face of described first groove 204 sidewall surfaces is (110)；And follow-up the 3rd grooved position being formed in epitaxial substrate device region and shape are identical with described first groove 204, therefore the crystal orientation of described 3rd trenched side-wall and the wafer notch crystal orientation of epitaxial substrate are parallel, and the crystal orientation of its sidewall surfaces is (100)；The crystal face causing described test substrate 200 sidewall deflects 45 degree of angles relative to the crystal face of described epitaxial substrate sidewall.
Crystal face due to the 3rd trenched side-wall that subsequent technique is formed, 45 degree of angles of crystal face deflection relative to the sidewall of described test substrate 200 first groove 204, when the sidewall crystal face of described second groove 205 also deflects 45 degree of angles relative to described first groove 204, the sidewall of described second groove 205 is identical with the crystal face of the 3rd trenched side-wall being subsequently formed in the substrate of outer and bottom with the crystal face of bottom, trenched side-wall is also identical with the surface covalent bond density of bottom, wherein, the shape of described 3rd groove is consistent with described first groove 204 with position；Therefore, adopt the oxidated layer thickness that identical thermal oxidation technology is formed in described second groove 205 with the 3rd groove identical, thus the follow-up technique forming the second oxide layer reaching design standard thickness in described second groove 205, it is possible to it is applied to follow-up formation oxide layer in the 3rd groove.
Refer to Figure 10, Figure 11 and Figure 12, Figure 11 is Figure 10 cross-sectional view on AA ' direction, Figure 12 is Figure 10 cross-sectional view on BB ' direction, adopting thermal oxidation technology to form the first oxide layer 206 in sidewall and the lower surface of described first groove 204, sidewall and lower surface at described second groove 205 form the second oxide layer 207；Test the thickness of described second oxide layer 207, when the thickness of described second oxide layer 207 reaches preset thickness, obtain the formation process parameter of described second oxide layer 207.
Described first oxide layer 206 is as the gate dielectric layer of the trench transistor formed in described test substrate 200, and described second oxide layer 207 is for simulating the follow-up technique forming the 3rd oxide layer in the 3rd groove of epitaxial substrate.
Owing to the crystal face of described second groove 205 sidewall deflects 45 degree of angles relative to the crystal face of described first groove 204 sidewall, therefore the described sidewall of the second groove 205 and the atomic density of lower surface are different from described first groove 204, when adopting thermal oxidation technology to form the first oxide layer 206 and the second oxide layer 207, described first oxide layer 206 is different with the oxidation rate of the second oxide layer 207, and the oxidated layer thickness that the identical time is formed is different.
As shown in figure 11, it is in the cross-sectional view of described first groove 204 of device region 201, as shown in figure 12, is in the cross-sectional view of described second groove 205 in Cutting Road district 202；In the present embodiment, owing to the sidewall crystal face of described second groove 205 has deflected 45 degree of angles relative to described first groove 204, therefore the covalent bond density of described first groove 204 sidewall (110) crystal face is more than the covalent bond density of described second groove 205 sidewall (100) crystal face；When the first oxide layer 206 adopting thermal oxidation technology to concurrently form and the second oxide layer 207, (110) speed of growth of the thermal oxide layer of crystal face is more than (100) crystal face, therefore, when the growth adopting identical technological parameter to carry out gate oxide, the thickness of described first oxide layer 206 is more than the thickness of described second oxide layer 207.
Owing to described second groove 205 sidewall is identical with the indices of crystallographic plane of the 3rd trenched side-wall being subsequently formed in epitaxial substrate and lower surface with the bottom indices of crystallographic plane, therefore adopt the oxidated layer thickness that identical thermal oxidation technology is formed in described second groove 205 with the 3rd groove identical；When described second oxide layer 207 meets the design standard thickness of gate dielectric layer, the parameters of obtained thermal oxidation technology is applied to the oxide layer being subsequently formed in the 3rd groove, the oxide layer formed also is able to meet the thickness of design standard, thus ensureing that the gate dielectric layer thickness of trench transistor is controlled, the stable performance of the trench transistor formed.
After forming described second oxide layer 207, testing the thickness of described second oxide layer 207, the step of described test thickness is: described second oxide layer 207 is cut into slices；Section measurement to described second oxide layer 207 section, obtains the thickness of described second oxide layer 207.
Described preset thickness designs standard thickness for trench transistor gate dielectric layer, and its thickness range is 100 angstroms to 1000 angstroms；The parameter of described thermal oxidation technology includes: reacting gas, response time and reaction temperature；When the thickness of described second oxide layer 207 reaches described preset thickness, the parameters of the thermal oxidation technology that record adopted at that time, and use when subsequent technique forms the oxide layer in the 3rd groove.
It should be noted that, after forming described first oxide layer 206 and the second oxide layer 207, in described first groove 204, form the first gate electrode layer (not shown) filling full described first groove 204, in described second groove 205, form the second gate electrode layer (not shown) filling full described second groove 205；The material of described first gate electrode layer and second gate electrode layer is polysilicon, obtains the technological parameter forming described first gate electrode layer and second gate electrode layer.
So far, the trench transistor being formed at test substrate 200 completes, and obtains the complete process flow that can form the trench transistor meeting design standard in follow-up outer substrate.
Refer to Figure 13, epitaxial substrate 300 is provided, the edge of described epitaxial substrate 300 has wafer notch (not shown), the crystal orientation of the wafer notch of described epitaxial substrate 300 becomes 45 degree of angles relative to the crystal orientation of test substrate 200 wafer notch, described epitaxial substrate 300 has some device regions 301, between described adjacent devices district 301, there is Cutting Road district 302, described epitaxial substrate 300 surface has the second photoresist layer 303, and the shape of described second photoresist layer 303 is identical with the shape of described first photoresist layer 203.
Described outer substrate 300 is used for being formed trench transistor, and described epitaxial substrate 300 includes silicon substrate and is positioned at the epitaxial layer of described surface of silicon；The forming method of described epitaxial substrate 300 is: adopt epitaxial deposition process to form epitaxial layer in surface of silicon；It follows that described epitaxial substrate 300 is costly, it is unsuitable for being formed in the technological process of trench transistor in simulation using；In the present embodiment, the crystal orientation of epitaxial substrate 300 wafer notch becomes 45 degree of angle angles relative to the crystal orientation of test substrate 200 wafer notch, for<100>, thus the 3rd trenched side-wall crystal face in the epitaxial substrate 300 being subsequently formed also becomes 45 degree of angles relative to the sidewall crystal face of the first groove 204 in test substrate.
The wafer notch of described epitaxial substrate 300 is in described epitaxial substrate 300 edge, and it is perpendicular to the cutting mouth on described epitaxial substrate 300 surface, for determining the direction of described epitaxial substrate 300 in the technological process of each road, and make the described epitaxial substrate 300 cannot be arbitrarily mobile；The crystal orientation of described wafer notch is identical with by the diameter wafer direction of described wafer notch.
The formation process of described second photoresist layer 303 with formed described first photoresist layer 203 time identical, when described second photoresist layer 303 is exposed, adopt the first mask blank when forming described first photoresist layer 203, thus the correspondence position of the 3rd groove and the first groove 204 are identical in the device region 301 that exposes of described second photoresist layer 303, in the Cutting Road district 302 exposed, the position of the 4th groove is identical with described second groove 205.
Refer to Figure 14, adopt the technological parameter forming described first groove 204 and the second groove 205, with described second photoresist layer 303 for epitaxial substrate 300 described in mask etching, forming some the 3rd grooves 304 being parallel to each other in the device region 301 of described epitaxial substrate 300, in the Cutting Road district of described epitaxial substrate 300,302 form some the 4th grooves 305 being parallel to each other.
Described 3rd groove 304 and the position of the 4th groove 305 and formation process and described first groove 204 and the second groove 205 are identical；In the present embodiment, with described second photoresist layer 303 for mask, adopt epitaxial substrate 300 described in anisotropic dry etching, form described 3rd groove 304 and the 4th groove 305；The bottom of described 3rd groove 304 and the 4th groove 305 is being carried out isotropic dry etch process, is making bottom to epitaxial substrate 300 sunken inside, and surface is round and smooth.
Described 3rd groove 304 is used for being formed trench transistor, described 4th groove 305 is formed at Cutting Road district 302, and described Cutting Road district 302 is after the follow-up manufacture completing semiconductor device, can be cut in scribing process, therefore described 4th groove 305 can be removed together with Cutting Road district 302, from without the semiconductor device ultimately formed is impacted.
Refer to Figure 15, Figure 16 and Figure 17, Figure 16 is Figure 15 cross-sectional view on CC ' direction, Figure 17 is Figure 15 cross-sectional view on DD ' direction, thermal oxidation technology is adopted to form the 3rd oxide layer 306 in sidewall and the lower surface of described 3rd groove 304, sidewall and lower surface at described 4th groove 305 form the 4th oxide layer 307, and the parameter of described thermal oxidation technology is identical with the technological parameter of the second oxide layer 207 forming preset thickness.
Described formation the 3rd oxide layer 306 is identical with the technique of the second oxide layer 207 forming preset thickness with the thermal oxidation technology of the 4th oxide layer 307, the thickness of the 3rd oxide layer 306 formed is preset thickness, therefore meets the designing requirement of the gate dielectric layer of trench transistor.
When the crystal orientation of described epitaxial substrate 300 wafer notch becomes 45 degree of angles relative to the crystal orientation of described test substrate 200 wafer notch, and the crystal orientation of the second groove 205 sidewall being formed at test substrate 200 is when also deflecting 45 degree of angles relative to described first groove 204, owing to described 3rd groove 304 is positioned at the position of described epitaxial substrate 300, and be positioned at the position testing substrate 200 with described first groove 204 identical, therefore the crystal orientation of described second groove 205 sidewall and lower surface, identical with the crystal orientation of described 3rd groove 304 sidewall and lower surface；Therefore, adopt the 3rd oxide layer 306 in the second oxide layer 207 thickness and the 3rd groove 304 that identical thermal oxidation technology formed in described second groove 205 identical.
Due to known in the second groove 205, form preset thickness time thermal oxidation technology parameter, the thickness adopting the 3rd oxide layer 306 that described technological parameter formed also is preset thickness；And described preset thickness meets the design standard of gate dielectric layer, the 3rd oxide layer 306 formed is as the gate dielectric layer of trench transistor, the thickness of the trench transistor gate dielectric layer therefore ultimately formed meets design standard, makes the stable performance of the trench transistor formed.
It should be noted that after forming the 3rd oxide layer 306 and the 4th oxide layer 307, adopt the technique forming first gate electrode layer and second gate electrode layer, form the 3rd gate electrode layer and the 4th gate electrode layer of filling full described 3rd groove 304 and the 4th groove 305.
After the manufacture of the semiconductor device completed in device region 301, described epitaxial substrate 300 being cut, remove Cutting Road district 302 part, described 4th groove 305 and described 4th oxide layer 307, in above-mentioned scribing processes, are removed simultaneously.
In the method for the control trench transistor gate dielectric layer thickness of the present embodiment, form the crystal orientation of sidewall in the Cutting Road district of test substrate and deflect second groove at 45 degree of angles relative to the first groove, in described second groove, form the second oxide layer meeting gate dielectric layer thickness calibration, and in the 3rd groove in substrate devices district, outer, form the 3rd oxide layer with the formation process of described second oxide layer；Owing to described 3rd groove is identical with the crystal face of described its sidewall of second groove and lower surface, adopt the oxidated layer thickness that identical thermal oxidation technology is formed identical；Therefore by the thickness of gate oxide in technical arrangement plan test substrate the second groove, reach requirement on devices, thus adopting formation the 3rd oxide layer of same process parameter to also comply with gate dielectric layer thickness calibration, and described 3rd oxide layer is as the gate dielectric layer of the trench transistor of required formation, so that the control of the trench transistor gate dielectric layer thickness formed is more accurate, testing cost is lower, and the trench transistor formed is functional.
In sum, in the Cutting Road district of test substrate, form the second groove, adopt thermal oxidation technology to form the second oxide layer in sidewall and the lower surface of described second groove, and when the thickness of described second oxide layer reaches preset thickness, record technological parameter；And in the 3rd groove, form the 3rd oxide layer with described technological parameter, described 3rd groove is formed in the device region of epitaxial substrate, and position in the device region of test substrate of position and shape and the first groove and shape identical；Owing to the crystal orientation of described epitaxial substrate wafer notch becomes 45 degree of angles relative to the crystal orientation of test substrate wafer notch, therefore the crystal face of the 3rd trenched side-wall becomes 45 degree of angles relative to the crystal face of described first trenched side-wall；When the crystal orientation of described second trenched side-wall deflects 45 degree of angles relative to the crystal orientation of described first trenched side-wall, the described sidewall of the second groove is identical with the indices of crystallographic plane of the 3rd groove with the indices of crystallographic plane of lower surface, the sidewall of described second groove is also identical with the covalent bond density of the sidewall of described 3rd groove and lower surface with the covalent bond density of lower surface, therefore adopts the second oxide layer that identical thermal oxidation technology is formed identical with the 3rd oxidated layer thickness；When forming the second oxide layer reaching preset thickness in the second groove testing substrate, record thermal oxidation technology parameter at that time, and in the 3rd groove, forming the 3rd oxide layer with identical thermal oxidation technology, the 3rd oxide layer formed can reach preset thickness too；Control and the adjustment of the gate dielectric layer thickness of the epitaxial substrate device region formed when described 3rd oxide layer is as the gate dielectric layer of trench transistor can be more accurate, lower in cost, and the device performance of formation is more preferably.
Although the present invention is with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; may be by the method for the disclosure above and technology contents and technical solution of the present invention is made possible variation and amendment; therefore; every content without departing from technical solution of the present invention; according to any simple modification, equivalent variations and modification that above example is made by the technical spirit of the present invention, belong to the protection domain of technical solution of the present invention.
Claims (17)
1. the method controlling trench transistor gate dielectric layer thickness, it is characterised in that including:
Thering is provided test substrate, described test substrate has some device regions, has Cutting Road district between adjacent described device region, and the edge of described test substrate has wafer notch；
Some the first grooves being parallel to each other are formed in the device region of described test substrate, in the Cutting Road district of described test substrate, form some the second grooves being parallel to each other simultaneously, the crystal orientation of described second trenched side-wall deflects 45 degree of angles relative to the crystal orientation of described first trenched side-wall, when the shape of described first groove reaches preset shape, obtain the technological parameter forming described first groove；
Thermal oxidation technology is adopted to form the first oxide layer in sidewall and the lower surface of described first groove, sidewall and lower surface at described second groove concurrently form the second oxide layer, when the thickness of described second oxide layer reaches preset thickness, obtain the formation process parameter of described second oxide layer；
Thering is provided epitaxial substrate, described epitaxial substrate has some device regions, and the edge of described epitaxial substrate has wafer notch, and the crystal orientation of described epitaxial substrate wafer notch becomes 45 degree of angles relative to the crystal orientation of test substrate wafer notch；
Adopt the technological parameter of described first groove, in the device region of described epitaxial substrate, form some the 3rd grooves being parallel to each other；
Adopting thermal oxidation technology to form the 3rd oxide layer in sidewall and the lower surface of described 3rd groove, the parameter of described thermal oxidation technology is identical with the technological parameter of the second oxide layer forming preset thickness.
2. the method controlling as claimed in claim 1 trench transistor gate dielectric layer thickness, it is characterised in that be 100 angstroms～1000 angstroms in described preset thickness.
3. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 1, it is characterized in that, the preset shape of described first groove includes: the degree of depth of described first groove is 0.8～2 micron, and the bottom of described first groove is round and smooth to test substrate sunken inside and surface.
4. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 1, it is characterised in that the forming step of described first groove and the second groove is: with the first mask blank, forms the first photoresist layer at test substrate surface；With described first photoresist layer for mask, adopt etching technics to form some the first grooves being parallel to each other in the device region of described test substrate simultaneously, in the Cutting Road district of described test substrate, form some the second grooves being parallel to each other.
5. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 4, it is characterised in that the step of described 3rd groove is: with the first mask blank, form the second photoresist layer at extension substrate surface；With described second photoresist layer for mask, etching technics is adopted to form some the 3rd grooves being parallel to each other in the device region of described epitaxial substrate；While forming described 3rd groove, in the Cutting Road district of described epitaxial substrate, form some the 4th grooves being parallel to each other.
6. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 4, it is characterised in that the technological parameter of described first groove includes: the position of etching gas, etch period, etching bias and described first groove.
7. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 1, it is characterised in that the technological parameter of the second oxide layer of described formation preset thickness includes: reacting gas, response time and reaction temperature.
8. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 1, it is characterised in that the step obtaining described second oxidated layer thickness is: described second oxide layer is cut into slices；Section measurement to described second oxide layer section, obtains the thickness of described second oxide layer.
9. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 1, it is characterized in that, also include: after forming the first oxide layer and the second oxide layer, in described first groove, form the first gate electrode layer filling full described first groove, in described second groove, form the second gate electrode layer filling full described second groove；Obtain being formed the technological parameter of described first gate electrode layer and second gate electrode layer.
10. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 9, it is characterized in that, to form the technological parameter of described first gate electrode layer and second gate electrode layer, in described 3rd groove, form the 3rd gate electrode layer filling full described 3rd groove.
11. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 10, it is characterised in that the material of described first gate electrode layer, second gate electrode layer and the 3rd gate electrode layer is polysilicon.
12. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 1, it is characterised in that described epitaxial substrate also includes: the Cutting Road district between adjacent devices district.
13. the method controlling as claimed in claim 1 trench transistor gate dielectric layer thickness, it is characterised in that described epitaxial substrate includes: silicon substrate and be positioned at the epitaxial layer of described surface of silicon.
14. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 1, it is characterised in that described test substrate is silicon substrate.
15. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 1, it is characterised in that the crystal orientation of the wafer notch of described test substrate or epitaxial substrate is identical with by the diameter wafer direction of described wafer notch.
16. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 15, it is characterised in that the notch crystal orientation of described epitaxial substrate is<100>.
17. the method controlling trench transistor gate dielectric layer thickness as claimed in claim 15, it is characterised in that the notch crystal orientation of described test substrate is<110>.
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| CN1893111A (en) * | 2005-05-12 | 2007-01-10 | 谢福渊 | Elimination of gate oxide weak spot in deep trench |
| CN102280384A (en) * | 2011-07-05 | 2011-12-14 | 上海宏力半导体制造有限公司 | Process for manufacturing power trench type MOSFET |
| TW201218258A (en) * | 2010-09-30 | 2012-05-01 | Toshiba Kk | Triple oxidation on DSB substrate |
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| KR100845051B1 (en) * | 2006-04-28 | 2008-07-09 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with recess gate |
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| CN1893111A (en) * | 2005-05-12 | 2007-01-10 | 谢福渊 | Elimination of gate oxide weak spot in deep trench |
| TW201218258A (en) * | 2010-09-30 | 2012-05-01 | Toshiba Kk | Triple oxidation on DSB substrate |
| CN102280384A (en) * | 2011-07-05 | 2011-12-14 | 上海宏力半导体制造有限公司 | Process for manufacturing power trench type MOSFET |
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