CN102768858B - A kind of memory body - Google Patents
A kind of memory body Download PDFInfo
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- CN102768858B CN102768858B CN201110120754.7A CN201110120754A CN102768858B CN 102768858 B CN102768858 B CN 102768858B CN 201110120754 A CN201110120754 A CN 201110120754A CN 102768858 B CN102768858 B CN 102768858B
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Abstract
The invention relates to a kind of memory body, is a kind of Sheffer stroke gate memory storage comprising Sheffer stroke gate memory cell tandem, and wherein each memory cell comprises a charge trapping structure and is formed on a light doped substrate region.One of this Sheffer stroke gate memory cell is chosen memory cell and can be arranged in pairs or groups by the relatively low programming voltage of applying one and previous applied setting voltage and in addition sequencing, and this setting voltage is applied to substrate and initialization reversion.Reversion in substrate causes becoming thermoelectron being contained in the electronics chosen in memory cell passage.Consequently, the thermoelectron that relatively low programming voltage can make the grid choosing memory cell have enough energy is chosen in the charge trapping structure of memory cell with tunneling entering.
Description
Technical field
The present invention relates to a kind of fast-flash memory body technique, particularly relate to a kind of in Sheffer stroke gate configuration the suitable fast flash memory bank as low-voltage sequencing and erase operation.
Background technology
Fast flash memory bank is the one of non-volatile ic memory technology.Traditional fast flash memory bank uses floating grid memory cell.Along with the density of memory storage promotes, exceed between floating grid memory cell and add close, namely the electric charge reciprocal effect be stored in adjacent floating grid can throw into question, and therefore forms restriction, makes to adopt the fast-flash memory volume density of floating grid to promote.The memory cell that another kind of fast flash memory bank uses is called charge-trapping memory cell, and it adopts electric charge capture layer to replace floating grid.Charge-trapping memory cell utilizes charge trapping material, can not cause influencing each other between individual memory born of the same parents, and can be applied to highdensity fast flash memory bank as floating grid.
Typical charge storage memory cell comprises a field-effect transistor (FET) structure, wherein comprise the source electrode and drain electrode separated by passage, and by a charge storing structure with the grid of channel separation, wherein this charge storing structure comprise tunneling dielectric layer, electric charge storage layer (floating grid or dielectric layer), with barrier dielectric layer.Traditional design comparatively is early as SONOS device, wherein source electrode, drain electrode and passage are formed on silicon substrate (S), tunneling dielectric layer is then formed by monox (O), electric charge storage layer is formed (N) by silicon nitride, barrier dielectric layer is formed by monox (O), and grid is then polysilicon (S).
Flash memory device usually can use Sheffer stroke gate (NAND) or rejection gate (NOR) framework applies, but can be also other framework, comprises and door (AND) framework.Wherein Sheffer stroke gate (NAND) framework is special is favored because of the advantage of its high density in data storage application aspect and high speed.Rejection gate (NOR) framework is then suitable for being such as in other application such as law of procedure storage, because random access is important functional requirement.In a Sheffer stroke gate (NAND) framework, it is tunneling that programmed process normally relies on Fu Le-Nuo get Han (FN), and need high voltage, normally in 20 voltage magnitudes, and needs high voltage transistor to process.This extra high voltage transistor and collocation are used in the transistor of logic and other data streams in same integrated circuit, and the complicacy of technique can be caused to increase.Like this then the manufacturing cost of this device can be increased.
As can be seen here, above-mentioned existing fast flash memory bank with in use in structure, obviously still has inconvenience and defect, and is urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development, and common product does not have appropriate structure to solve the problem, this is obviously the anxious problem for solving of relevant dealer always.Therefore how to found a kind of memory body of new structure, to utilize low-voltage to get final product programming operations in Sheffer stroke gate (NAND) framework, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
The object of the invention is to, overcome the defect that existing fast flash memory bank exists, and a kind of memory body of new structure is provided, technical matters to be solved makes it in Sheffer stroke gate (NAND) framework, utilize low-voltage to get final product programming operations, is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of memory body that the present invention proposes, comprise multiple memory cell serial arrangement in semiconductor main body; Many character lines, the memory cell that each the character line in these many character lines is corresponding with the plurality of memory cell couples; And the control circuit to couple with this many character lines.This control circuit be applicable to choose with one in the plurality of memory cell of sequencing character line corresponding one choose memory cell.This sequencing is by one to setting voltage of one first and 1 second end of the plurality of memory cell of bias voltage; Reduction is applied to the voltage class of this one of this first and second end of the plurality of memory cell from this setting voltage to one bit line programming voltage; Apply a forward voltage to the character line do not chosen corresponding to memory cell; And apply a programming voltage to this choose corresponding to memory cell this choose character line.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory body, wherein said semiconductor body comprises a light doped substrate region.The doping content in this light doped substrate region is less than or equal to 5x10
12cm
-2.This light doped substrate region comprises a N-type state doped region.
Aforesaid memory body, wherein each memory cell comprises a respective charge trapping structure.This charge trapping structure can be formed on a light doped substrate region.This charge trapping structure comprises respective passage oxide layer, and the thickness of each passage oxide layer is less than 90 dusts.
Aforesaid memory body, is wherein applied to this this programming voltage choosing character line and is less than or equal to 17 volts.This forward voltage is between 3-8 volt range.
Aforesaid memory body, wherein applies the reversion that this setting voltage causes in this semiconductor body.
Aforesaid memory body, wherein the plurality of memory cell of bias voltage first and one second the step of one of end be carry out in a very first time interval, and the step wherein reducing this voltage class, apply this forward voltage and apply this programming voltage is carried out in one second time interval behind this very first time interval.
Aforesaid memory body, wherein carry out the plurality of memory cell of bias voltage first and one second end one while apply a ground voltage class to the plurality of memory cell first and one second end another one and to each in these many character lines.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to the present invention propose a kind of memory body, comprise there is multiple memory cell one first tandem serial arrangement in semiconductor main body; There is one second tandem serial arrangement of multiple memory cell in this semiconductor body; Many character lines, one of one of this first tandem memory cell respective in each the character line in these many character lines and the plurality of memory cell and this second tandem memory cell couple; And the control circuit to couple with this many character lines.This control circuit be applicable to choose with one in this first tandem of sequencing character line corresponding one choose memory cell.This sequencing can be reached by following steps: apply the one of a bit line programming voltage to one first and 1 second end in this first tandem memory cell; Maintain this first and second both end in this second tandem memory cell in this ground voltage class; Apply a forward voltage to the character line do not chosen corresponding to memory cell; And apply a programming voltage to this choose corresponding to memory cell this choose character line.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory body, wherein said semiconductor body comprises a light doped substrate region.The doping content in this light doped substrate region is less than or equal to 5x10
12cm
-2.This light doped substrate region comprises a N-type state doped region.
Aforesaid memory body, wherein each memory cell comprises a respective charge trapping structure.This charge trapping structure can be formed on a light doped substrate region.This charge trapping structure comprises respective passage oxide layer, and the thickness of each passage oxide layer is less than 90 dusts.
Aforesaid memory body, is wherein applied to this this programming voltage choosing character line and is less than or equal to 17 volts.This forward voltage is between 3-8 volt range.
Aforesaid memory body, wherein applies the reversion that a setting voltage causes in this semiconductor body.
Aforesaid memory body, wherein said control circuit further configuration is, in a very first time interval in this first tandem memory cell of bias voltage first and one second one to setting voltage of end, and first and second both the end in each and this second tandem memory cell of simultaneously applying in a ground voltage class to the another one, these many character lines of first in this first tandem memory cell and one second end.Applying this bit line programming voltage, maintaining this first and second both end in this second tandem memory cell in this ground voltage class, the step that applies this forward voltage and apply this programming voltage is all carry out in one second time interval behind this very first time interval.
Aforesaid memory body, wherein apply this bit line programming voltage comprise reduce this one being applied to this first and second end in this first tandem memory cell voltage class from a setting voltage to this bit line programming voltage.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, memory body of the present invention at least has following advantages and beneficial effect: memory body of the present invention can utilize low-voltage to get final product programming operations in Sheffer stroke gate (NAND) framework.
In sum, the invention relates to a kind of memory body, is a kind of Sheffer stroke gate memory storage comprising Sheffer stroke gate memory cell tandem, and wherein each memory cell comprises a charge trapping structure and is formed on a light doped substrate region.One of this Sheffer stroke gate memory cell is chosen memory cell and can be arranged in pairs or groups by the relatively low programming voltage of applying one and previous applied setting voltage and in addition sequencing, and this setting voltage is applied to substrate and initialization reversion.Reversion in substrate causes becoming thermoelectron being contained in the electronics chosen in memory cell passage.Consequently, the thermoelectron that relatively low programming voltage can make the grid choosing memory cell have enough energy is chosen in the charge trapping structure of memory cell with tunneling entering.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of instructions, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A and Figure 1B shows to use one of traditional programming operations bias voltage to choose the diagrammatic cross-section that Sheffer stroke gate tandem and does not choose Sheffer stroke gate tandem respectively.
Fig. 1 C is the simplified diagram of the Sheffer stroke gate tandem of display shown in Figure 1A and Figure 1B.
Fig. 2 A is the sectional view of display according to a Sheffer stroke gate fast-flash memory tandem part for the embodiment of the present invention.
Fig. 2 B is the schematic diagram of display according to the Sheffer stroke gate fast-flash memory tandem of the embodiment of the present invention.
The time diagram of one example of its operation signal when Fig. 3 is the programming operations of the Sheffer stroke gate tandem of display Fig. 2 A and Fig. 2 B.
Fig. 4 A and Fig. 4 B is the schematic diagram of the example of display routine voltage and passage oxidated layer thickness, and it can be used as the application-specific of device shown in Fig. 2 A and Fig. 2 B.
Fig. 4 C is the schematic cross sectional schematic diagram of the memory cell of display one embodiment, and it demonstrates the enlarged drawing of the charge trapping structure of an example.
Fig. 5 be display traditional Sheffer stroke gate memory tandem distribute with character line WL0 of the present invention compare schematic diagram.
Fig. 6 is the schematic diagram that can be with that how injection of hot carrier occurs when programming operations in display the present invention.
Fig. 7 is the result of display experimental data, and how display reaches the schematic diagram that enough critical voltage Vt difference makes to allow to determine whether a memory cell is programmed or wipes.
Fig. 8 is the block diagram of the integrated circuit can applying hot carrier injecting program Sheffer stroke gate fast flash memory bank described in the invention.
7,8: gate dielectric layer
9: charge trapping structure
10: semiconductor body
11,19: contact
12-18: node
21: ground connection selects line GSL
22-27: character line
28: tandem selects line SSL
30: common source line CS
31: bit line
32: do not choose bit line
40: light doped substrate region
101,103: Sheffer stroke gate tandem
210: integrated circuit
212: Sheffer stroke gate fast flash memory bank
214: character line/tandem selective decompression device and driver
216: character line
218: bit line demoder
220: bit line
222,226: bus
224: sensing amplifier/data input structure
234: controller (hot carrier injecting program, FN wipe)
236: bias voltage adjustment supply voltage
228: data input line
230: other circuit
232: data output line
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of a kind of memory body proposed according to the present invention, structure, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, should to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the present invention.
Figure 1A and Figure 1B shows to use one of traditional programming operations bias voltage to choose the diagrammatic cross-section that Sheffer stroke gate tandem and does not choose Sheffer stroke gate tandem respectively.Wherein multiple charge-trapping flash memory cell is cascaded and becomes Sheffer stroke gate tandem, and carries out the bias voltage of the tunneling sequencing of FN, and it is the typical operation in Sheffer stroke gate fast flash memory bank framework.Fig. 1 C is the simplified diagram of the Sheffer stroke gate tandem of display shown in Figure 1A and Figure 1B.
Figure 1A shows and comprises to one target memory born of the same parents (the memory cell A in Fig. 1 C) choose the Sheffer stroke gate tandem on bit line bias voltage schematic diagram one, and Figure 1B shows the bias voltage schematic diagram being positioned at the Sheffer stroke gate tandem do not chosen on bit line to.Use energy gap engineering SONOS charge-trapping technology can consult No. 7315474th, the United States Patent (USP) of Lue with the technology implementing Sheffer stroke gate fast flash memory bank, it is incorporated by reference data at this.Sheffer stroke gate tandem can use many different configurations to implement, and comprises FINFET technology, shallow trench isolation technology, vertical Sheffer stroke gate technology etc.The example of some vertical Sheffer stroke gate structure, refers to No. EP2048709th, the European patent that people's titles such as Kim are " Non-volatilememorydevice, methodofoperatingsameandmethodoffabricatingthesame ".
Refer to shown in Figure 1A, this memory cell is formed in semiconductor main body 10.For n passage memory cell, semiconductor body 10 can be the p well of an isolation in the darker n well of semiconductor wafer.Alternatively, semiconductor body 10 can by insulation course or other similarly mode isolate.Some embodiment can use p passage memory cell, and the doping wherein in semiconductor body 10 is N-shaped.
Multiple flash memory cell can be arranged to the tandem arranged along a bit line direction orthogonal with character line direction.Character line 22-27 is along stretching by some parallel Sheffer stroke gate tandems.Node 12-18 is by the n-type region (for n lane device) in semiconductor body, and as the source/drain region of memory cell.First change-over switch formed by metal oxide semiconductor transistor has a grid and selects in line GSL21 in ground connection, and it is connected between the corresponding memory cell with the first character line 22 (WL0 in Fig. 1 C) and the contact 11 formed by the n-type region in semiconductor body 10.This contact 11 together source line CS30 connects.Second change-over switch formed by metal oxide semiconductor transistor has a grid and selects in line SSL28 in tandem, and it is connected between the corresponding memory cell with last character line 27 and the contact 19 formed by the n-type region in semiconductor body 10.This contact 19 is connected with bit line BL31.First and second change-over switch in this illustrative embodiments is metal oxide semiconductor transistor, has the gate dielectric layer 7 and 8 of silicon dioxide in this example.
In this illustrates, for simplicity there are in this tandem six memory cells.In typical configuration, Sheffer stroke gate tandem can comprise 16,32 or more a memory cell serial arrangement.Character line 22-27 corresponding to these memory cells has charge trapping structure 9 in character line and semiconductor body 10 between passage area.Charge trapping structure 9 in this memory cell can be dielectric charge catch structure, floating gate charge capturing structure or other are suitable for the fast-flash memory body structure using technology described herein to carry out sequencing.In addition, in the embodiment of Sheffer stroke gate flash structures, develop the form not having junction, its interior joint 13-17, and optionally comprise node 12 and 18 and can omit in structure since then.
Figure 1A shows the sectional view of Sheffer stroke gate (NAND) the structural flash memory body of an existing known techniques, and it is that to bring out FN tunneling with the schematic diagram of the bias voltage memory cell corresponding with character line 24 being carried out to sequencing.According to bias voltage shown herein, ground connection selects line GSL to be biased into be approximately 0V and common source line ground connection, the first change-over switch selecting line GSL21 corresponding with ground connection is made to be close, and tandem selects that line SSL is biased into about VCC and selected bit line is also ground connection, the second change-over switch selecting line SSL28 corresponding with tandem is made to be open.Under these conditions, the semiconductor body in relevant to Sheffer stroke gate tandem region 33 is precharged to about 0V.This chooses character line 24 and is biased to a high voltage sequencing class V-PGM, in certain embodiments can up to the order of magnitude of 20-22 volt.The thermoelectron in main body 10 is tunneling to be entered in the charge trapping structure 9 of selected memory cell to select so high voltage to be enough to cause.Meanwhile, do not choose character line 22,23,25-27 is biased to a forward voltage V-PASS, it is also less than than V-PGM the voltage that one can be suppressed the sequencing not choosing memory cell in this tandem.For example, the grid of memory cell C receives forward voltage V-PASS from character line 25, although and memory cell C has the body region being set to sequencing, this low forward voltage V-PASS is still enough to the programmed process disturbing memory cell C.
Figure 1B shows the sectional view of Sheffer stroke gate (NAND) the structural flash memory body of an existing known techniques, and it is the bias voltage schematic diagram Sheffer stroke gate tandem sharing character line 22-27 in Figure 1A not being chosen to bit line.Can find by figure, all character lines, ground connection select line GSL to select line SSL all identical with the bias voltage shown in Figure 1A with tandem.Similarly, common source line 30 is also ground connection.But the bit line do not chosen is biased into the class being about VCC.So the second change-over switch can be closed, its and tandem select line SSL corresponding, and the semiconductor body in region 35 and the bit line BL32 that do not choose are removed and couple.Consequently, the semiconductor body in region 35 can by being applied to the capacitive coupling oneself voltage rise that character line 22-27 voltage produces, and it can prevent from being enough to disturb the electric field of charge trapping structure in the memory cell not choosing Sheffer stroke gate tandem to be formed.According to capacitive character oneself voltage rise so-called increase progressively step-by-step impulse sequencing (ISSP) operation be known by industry.
Although the programming operations described in Figure 1A-Fig. 1 C can be efficient, it still has some shortcoming.A problem is that programming voltage class V-PGM needs high voltage class so (such as 20-22 volt).High voltage needs so can be configured to the restriction in design to the semiconductor junction of some memory storage, and make the micro of semiconductor structure become very difficult.
Another problem of traditional programization operation such as described in Figure 1A-Fig. 1 C is that it only allows forward voltage V-PASS variation very among a small circle to prevent interference.On the other hand, if the words that forward voltage V-PASS is too low, then do not have enough capacitance coupling effects to boost to the Sheffer stroke gate tandem of not choosing such as shown in Figure 1B, and the memory cell (the memory cell B in Fig. 1 C) sharing character line with target memory born of the same parents (the memory cell A in Fig. 1 C) can be produced and disturbed.On the other hand, if forward voltage V-PASS is too high, then may produce the injection of hot carrier choosing the memory cell (the memory cell C in Fig. 1 C) of not choosing in Sheffer stroke gate tandem.Consequently, forward voltage V-PASS must control carefully between its up-and-down boundary.For example, typical forward voltage V-PASS scope is between 9-11 volt.So rigorous control can be very difficult because of the factor such as technique or environmental turbulence.
Another problem of traditional programization operation like this is that so-called Gate Induced Drain electric leakage (GIDL) problem sometimes can occur, and for example selects the junction between line GSL and the memory cell of character line WL0 to occur ground connection.This Gate Induced Drain electric leakage (GIDL) problem is difficult to avoid, and can become more serious after device micro.
These and other the shortcoming of tradition Sheffer stroke gate memory storage and programming operations can be overcome by use device and method described in the invention.A kind of Sheffer stroke gate memory storage of improvement can have to be reached with similar Sheffer stroke gate memory cell in Figure 1A and Figure 1B, and wherein each memory cell comprises a charge trapping structure between doped source/drain areas.But Sheffer stroke gate memory cell disclosed herein is preferably formed on light doped substrate region, for example, has doping content and is less than 5 × 10
12cm
-2, be preferably greater than zero and make to have a small amount of impurity.This light doped substrate allows the reversion in low voltage class.Typically, this Sheffer stroke gate memory cell is N-type device, although P type device is perhaps also feasible and can be implemented according to spirit of the present invention by the technician haveing the knack of this skill.Generally speaking, what the present invention disclosed is mainly absorbed in N-type device.In N-type device, regions and source/drain comprises N+ doped region, such as, formed as burying diffusion zone.In situation so, light doped region is the doping of N-type state, so can help electron inversion.
In addition, memory storage disclosed herein and programming operations can allow to reduce programming voltage class V-PGM, and such as programming voltage class V-PGM can be less than or equal to 17 volts.For example, programming voltage class V-PGM can reach between 13V≤V-PGM≤17V.In device described herein and programming operations, channeling potential (Vch) can because low-down substrate doping boosted to programming voltage class V-PGM 0.6 times or 0.7 times.For example, it is approximately 7 or 8V that channeling potential can boost to by the programming voltage of 13V, and it can bring out the storage node that hot carrier injects memory cell.Consequently, can use the forward voltage V-PASS that less, for example, between 3V≤V-PASS≤8V, it can help sup.G to bring out drain leakage (GIDL).In addition, sequencing and read operation can use identical forward voltage V-PASS.
Fig. 2 A and Fig. 2 B is an embodiment of display Sheffer stroke gate quick flashing memory device of the present invention.Fig. 2 A is the sectional view that multiple dielectric charge catch flash memory cell serial arrangement is formed a part for Sheffer stroke gate tandem by display, and Fig. 2 B is the schematic diagram that display comprises the Sheffer stroke gate tandem 101 and 103 of the memory cell shown in Fig. 2 A.
This Sheffer stroke gate tandem 101 and 103 comprises first and second change-over switch, select line GSL and tandem to select line SSL corresponding respectively with ground connection, it is similar to shown in Figure 1A and Figure 1B, each is formed by metal oxide semiconductor transistor, this transistor has grid and is connected between a memory cell and contact, and wherein this contact is formed in semiconductor body 10 by a n-type region and forms.Ground connection in this situation selects line GSL, and this contact can connect by source line CS together; Tandem in this situation selects line SSL, and this contact can be connected with bit line BL.Refer to shown in Fig. 2 A, each memory cell is connected with respective character line WL, such as, character line 23-25 shown in Fig. 2 A.These memory cells each also comprise between the passage area of respective charge trapping structure 9 in character line WL and semiconductor body 10.For n passage memory cell, semiconductor body 10 can be the p well of an isolation in the darker n well of semiconductor wafer.Alternatively, semiconductor body 10 can by insulation course or other similarly mode isolate.Some embodiment can use p passage memory cell, and the doping wherein in semiconductor body 10 is N-shaped.
Multiple flash memory cell is arranged to the tandem arranged along a bit line direction orthogonal with character line direction.Character line WL is along stretching by some parallel Sheffer stroke gate tandems.Being such as the node 14-15 shown in Fig. 2 A, is formed by the n-type region (for n lane device) in semiconductor body 10, and as the source/drain region of memory cell.
In this illustrates, for simplicity there are in this tandem six memory cells.In typical configuration, Sheffer stroke gate tandem can comprise 16,32 or more a memory cell serial arrangement.Character line WL0-WL5 corresponding to these memory cells has charge trapping structure 9 in character line and semiconductor body 10 between passage area.
Must be noted that the memory storage shown in Fig. 2 A can comprise the reversion that light doped substrate region 40 is such as the minority carrier of electronics in N-shaped lane device with erasing.In other words, Umklapp process can occur not having the device in light doped substrate region 40 to compare relative lower voltage class with tradition.Can adulterate the conductivity identical with 15 with source/drain region 14 in this light doped substrate region 40.For example, to a n lane device, this light doped substrate region 40 can be n-doped region.To the embodiment comprising light doped substrate region 40, this light doped region can have doping content and be less than or equal to 5x10
12cm
-2.This light doped region 40 can the known in this way diffusion technique mode of example be formed.
Charge trapping structure 9 in this memory cell can be dielectric charge catch structure, floating gate charge capturing structure or other are suitable for using technology described herein to carry out the fast-flash memory body structure of sequencing.In addition, in the embodiment of Sheffer stroke gate flash structures, developed the form not having junction, its interior joint 13-17, and optionally comprised node 12 and 18 and can omit in structure since then.
Fig. 2 B shows, disclosed by the present invention, multiple dielectric charge catch flash memory cell serial arrangement is formed Sheffer stroke gate tandem 101 and 103, and the schematic diagram of bias voltage during programming operations.In fig. 2b, Sheffer stroke gate tandem 101 chooses memory tandem, and it comprises target memory born of the same parents (memory cell A) on character line WL2 to carry out programming operations.Sheffer stroke gate tandem 103 one does not choose memory tandem and and do not choose bit line BL1 and be connected.Compared with Fig. 1 C, can find that sequencing bit line in fig. 2b and sequencing disturb bit line voltage to be contrary with Fig. 1 C.
The time diagram of one example of its operation signal when Fig. 3 is the programming operations of the Sheffer stroke gate tandem 101 of display Fig. 2 A and Fig. 2 B.More specifically, show in Fig. 3 do not choose character line signal 105, choose character line signal 106, tandem selects line SSL signal 107 and ground connection to select line GSL signal 108.In order to sequencing target memory born of the same parents A, do not choose character line signal 105 to be applied to and not choose character line WL0, WL1 and WL3-WL5, choose character line signal 106 to be applied to and to choose character line WL2, tandem selects line SSL signal 107 to select change-over switch to be applied to substrate from bit line BL0 by tandem, and ground connection selects line GSL signal 108 to select change-over switch to be applied to substrate from common source line CS by ground connection.
When time t0, Sheffer stroke gate tandem 101 is in standby condition, and its signal 105 to 108 is all set as 0V.When time t1 or before, programming operations is by for example according to the initial start by internal command of known memory body control system.When responding, as shown in Figure 2 B, apply the voltage being about Vcc and select line SSL to tandem, open this tandem and select change-over switch, and the voltage of applying≤0V selects line GSL to ground connection, close this ground connection and select change-over switch.When time t1, tandem is selected line SSL signal 107 to comprise a setting pulse 111 and is applied to the substrate choosing Sheffer stroke gate tandem 101 by bit line BL0.This setting pulse 111 exceeds the predetermined value of Vcc mono-, and for example, some voltage range selects the critical voltage < Vcc < of line SSL to set pulse 111 in tandem.A kind of situation that this setting pulse 111 is created is that wherein tandem is selected the drain voltage of change-over switch comparatively grid place is higher, and have the effect in electronics suction passage region, in other words, it chooses this Umklapp process initial in tandem at this.It should be noted that this effect can't occur not choosing tandem 103, wherein bit line BL1 applies 0V.
When time t2, when apply programming voltage to memory cell A choose character line WL2 time, memory cell A near or passage in thermoelectron be pulled in the charge trapping structure 9 of memory cell A.Should be noted that the voltage class in Fig. 3 does not draw to scale, and it must be understood that V-PGM > V-PASS.When time t2, V-PASS is applied to the memory cell do not chosen, but V-PASS is not strong to allowing thermoelectron to overcome to be captured to be such as energy barrier height needed for the charge trapping structure 9 not choosing in memory cell of memory cell B and C.Finally, when time t3, all voltage all gets back to 0V and this programming operations completes.Have the knack of this skill technician should be appreciated that can to choose in some period between t2 and t3 allow reasonable time to make thermoelectron is tunneling to be entered in charge trapping structure 9, and can be such as plant bulk and material according to different factors and change.
Then, refer to shown in Fig. 4 A and Fig. 4 B, these figure are schematic diagram of the example of display routine voltage and passage oxidated layer thickness, and it can be used as the application-specific of device shown in Fig. 2 A and Fig. 2 B.For example, as shown in Figure 4 A, in certain embodiments, the programming voltage of about 17V can as V-PGM, and forward voltage V-PASS is approximately 7-13V.As shown in Figure 4 A, the electronics of significant number is injected into be chosen in the charge trapping structure 9 of memory cell A, and does not choose memory cell B and only have minority.
Fig. 4 C is the schematic cross sectional schematic diagram of the memory cell of display one embodiment, and it demonstrates the enlarged drawing with the example charge trapping structure 9 of character line 24 Associated Memory born of the same parents.Other memory cell and identical shown in Fig. 4 C, so only show a memory cell for simplicity.This charge trapping structure 9 comprises a passage oxide layer 9c and is located immediately on substrate 10, or more specifically, on the light doped region 40 of substrate.Afterwards, a floating grid (charge storage) layer 9b is directly provided on passage oxide layer 9c.One stops that dielectric layer 9a is directly provided on floating-gate 9b.Control gate 24 is located immediately at and stops on dielectric layer 9a.So, for example, this charge trapping structure 9 can use the structure of silicon-oxide-nitride-oxide-silicon (SONOS) to be formed.But, also can use other charge trapping structure.
Fig. 4 B shows programming operations of the present invention and relatively thick passage oxide layer can be allowed valuably to be formed at the charge trapping structure 9 of memory cell shown in Fig. 2 A and Fig. 2 B.For example, the thickness T9c of passage oxide layer 9c can be between the scope of 79 to 91 dusts.Thicker passage oxide layer can need slightly long Programming times (time longer in such as Fig. 3 is between t2 and t3), so preferably T9c thickness is less than 90 dusts.But the memory cell with thicker passage oxide layer can have the advantage of longer holding time, so other thickness also can be used.
Fig. 5 be display traditional Sheffer stroke gate memory tandem distribute with character line WL0 of the present invention compare schematic diagram.As shown in Figure 5, because Sheffer stroke gate quick flashing memory device of the present invention has the lower programming voltage V-PGM of more traditional Sheffer stroke gate memory storage and forward voltage V-PASS voltage class, Sheffer stroke gate quick flashing memory device of the present invention can have the advantage significantly reducing character line WL0 distribution still can be enough to produce hot carrier in this region because eliminating Gate Induced Drain electric leakage (GIDL).
Fig. 6 is the schematic diagram that can be with that display the present invention chooses how the injection of hot carrier occurs when programming operations memory cell A.Must be noted that the electron injection shown by Fig. 6, because it occurs in N-type lane device.Know this skill personage and be appreciated that be hole injection in P type lane device.When programming operations, higher tandem strobe pulse 111 supplies energy to the electronics in substrate, is included in the electronics in light doped substrate region 40.Can interband be tunneling makes Accelerating electron, and these electronics become thermoelectron.Apply programming voltage V-PGM and attract these thermoelectrons, provide enough energy to overcome the energy barrier in passage oxide layer, make injection of hot electrons enter floating grid (FG) layer.
Fig. 7 is the result of display experimental data, and how display reaches the schematic diagram that enough critical voltage Vt difference makes to allow to determine whether a memory cell is programmed or wipes.For example, in the figure 7, can distinguish in erasing memory cell B Self-memory born of the same parents A because critical voltage difference is therebetween approximately 3.5V.
Fig. 8 is the block diagram of the integrated circuit can applying hot carrier injecting program Sheffer stroke gate fast flash memory bank described in the invention.This integrated circuit 210 comprises use charge-trapping or a memory array 212 of floating grid memory cell, and it is formed at for example, on semiconductor substrate.Character line and tandem selective decompression device and driver (comprising suitable driver) 214 select line and ground connection to select line to couple and electrical communication with many character lines 216, tandems, and arrange along the column direction of Sheffer stroke gate fast flash memory bank 212.Bit line (OK) demoder 218 with take bar bit line 220 electrical communication by force and line direction along Sheffer stroke gate fast flash memory bank 212 arrange, to read data or write data from the memory cell of Sheffer stroke gate fast flash memory bank 212 extremely wherein.Address is supplied to character line and tandem selective decompression device and driver 214 and bit line demoder 218 by bus 222.Sensing amplifier in square frame 224 and data input structure, comprise the current source of reading, sequencing and erasing mode, couples via data bus 226 and bit line demoder 218.Data is supplied to data input line 228 by the input/output end port on integrated circuit 210, or by the source of information of other inner/outer of integrated circuit 210, inputs to the data input structure in square frame 224.Other circuit 230 are contained within integrated circuit 210, such as general object processor or specific purposes application circuit, or block combiner is to provide the SoC of being supported by array function.Data, by the sensing amplifier in square frame 224, via data output line 232, is provided to integrated circuit 210, or is provided to other End of Data of integrated circuit 210 inner/outer.
Controller 234 used in the present embodiment, employ bias voltage adjustment state machine, control the application of bias voltage adjustment supply voltage and bias voltage adjustment supply voltage 236, such as reading, sequencing, erasing, erase-verifying and sequencing confirm that voltage or electric current put on character line or bit line, and use the operation of access control Row control character line/source electrode line.This controller also applies switching sequence to bring out hot carrier sequencing described herein.Controller 234 can use the special function logic circuit known by industry to implement.In alternative embodiments, this controller 234 includes general object processor, and it can be used in same integrated circuit, to perform the operation of a computer program and control device.In another embodiment, this controller 234 is combined by specific purposes logical circuit and general object processor.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (22)
1. a memory body, is characterized in that it comprises:
Multiple memory cell serial arrangement is in semiconductor main body;
Many character lines, the memory cell that each the character line in these many character lines is corresponding with the plurality of memory cell couples; And
Control circuit, couples with these many character lines, this control circuit be applicable to by choose with one in the plurality of memory cell of the following step sequencing character line corresponding one choose memory cell:
One to one setting voltage of one first and 1 second end of the plurality of memory cell of bias voltage, applies the reversion that this setting voltage causes in this semiconductor body;
Reduction is applied to the voltage class of this one of this first and second end of the plurality of memory cell from this setting voltage to one bit line programming voltage;
Apply a forward voltage to the character line do not chosen corresponding to memory cell; And
Apply a programming voltage to this choose corresponding to memory cell this choose character line.
2. memory body according to claim 1, is characterized in that wherein said semiconductor body comprises a light doped substrate region.
3. memory body according to claim 2, is characterized in that the doping content in wherein said light doped substrate region is less than or equal to 5 × 10
12cm
-2.
4. memory body according to claim 2, is characterized in that wherein said light doped substrate region comprises a N-type state doped region.
5. memory body according to claim 1, is characterized in that each memory cell in wherein said multiple memory cells comprises a respective charge trapping structure.
6. memory body according to claim 5, is characterized in that wherein said charge trapping structure is formed on a light doped substrate region.
7. memory body according to claim 5, it is characterized in that wherein said charge trapping structure comprises respective passage oxide layer, the thickness of each passage oxide layer is less than 90 dusts.
8. memory body according to claim 1, is characterized in that being wherein applied to this this programming voltage choosing character line is less than or equal to 17 volts.
9. memory body according to claim 8, is characterized in that wherein said forward voltage is between 3-8 volt range.
10. memory body according to claim 1, it is characterized in that the wherein the plurality of memory cell of bias voltage first and one second the step of one of end be carry out in a very first time interval, and the step wherein reducing this voltage class, apply this forward voltage and apply this programming voltage is carried out in one second time interval behind this very first time interval.
11. memory bodys according to claim 1, it is characterized in that wherein carrying out the plurality of memory cell of bias voltage first and one second end one while apply a ground voltage class to the plurality of memory cell first and one second end another one and to each in these many character lines.
12. 1 kinds of memory bodys, is characterized in that it comprises:
There is one first tandem serial arrangement of multiple memory cell in semiconductor main body;
There is one second tandem serial arrangement of multiple memory cell in this semiconductor body;
Many character lines, one of one of this first tandem memory cell respective in each the character line in these many character lines and the plurality of memory cell and this second tandem memory cell couple; And
Control circuit, couples with these many character lines, this control circuit be applicable to choose with one in this first tandem by the plurality of memory cell of the following step sequencing character line corresponding one choose memory cell:
One to one setting voltage of one first and 1 second end in this first tandem memory cell of bias voltage, applies the reversion that this setting voltage causes in this semiconductor body;
Reduce the voltage class of this one of this first and second end be applied in this first tandem memory cell from this setting voltage to one bit line programming voltage; Maintain both one first and 1 second ends in this second tandem memory cell in a ground voltage class;
Apply a forward voltage to the character line do not chosen corresponding to memory cell; And
Apply a programming voltage to this choose corresponding to memory cell this choose character line.
13. memory bodys according to claim 12, is characterized in that wherein said semiconductor body comprises a light doped substrate region.
14. memory bodys according to claim 13, is characterized in that the doping content in wherein said light doped substrate region is less than or equal to 5 × 10
12cm
-2.
15. memory bodys according to claim 13, is characterized in that wherein said light doped substrate region comprises a N-type state doped region.
16. memory bodys according to claim 12, is characterized in that each memory cell in wherein said multiple memory cells comprises a respective charge trapping structure.
17. memory bodys according to claim 16, is characterized in that wherein said charge trapping structure is formed on a light doped substrate region.
18. memory bodys according to claim 16, it is characterized in that wherein said charge trapping structure comprises respective passage oxide layer, the thickness of each passage oxide layer is less than 90 dusts.
19. memory bodys according to claim 12, is characterized in that being wherein applied to this this programming voltage choosing character line is less than or equal to 17 volts.
20. memory bodys according to claim 19, is characterized in that wherein said forward voltage is between 3-8 volt range.
21. memory bodys according to claim 12, it is characterized in that wherein said control circuit further configuration be, when the one of this first and second end in a very first time interval in this first tandem memory cell of bias voltage is to this setting voltage, apply this first and second both the end in each and this second tandem memory cell in this ground voltage class to the another one, these many character lines of this first and second end in this first tandem memory cell simultaneously.
22. memory bodys according to claim 21, it is characterized in that wherein applying this bit line programming voltage, maintaining this first and second both end in this second tandem memory cell in this ground voltage class, the step that applies this forward voltage and apply this programming voltage is all carry out in one second time interval behind this very first time interval.
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| CN109411002B (en) * | 2017-08-15 | 2021-01-29 | 华为技术有限公司 | Data reading method and flash memory controller |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101223640A (en) * | 2005-07-14 | 2008-07-16 | 美光科技公司 | High density nand non-volatile memory device |
| CN101409290A (en) * | 2007-10-12 | 2009-04-15 | 三星电子株式会社 | Non-volatile memory device, method of operating the same, and method of fabricating the same |
| CN101449335A (en) * | 2006-05-19 | 2009-06-03 | Nxp股份有限公司 | Sonos memory device and method of operating a sonos memory device |
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| US7894263B2 (en) * | 2007-09-28 | 2011-02-22 | Sandisk Corporation | High voltage generation and control in source-side injection programming of non-volatile memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101223640A (en) * | 2005-07-14 | 2008-07-16 | 美光科技公司 | High density nand non-volatile memory device |
| CN101449335A (en) * | 2006-05-19 | 2009-06-03 | Nxp股份有限公司 | Sonos memory device and method of operating a sonos memory device |
| CN101409290A (en) * | 2007-10-12 | 2009-04-15 | 三星电子株式会社 | Non-volatile memory device, method of operating the same, and method of fabricating the same |
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