CN102761115B - ESD protection circuit - Google Patents
ESD protection circuit Download PDFInfo
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- CN102761115B CN102761115B CN201110106372.9A CN201110106372A CN102761115B CN 102761115 B CN102761115 B CN 102761115B CN 201110106372 A CN201110106372 A CN 201110106372A CN 102761115 B CN102761115 B CN 102761115B
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- 239000004065 semiconductor Substances 0.000 claims description 134
- 229910044991 metal oxide Inorganic materials 0.000 claims description 116
- 150000004706 metal oxides Chemical class 0.000 claims description 116
- 230000005611 electricity Effects 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 230000003068 static Effects 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N oxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 238000007689 inspection Methods 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 101710031899 moon Proteins 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 230000000875 corresponding Effects 0.000 description 8
- 238000001514 detection method Methods 0.000 description 5
- 238000007599 discharging Methods 0.000 description 5
- 230000002633 protecting Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 206010003497 Asphyxia Diseases 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 150000002927 oxygen compounds Chemical class 0.000 description 2
- 230000001681 protective Effects 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 210000000080 chela (arthropods) Anatomy 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000001737 promoting Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001960 triggered Effects 0.000 description 1
Abstract
A kind of ESD protection circuit, includes an electrostatic discharge testing circuit and multiple power supply clamped circuit.Electrostatic discharge testing circuit is electrically connected to one first high-voltage power-line, one second high-voltage power-line and at least one low-tension supply line, for detecting electrostatic and the electrostatic of the second high-voltage power-line of the first high-voltage power-line, and electrostatic discharge testing circuit includes one first trigger element and one second trigger element, it is respectively and electrically connected to the first high-voltage power-line and the second high-voltage power-line.Each power supply clamped circuit is respectively provided with a trigger point, and trigger point is electrically connected to the first trigger element and the second trigger element.
Description
Technical field
The present invention relates to a kind of ESD protection circuit, particularly relate to one and be electrically connected at least two electricity for protection
The ESD protection circuit of the integrated circuit of source line group.
Background technology
Along with scientific and technological progress, integrated circuit processing technique the most constantly progresses greatly, and the most various electronic circuits can aggregation/one-tenth
Shape is on one chip.At present IC chip can divide into core circuit and input/output circuitry, and core circuit with
Input/output circuitry uses different size of voltage source to drive respectively.For core circuit to be made and input/output circuitry energy
Receive extraneous voltage source, IC chip can be provided with core power connection pad and the input/output power supply connection pad of conduction.
But, when chip encapsulating, test, transport, process, etc. during, these connection pads be also easy to because with the external world
Electrostatic potential source contact, and the improper electric power of electrostatic is conducted to chip internal, and and then cause the damage of chip internal circuits,
This phenomenon is so-called static discharge (electrostatic discharge, ESD).Therefore, it is used for protecting integrated circuit
Chip is from the ESD protection circuit (ESD protection circuit) of damage of electrostatic discharge, the most therefore along with integrated
Improving of circuit technology and become more important.
Refer to Fig. 1, Fig. 1 is the electrostatic discharge protective electricity becoming known for the integrated circuit that protection uses two groups of source line group
The circuit diagram on road.As it is shown in figure 1, respectively group source line group 10 is respectively provided with a high-voltage power-line 10a and a low-tension supply line
10b, and electrostatic discharge event is likely to occur in each high-voltage power-line 10a and each low-tension supply line 10b, and flow to other high pressure
Power line 10a and low-tension supply line 10b.In order to protect the integrated circuit using these two groups of source line group 10, it is known that static discharge
Protection circuit 12 is electrically connected with so far two groups of source line group 10, and includes four power supply clamped circuits 14, is electrically connected with in respectively
Between high-voltage power-line 10a and each low-tension supply line 10b.Further, each power supply clamped circuit 14 includes an electric capacity 16, one respectively
Resistance 18,1 first N-type metal-oxide semiconductor (MOS) (NMOS) transistor 20,1 second N-type metal-oxide semiconductor (MOS) crystal
Pipe 22 and a diode 24.Each electric capacity 16 is electrically connected with in corresponding high-voltage power-line 10a and each first N-type metal
Between the grid of oxide semi conductor transistor 20, and each resistance 18 is electrically connected with in corresponding low-tension supply line 10b
And between the grid of each first N-type metal oxide semiconductor transistor 20.Thereby, in each power supply clamped circuit 14, when quiet
Discharge of electricity occurs when high-voltage power-line 10a, and the resistance-capacitance circuit being made up of electric capacity 16 and resistance 18 can provide a high-voltage
To the grid of the first N-type metal oxide semiconductor transistor 20, to open the first N-type metal oxide semiconductor transistor
20.Additionally, the drain electrode of each first N-type metal oxide semiconductor transistor 20 is respectively and electrically connected to corresponding height with source electrode
Voltage source line 10a and the base stage of each second N-type metal oxide semiconductor transistor 22, therefore when the first N-type metal-oxide
When semiconductor transistor 20 is unlocked, occur the electrostatic at high-voltage power-line 10a can pass through the first N-type metal-oxide semiconductor (MOS)
Transistor 20, and trigger the second N-type metal oxide semiconductor transistor 22, make the second N-type metal-oxide semiconductor (MOS) crystal
Pipe 22 is unlocked.The drain electrode of each second N-type metal oxide semiconductor transistor 22 is respectively and electrically connected to corresponding with source electrode
High-voltage power-line 10a and low-tension supply line 10b, and the grid of each second N-type metal oxide semiconductor transistor 22 is electrical
It is connected to corresponding low-tension supply line 10b.When the second N-type metal oxide semiconductor transistor 22 is unlocked, occur
The electrostatic of high-voltage power-line 10a can pass through the second N-type metal oxide semiconductor transistor 22, and is directed to low-tension supply line
10b, thereby can be by the electrostatic guide of high-voltage power-line 10a to low-tension supply line 10b.It addition, the anode of each diode 24 is with cloudy
Pole is respectively and electrically connected to corresponding low-tension supply line 10b and high-voltage power-line 10a, and the electrostatic making low-tension supply line 10b can
It is led to high-voltage power-line 10a.
It follows that need to be electrically connected with a power supply clamped circuit between each high-voltage power-line 10a and each low-tension supply line 10b
14 guide the generation electrostatic at each high-voltage power-line 10a, and each power supply clamped circuit 14 need to arrange electric capacity 16 and an electricity
Resistance 18, detects as testing circuit and the electrostatic at each high-voltage power-line 10a occurs, to provide high potential to the first N-type metal
The grid of oxide semi conductor transistor 20.Therefore, as a example by two groups of source line group 10, need four power supply clamped circuits 14 to add
With protection.And when the group number of source line group 10 increases to three groups, the quantity of power supply clamped circuit 14 then needs to increase to nine, because of
This also must increase by nine electric capacity 16 and nine resistance 18 are used as testing circuit.But, in known IC chip, electric capacity
16 account for a certain proportion of area of IC chip, the therefore number of the source line group 10 needed for IC chip with resistance 18
When measuring the most, the electric capacity 16 of ESD protection circuit 12 and the quantity of resistance 18 also must be the most, and then limit ic core
The size of sheet.
In view of this, an important issue of the electric capacity of ESD protection circuit and the quantity actually industry of resistance is reduced.
Summary of the invention
One of the main object of the present invention is to provide a kind of ESD protection circuit, to reduce the number of electric capacity and resistance
Amount.
In order to achieve the above object, the present invention provides a kind of ESD protection circuit, is electrically connected at least two power lines
Group.Source line group includes that one first high-voltage power-line, one first low-tension supply line, one second high-voltage power-line and one second are low
Voltage source line.ESD protection circuit includes an electrostatic discharge testing circuit and multiple power supply clamped circuit.Electrostatic is put
Power detection circuit is electrically connected to the first high-voltage power-line, the second high-voltage power-line and the first low-tension supply line and the second low pressure
At least one of power line, for electrostatic and the electrostatic of the second high-voltage power-line of detection the first high-voltage power-line, and electrostatic is put
Power detection circuit includes one first trigger element and one second trigger element, be respectively and electrically connected to the first high-voltage power-line with
Second high-voltage power-line.Power supply clamped circuit is electrically connected to source line group, and is respectively provided with a trigger point, wherein trigger point electricity
Property is connected to the first trigger element and the second trigger element.
The ESD protection circuit of the present invention is by being arranged at each power supply strangulation by single electrostatic discharge testing circuit
Outer the avoiding of circuit limits the size of integrated circuit because the quantity of power supply clamped circuit increases.
Accompanying drawing explanation
Fig. 1 is the circuit signal of the ESD protection circuit becoming known for the integrated circuit that protection uses two groups of power supplys
Figure.
Fig. 2 is the block schematic diagram of the ESD protection circuit of first preferred embodiment of the invention.
Fig. 3 is the schematic diagram of the electrostatic discharge testing circuit of first preferred embodiment of the invention.
Fig. 4 is the schematic diagram of the power supply clamped circuit of first preferred embodiment of the invention.
Fig. 5 is the schematic diagram of the electrostatic discharge testing circuit of second preferred embodiment of the invention.
Fig. 6 is an embodiment of the electrostatic discharge testing circuit of second preferred embodiment of the invention.
Fig. 7 is the schematic diagram of the power supply clamped circuit of second preferred embodiment of the invention.
Fig. 8 is the schematic diagram of the ESD protection circuit of third preferred embodiment of the invention.
[main element symbol description]
10 source line group 10a high-voltage power-lines
10b low-tension supply line 12 ESD protection circuit
14 power supply clamped circuit 16 electric capacity
18 resistance 20 first N-type metal-oxides half
Conductor transistor
22 second N-type burning 24 diodes
Thing semiconductor transistor
100 ESD protection circuit 102 first source line group
102a the first high-voltage power-line 102b the first low-tension supply line
104 second source line group 104a the second high-voltage power-lines
104b the second low-tension supply line 106 electrostatic discharge testing circuit
108 power supply clamped circuit 108a the first power supply clamped circuits
108b second source clamped circuit 108c the 3rd power supply clamped circuit
108d the 4th power supply clamped circuit 108e the 5th power supply clamped circuit
108f the 6th power supply clamped circuit 108g the 7th power supply clamped circuit
108h the 8th power supply clamped circuit 108i the 9th power supply clamped circuit
110 trigger point 112 connecting lines
114 first trigger element 116 second trigger elements
118 first N-type burning 120 first electric capacity
Thing semiconductor transistor
122 second electric capacity 124 first resistance
125 first diode 126 the 3rd metal-oxide semiconductor (MOS)s
Transistor
128 second diode 130 the 4th metal-oxide semiconductor (MOS)s
Transistor
132 the 3rd diode 1 34 fifth metal oxide semiconductors
Transistor
136 the 4th diode 138 the 6th metal-oxide semiconductor (MOS)s
Transistor
140 the 5th diode 150 phase inverters
150a input 150b outfan
152 electrostatic discharge testing circuit 154 the 3rd electric capacity
156 second resistance 158 the 3rd resistance
160 p-type metal-oxides partly lead 162 second N-type metal-oxides half
Body transistor conductor transistor
170 the 3rd source line group 170a the 3rd high-voltage power-lines
170b the 3rd low-tension supply line 172 ESD protection circuit
174 electrostatic discharge testing circuit 176 the 3rd trigger elements
178 the 4th electric capacity 180 the 7th metal-oxide semiconductor (MOS)s
Transistor
B base stage D drains
G grid S source electrode
Detailed description of the invention
Refer to the circuit diagram of the ESD protection circuit that Fig. 2, Fig. 2 are first preferred embodiment of the invention.As
Shown in Fig. 2, ESD protection circuit 100 is electrically connected at least two source line group 102,104, occurs at electricity for protection
The various static discharge patterns of source line group 102.Source line group 102,104 includes one first source line group 102 and a second source
Line group 104, wherein the first source line group 102 has one first high-voltage power-line 102a and one first low-tension supply line 102b, and
Second source line group 104 has one second high-voltage power-line 104a and one second low-tension supply line 104b.In the present embodiment,
First high-voltage power-line 102a provides one first voltage, and such as: 2.5 volts or 3.3 volts, and the first low-tension supply line 102b is then
It is an earth terminal, makes the first source line group 102 can be used for driving input/output (I/O) circuit.Second high-voltage power-line 104a carries
For one second voltage, such as: 1.0 volts, and the second low-tension supply line 104b is another earth terminal, makes the first voltage more than second
Voltage, thereby second source line group 104 can be used for driving the pressure core circuit low compared with input/output circuitry.The of the present invention
One high-voltage power-line 102a and the second high-voltage power-line 104a is not limited to provide above-mentioned voltage.Further, electrostatic discharge protective electricity
Road 100 includes an electrostatic discharge testing circuit 106 and multiple power supply clamped circuit 108, the most each power supply clamped circuit 108 points
Not there is a trigger point (triggernode) 110, and each power supply clamped circuit 108 is respectively used to release and occurs at the first high pressure
The electrostatic of power line 102a and the second high-voltage power-line 104a is to the first low-tension supply line 102b and the second low-tension supply line 104b.
Electrostatic discharge testing circuit 106 is electrically connected to the first high-voltage power-line 102a, the second high-voltage power-line 104a, the first low tension
At least one and each trigger point 110 of source line 102b and the second low-tension supply line 104b, occurs first high for detection
One electrostatic discharge event of voltage source line 102a with occur at another electrostatic discharge event of the second high-voltage power-line 104a.Separately
Outward, ESD protection circuit 100 also includes a connecting line 112, is used for being electrically connected with electrostatic discharge testing circuit 106 and each electricity
The trigger point 110 of source clamped circuit 108, makes the produced signal that triggers of electrostatic discharge testing circuit 106 can be transferred to each power supply
Clamped circuit 108, and open each power supply clamped circuit 108.
Refer to Fig. 3, and in the lump with reference to Fig. 2.Fig. 3 is the electrostatic discharge testing circuit of first preferred embodiment of the invention
Schematic diagram.As shown in Figure 2 and Figure 3, electrostatic discharge testing circuit 106 includes that one first trigger element 114 and one second triggers
Unit 116.First trigger element 114 is electrically connected to the first high-voltage power-line 102a and trigger point 110, and examines in static discharge
Slowdown monitoring circuit 106 detects that generation provides one first triggering signal to even when the electrostatic discharge event of the first high-voltage power-line 102a
Wiring 112, makes the power supply clamped circuit 108 being electrically connected to connecting line 112 can be triggered signal triggering by first and open, and then
There is provided electrostatic discharging path release that the electrostatic at the first high-voltage power-line 102a occurs.It addition, the second trigger element 116 electrically connects
It is connected to the second high-voltage power-line 104a and trigger point 110, and detects that generation is at the second high pressure in electrostatic discharge testing circuit 106
There is provided one second triggering signal to connecting line 112 during the electrostatic discharge event of power line 104a, make to be electrically connected to connecting line 112
Power supply clamped circuit 108 can by second trigger signal trigger and open, and then provide electrostatic discharging path discharge the second high pressure
The electrostatic of power line 104a.In the present embodiment, the first trigger element 114 and the second trigger element 116 can be respectively one the oneth N
Type metal oxide semiconductor (NMOS) transistor 118.Wherein, the grid G of each first N-type metal semiconductor transistor 118 that
This is electrically connected with, and the drain D of each first N-type metal semiconductor transistor 118 is respectively and electrically connected to the first high-voltage power-line
102a and the second high-voltage power-line 104a, and the source S electric connection of each first N-type metal oxide semiconductor transistor 118
To connecting line 112, to be electrically connected to each trigger point 110.Further, electrostatic discharge testing circuit 106 also includes one first electric capacity
120, one second electric capacity 122 and one first resistance 124, occurs the electrostatic at the first high-voltage power-line 102a to put for detection
Electricity event with occur at the electrostatic discharge event of the second high-voltage power-line 104a.First electric capacity 120 is electrically connected at the first high pressure
Between the grid G of power line 102a and the first N-type metal oxide semiconductor transistor 118, and the second electric capacity 122 is electrically connected with
Between the grid G of the second high-voltage power-line 104a and the first N-type metal oxide semiconductor transistor 118, and the first resistance
124 be electrically connected at the grid G of each first N-type metal oxide semiconductor transistor 118 and the second low-tension supply line 104b it
Between.In other embodiments of the invention, the first resistance 124 also can be electrically connected at the first N-type metal-oxide semiconductor (MOS) crystalline substance
Between grid G and the first low-tension supply line 102b of body pipe 118.Or, electrostatic discharge testing circuit 106 is except the first resistance
Between 124 grid G being electrically connected at the first N-type metal oxide semiconductor transistor 118 and the second low-tension supply line 104b
Also can also include a resistance outward, the grid G being electrically connected at the first N-type metal oxide semiconductor transistor 118 is low with first
Between voltage source line 102b.
It follows that the first electric capacity 120 and the first resistance 124 constitute a resistance-capacitance circuit (RC circuit), it is electrically connected with
Between the first high-voltage power-line 102a and the second low-tension supply line 104b, therefore occur at the first high pressure when electrostatic discharge event
During power line 102a, electrostatic can promote the grid of each first N-type metal oxide semiconductor transistor 118 by the first electric capacity 120
The current potential of pole G, and then open the first N-type metal oxide semiconductor transistor 118.Thereby, electrostatic can be from the first high voltage power supply
Line 102a is directed to connecting line 112, to trigger each power supply clamped circuit 118 further.Similarly, the second electric capacity 122 is also with
One resistance 124 constitutes another resistance-capacitance circuit, be electrically connected at the second high-voltage power-line 104a and the second low-tension supply line 104b it
Between, therefore when electrostatic discharge event occurs at the second high-voltage power-line 104a, each first N-type metal-oxide semiconductor (MOS) crystal
Pipe 118 can be unlocked.Thereby, electrostatic can be directed to connecting line 112 from the second high-voltage power-line 104a, to trigger each electricity further
Source clamped circuit 108.It addition, the electrostatic discharge testing circuit 106 of the present embodiment also includes one first diode 125, and first
The anode of diode 125 and negative electrode are respectively and electrically connected to the second high-voltage power-line 104a and the first high-voltage power-line 102a, with
For promoting the electrostatic discharge capacity of the second high-voltage power-line 104a, and the core electricity that voltage capability is relatively low is born in protection effectively
Road avoids electrostatic breakdown.
In other embodiments of the invention, ESD protection circuit 100 separately can include two diodes, one of them
Anode and negative electrode be respectively and electrically connected to the first high-voltage power-line 102a and the second high-voltage power-line 104a, and wherein another one
Anode and negative electrode are respectively and electrically connected to the second high-voltage power-line 104a and the first high-voltage power-line 102a, make the first high voltage power supply
The electrostatic of line 102a or the second high-voltage power-line 104a can be directed to the second high-voltage power-line 104a or the first high-voltage power-line
102a.It addition, ESD protection circuit 100 the most separately can include two diodes, the anode of one of them is with negative electrode the most electrically
Be connected to the first low-tension supply line 102b and the second low-tension supply line 104b, and wherein another one anode with negative electrode the most electrically
It is connected to the second low-tension supply line 104b and the first low-tension supply line 102b, with the first low-tension supply line 102b or the second low tension
The electrostatic of source line 104b can be directed to the second low-tension supply line 104b or the first low-tension supply line 102b.
Refer to Fig. 4, and in the lump with reference to the signal of the power supply clamped circuit that Fig. 2, Fig. 4 are first preferred embodiment of the invention
Figure.As shown in Fig. 2 Yu Fig. 4, the power supply clamped circuit 108 of the present embodiment include one first power supply clamped circuit 108a, one second
Power supply clamped circuit 108b, one the 3rd power supply clamped circuit 108c and one the 4th power supply clamped circuit 108d.First power supply pincers
Circuit 108a processed is electrically connected between the first high-voltage power-line 102a and the first low-tension supply line 102b, for providing two electrostatic
Discharge path, respectively from the first high-voltage power-line 102a to first low-tension supply line 102b with from the first low-tension supply line 102b to
First high-voltage power-line 102a.Second source clamped circuit 108b is electrically connected at the first high-voltage power-line 102a and the second low pressure
Between power line 104b, for providing two electrostatic discharging paths, respectively from the first high-voltage power-line 102a to second low-tension supply
Line 104b with from the second low-tension supply line 104b to first high-voltage power-line 102a.3rd power supply clamped circuit 108c is electrically connected with
Between the second high-voltage power-line 104a and the first low-tension supply line 102b, for providing two electrostatic discharging paths, respectively from the
Two high-voltage power-line 104a to first low-tension supply line 102b with from the first low-tension supply line 102b to second high-voltage power-line
104a.4th power supply clamped circuit 108d be electrically connected at the second high-voltage power-line 104a and the second low-tension supply line 104b it
Between, for providing two electrostatic discharging paths, respectively from the second high-voltage power-line 104a to second low-tension supply line 104b with from the
Two low-tension supply line 104b to second high-voltage power-line 104a.Thereby, the first power supply clamped circuit 108a, a second source strangulation
Circuit 108b, one the 3rd power supply clamped circuit 108c and one the 4th power supply clamped circuit 108d can protect and be electrically connected at first
High-voltage power-line 102a, the first low-tension supply line 102b, the second high-voltage power-line 104a and the second low-tension supply line 104b's
Integrated circuit.
First power supply clamped circuit 108a includes one the 3rd metal oxide semiconductor transistor 126 and the 2nd 2
Pole pipe 128, and second source clamped circuit 108b includes one the 4th metal oxide semiconductor transistor 130 and the 3rd
Diode 132.3rd power supply clamped circuit 108c includes a fifth metal oxide semi conductor transistor 134 and the 4th
Diode 136, and the 4th power supply clamped circuit 108d includes one the 6th metal oxide semiconductor transistor 138 and one
Five diodes 140.In the present embodiment, the 3rd metal oxide semiconductor transistor the 126, the 4th metal-oxide semiconductor (MOS) is brilliant
Body pipe 130, fifth metal oxide semi conductor transistor 134 and the 6th metal oxide semiconductor transistor 138 are N-type metal
Oxide semi conductor transistor.Further, the source S of the 3rd N-type metal oxide semiconductor transistor 126 electrically connects with grid G
It is connected to the first low-tension supply line 102b, and the drain D of the 3rd N-type metal oxide semiconductor transistor 126 is electrically connected to
One high-voltage power-line 102a.The source S of the 4th N-type metal oxide semiconductor transistor 130 and grid G are electrically connected to second
Low-tension supply line 104b, and the drain D of the 4th N-type metal oxide semiconductor transistor 130 is electrically connected to the first high-tension electricity
Source line 102a.The source S of the 5th N-type metal oxide semiconductor transistor 134 and grid G are electrically connected to the first low-tension supply
Line 102b, and the drain D of the 5th N-type metal oxide semiconductor transistor 134 is electrically connected to the second high-voltage power-line 104a.
The source S of the 6th N-type metal oxide semiconductor transistor 138 and grid G are electrically connected to the second low-tension supply line 104b, and
The drain D of the 6th N-type metal oxide semiconductor transistor 138 is electrically connected to the second high-voltage power-line 104a.Thereby, first
The electrostatic of high-voltage power-line 102a can be via opening the 3rd N-type metal oxide semiconductor transistor 126 and the 4th N-type metal oxygen
Compound semiconductor transistor 130 discharges to the first low-tension supply line 102b and the second low-tension supply line 104b, and the second high-tension electricity
The electrostatic of source line 104a can be via opening the 5th N-type metal oxide semiconductor transistor 134 and the 6th N-type metal-oxide half
Conductor transistor 138 discharges to the first low-tension supply line 102b and the second low-tension supply line 104b.3rd metal oxygen of the present invention
Compound semiconductor transistor the 126, the 4th metal oxide semiconductor transistor 130, fifth metal oxide semi conductor transistor
134 and the 6th metal oxide semiconductor transistor 138 be not limited to N-type metal oxide semiconductor transistor, it is possible to for p-type
Metal-oxide semiconductor (MOS) (PMOS) transistor, and its be electrically connected with mode be by each P-type mos transistor
Source electrode be electrically connected to corresponding high-voltage power-line with grid, its drain electrode is then electrically connected to corresponding low-tension supply
Line.
In the present embodiment, the trigger point 110 of the first power supply clamped circuit 108a is the 3rd N-type metal-oxide semiconductor (MOS)
Base stage B of transistor 126, the trigger point 110 of second source clamped circuit 108b is the 4th N-type metal-oxide semiconductor (MOS) crystal
Base stage B of pipe 130, the trigger point 110 of the 3rd power supply clamped circuit 108c is the 5th N-type metal oxide semiconductor transistor
Base stage B of 134, and the trigger point 110 of the 4th power supply clamped circuit 108d is the 6th metal oxide semiconductor transistor 138
Base stage B.That is, the 3rd N-type metal oxide semiconductor transistor the 126, the 4th N-type metal oxide semiconductor transistor 130,
5th N-type metal oxide semiconductor transistor 134 and the 6th N-type metal oxide semiconductor transistor 138 touch for matrix
The transistor sent out, but be not limited.Further, the 3rd N-type metal oxide semiconductor transistor 126 and the 4th N-type metal oxygen
Compound semiconductor transistor 130 designed to be used and bears the first voltage that the first high-voltage power-line 102a is provided, and is also
Avoid the core circuit being electrically connected to identical voltage by electrostatic breakdown, the 3rd N-type metal oxide semiconductor transistor
126 is identical with the thickness of the grid oxic horizon of the 4th N-type metal oxide semiconductor transistor 130, and need to coordinate first high
The first voltage that voltage source line 102a is provided designs.Similarly, the 5th N-type metal oxide semiconductor transistor 134
It designed to be used with the 6th N-type metal oxide semiconductor transistor 138 and bear what the second high-voltage power-line 104a was provided
Second voltage.That is, in order to avoid being electrically connected to the input/output circuitry of identical voltage by electrostatic breakdown, the 5th N-type gold
The thickness of the grid oxic horizon belonging to oxide semi conductor transistor 134 and the 6th N-type metal oxide semiconductor transistor 138 needs
The second voltage coordinating the second high-voltage power-line 104a to be provided designs.
It addition, the anode of the second diode 128 and negative electrode are respectively and electrically connected to the first low-tension supply line 102b and first
High-voltage power-line 102a, the anode of the 3rd diode 132 and negative electrode are respectively and electrically connected to the second low-tension supply line 104b and the
One high-voltage power-line 102a, the anode of the 4th diode 136 and negative electrode be respectively and electrically connected to the first low-tension supply line 102b with
Second high-voltage power-line 104a, and the anode of the 5th diode 140 and negative electrode be respectively and electrically connected to the second low-tension supply line
104b and the second high-voltage power-line 104a.Thereby, the electrostatic of the first low-tension supply line 102b can be respectively via the second diode 128
Discharge to the first high-voltage power-line 102a and the second high-voltage power-line 104a with the 4th diode 136, and the second low-tension supply line
The electrostatic of 104b can discharge to the first high-voltage power-line 102a and via the 3rd diode 132 and the 5th diode 140 respectively
Two high-voltage power-line 104a.
From the foregoing, the ESD protection circuit 100 of the present embodiment be electrically connected at least two source line group 102,
104, and outside single electrostatic discharge testing circuit 106 is arranged at each power supply clamped circuit 108, thereby can avoid because of power supply
The quantity of clamped circuit 108 increases and limits the size of integrated circuit.Further, the single electrostatic discharge testing circuit of the present embodiment
106 are respectively provided with the first trigger element 114 for each source line group 102,104 and the second trigger element 116 produces triggering letter
Number, and by connecting line 112, triggering signal is transferred to each power supply clamped circuit 108, therefore can open each power supply clamped circuit
108, to carry out static discharge, and protection simultaneously is electrically connected to core circuit and the input/output circuitry of different voltage.
The electrostatic discharge testing circuit of the present invention is not limited with above-described embodiment with power supply clamped circuit.Hereafter will continue
Disclose other embodiments of the invention or change shape, the most for the purpose of simplifying the description and highlight each embodiment or change shape between difference
Different, identical label mark similar elements is used below, and no longer counterweight part again repeats.
Refer to the schematic diagram of the electrostatic discharge testing circuit that Fig. 5, Fig. 5 are second preferred embodiment of the invention.Such as Fig. 5 institute
Showing, compared to the first preferred embodiment, it is anti-that first trigger element 114 of the present embodiment and the second trigger element 116 are respectively one
Phase device 150, and each phase inverter 150 has an an input 150a and outfan 150b.Further, the input of each phase inverter 150
End 150a is electrically connected to each other, and the outfan 150b of each phase inverter 150 is electrically connected to connecting line 112.Additionally, the present embodiment
Electrostatic discharge testing circuit 152 include one the 3rd electric capacity 154,1 second resistance 156 and one the 3rd resistance 158, Qi Zhong
Three electric capacity 154 are electrically connected between input 150a and the second low-tension supply line 104b, and the second resistance 156 is electrically connected at
Between one high-voltage power-line 102a and input 150a, and the 3rd resistance 158 be electrically connected at the second high-voltage power-line 104a with
Between input 150a.
In order to understand the phase inverter of explanation the present embodiment, refer to Fig. 6, and in the lump with reference to Fig. 5.Fig. 6 is the present invention second
One embodiment of the electrostatic discharge testing circuit of preferred embodiment.As shown in figs. 5 and 6, each phase inverter of the present embodiment 150 points
Do not include P-type mos transistor 160 and an one second N-type metal oxide semiconductor transistor 162.Its
In, the grid G of each P-type mos transistor 160 respectively with each second N-type metal oxide semiconductor transistor
The grid G of 162 is electrically connected with, and the grid G of each P-type mos transistor 160 is electrically connected to each other, and conduct
Each input 150a.Thereby, the 3rd electric capacity 154 is electrically connected at the grid G of each P-type mos transistor 160
And between the second low-tension supply line 104b, the second resistance 156 is electrically connected at the first high-voltage power-line 102a and p-type burning
Between the grid G of thing semiconductor transistor 160, and the 3rd resistance 158 is electrically connected at the second high-voltage power-line 104a and p-type gold
Belong between the grid G of oxide semi conductor transistor 160.The drain D of each P-type mos transistor 160 is respectively
It is electrically connected to the drain D of each second N-type metal oxide semiconductor transistor 162, and respectively as each outfan 150b, and
The drain D of each P-type mos transistor 160 is respectively and electrically connected to connecting line 112.Additionally, each p-type metal oxygen
The source S of compound semiconductor transistor 160 is respectively and electrically connected to the first high-voltage power-line 102a and the second high-voltage power-line
104a, and the source S of each second N-type metal oxide semiconductor transistor 162 is respectively and electrically connected to the second low-tension supply line
104b.In other embodiments of the invention, the 3rd electric capacity 154 also can be electrically connected at P-type mos crystal
Between grid G and the first low-tension supply line 102b of pipe 160, and the source of each second N-type metal oxide semiconductor transistor 162
Pole S is then electrically connected to the first low-tension supply line 102b.
In the present embodiment, when electrostatic discharge event occurs at the first high-voltage power-line 102a, each p-type metal-oxide
The current potential of the grid G of semiconductor transistor 160 is in electronegative potential, therefore opens each P-type mos transistor
160.Thereby, the p-type metal semiconductor transistor 160 being electrically connected to the first high-voltage power-line 102a can be by electrostatic guide to even
Wiring 112, to trigger each power supply clamped circuit 108 further.Similarly, occur in the second high voltage power supply when electrostatic discharge event
During line 104a, the grid G of each P-type mos transistor 160 is in electronegative potential and is unlocked, with by the second high pressure
The electrostatic guide of power line 104a, to connecting line 112, therefore triggers each power supply clamped circuit 108.
Refer to the schematic diagram of the power supply clamped circuit that Fig. 7, Fig. 7 are second preferred embodiment of the invention.As it is shown in fig. 7,
Compared to the first preferred embodiment, the trigger point 110 of the first power supply clamped circuit 108a of the present embodiment is the 3rd N-type metal oxygen
The grid G of compound semiconductor transistor 126, and the trigger point 110 of second source clamped circuit 108b is the 4th N-type burning
The grid G of thing semiconductor transistor 130.Further, the trigger point 110 of the 3rd power supply clamped circuit 108c of the present embodiment is the 5th
The grid G of N-type metal oxide semiconductor transistor 134, and the trigger point 110 of the 4th power supply clamped circuit 108d is the 6th N
The grid G of type metal oxide semiconductor transistor 138.
Additionally, the ESD protection circuit of the present invention is not limited to above-described embodiment, in other embodiments of the present invention
In, ESD protection circuit also can be by the electrostatic discharge testing circuit of the first preferred embodiment and the electricity of the second preferred embodiment
Source clamped circuit is constituted, or ESD protection circuit can be by the electrostatic discharge testing circuit of the second preferred embodiment and
The power supply clamped circuit of one preferred embodiment is constituted.
It addition, the present invention is not limited to be only applicable to two groups of source line group, it is possible to be applicable to plural groups source line group.Please join
Examine the schematic diagram of the ESD protection circuit that Fig. 8, Fig. 8 are third preferred embodiment of the invention.As shown in Figure 8, compared to
One preferred embodiment, the source line group of the present embodiment also includes one the 3rd source line group 170, and the 3rd source line group 170 has
One the 3rd high-voltage power-line 170a and one the 3rd low-tension supply line 170b.In the ESD protection circuit 172 of the present embodiment,
Electrostatic discharge testing circuit 174 also includes one the 3rd trigger element 176 and one the 4th electric capacity 178, and the 3rd trigger element 176
Being one the 7th metal oxide semiconductor transistor 180, wherein the 7th metal oxide semiconductor transistor 180 can be N-type gold
Belong to oxide semi conductor transistor, but be not limited to this.The grid G of the 7th N-type metal oxide semiconductor transistor 180 electrically connects
It is connected to the grid G of each first N-type metal oxide semiconductor transistor 118, and the 7th N-type metal oxide semiconductor transistor
The drain D of 180 and source S are respectively and electrically connected to the 3rd high-voltage power-line 170a and connecting line 112.Further, the 4th electric capacity 178
It is electrically connected between grid G and the 3rd high-voltage power-line 170a of the 7th N-type metal oxide semiconductor transistor 180.This
Outward, the power supply clamped circuit 108 of the present embodiment also includes one the 5th power supply clamped circuit 108e, one the 6th power supply clamped circuit
108f, one the 7th power supply clamped circuit 108g, one the 8th power supply clamped circuit 108h and one the 9th power supply clamped circuit 108i,
Be electrically connected with between the first high-voltage power-line 102a and the 3rd low-tension supply line 170b, the second high-voltage power-line 104a with
Between 3rd low-tension supply line 170b, between the 3rd high-voltage power-line 170a and the first low-tension supply line 102b, the 3rd high-tension electricity
Between source line 170a and the second low-tension supply line 104b and the 3rd high-voltage power-line 170a and the 3rd low-tension supply line 170b it
Between.Owing to each power supply clamped circuit of the present embodiment includes a N-type metal oxide semiconductor transistor and one or two poles the most respectively
Pipe, is only that from the difference of the first preferred embodiment and is electrically connected between different high-voltage power-lines and low-tension supply line, therefore
Do not repeat them here.
In other embodiments of the invention, the first resistance 124 also can be electrically connected at the first N-type metal-oxide and partly leads
Between grid G and the first low-tension supply line 102b of body transistor 118, or it is electrically connected at the first N-type metal-oxide and partly leads
Between grid G and the 3rd low-tension supply line 170b of body transistor 118.Or, electrostatic discharge testing circuit 106 is except the first electricity
Resistance 124 be electrically connected at the grid G of the first N-type metal oxide semiconductor transistor 118 and the second low-tension supply line 104b it
Between outer also can also include at least one resistance, be electrically connected at the grid G of the first N-type metal oxide semiconductor transistor 118 with
Between first low-tension supply line 102b or grid G and the 3rd low-tension supply of the first N-type metal oxide semiconductor transistor 118
Between line 170b.Or, electrostatic discharge testing circuit 106 is electrically connected at the first N-type metal-oxide except the first resistance 124
Also can also include two resistance outside between grid G and the second low-tension supply line 104b of semiconductor transistor 118, be electrically connected with
With the first N-type gold between the grid G and the first low-tension supply line 102b of the first N-type metal oxide semiconductor transistor 118
Belong between grid G and the 3rd low-tension supply line 170b of oxide semi conductor transistor 118.
It follows that compared to the first preferred embodiment, the source line group of the present embodiment only adds one group, but static discharge
Protection circuit need to increase by five power supply clamped circuits and protect the integrated circuit being electrically connected to source line group.
Electrostatic discharge testing circuit is arranged at outside each power supply clamped circuit by the ESD protection circuit of the present embodiment,
And only in single electrostatic discharge testing circuit, another increase by one metal oxide semiconductor transistor and an electric capacity i.e. can be used for
Trigger each power supply clamped circuit, therefore can decrease in and each power supply clamped circuit arranges the required increase of electrostatic discharge testing circuit
Area.
In sum, the ESD protection circuit of the present invention is by being arranged at single electrostatic discharge testing circuit respectively
Outer the avoiding of power supply clamped circuit limits the size of integrated circuit because the quantity of power supply clamped circuit increases.
The foregoing is only the preferred embodiments of the present invention, all equalizations done according to claims of the present invention change and repair
Decorations, all should belong to the covering scope of the present invention.
Claims (18)
1. an ESD protection circuit, is electrically connected at least two source line group, and described source line group includes that one first is high
Voltage source line, one first low-tension supply line, one second high-voltage power-line and one second low-tension supply line, and this static discharge is anti-
Protection circuit includes:
One electrostatic discharge testing circuit, be electrically connected to this first high-voltage power-line, this second high-voltage power-line and this first
, there is the electrostatic at this first high-voltage power-line for detecting at least one of low-tension supply line and this second low-tension supply line
Electric discharge event with occur at another electrostatic discharge event of this second high-voltage power-line, and this electrostatic discharge testing circuit includes
One first trigger element and one second trigger element, this first trigger element is directly electrically connected to this first high-voltage power-line,
This second trigger element is directly electrically connected to this second high-voltage power-line；And
Multiple power supply clamped circuits are electrically connected to described source line group, and are respectively provided with a trigger point, the most the plurality of power supply
Each trigger point in multiple trigger points of clamped circuit is electrically connected to this first trigger element and this second trigger element.
2. ESD protection circuit as claimed in claim 1, wherein this first trigger element divides with this second trigger element
Be not one first N-type metal oxide semiconductor transistor, the grid of described first N-type metal oxide semiconductor transistor that
This is electrically connected with, and respectively the drain electrode of this first N-type metal oxide semiconductor transistor is respectively and electrically connected to this first high-tension electricity
Source line and this second high-voltage power-line, and the source electrode of described first N-type metal oxide semiconductor transistor is electrically connected to this
Each trigger point in multiple trigger points of multiple power supply clamped circuits.
3. ESD protection circuit as claimed in claim 2, wherein this electrostatic discharge testing circuit also includes one first electricity
Appearance, one second electric capacity and one first resistance, this first electric capacity is electrically connected at this first high-voltage power-line and described first N-type
Between the grid of metal oxide semiconductor transistor, this second electric capacity is electrically connected at this second high-voltage power-line and described the
Between the grid of one N-type metal oxide semiconductor transistor, and this first resistance is electrically connected at this second low-tension supply line
And between the grid of described first N-type metal oxide semiconductor transistor.
4. ESD protection circuit as claimed in claim 1, wherein this electrostatic discharge testing circuit also includes one the 1st
Pole is managed, and the anode of this first diode is electrically connected to this second high-voltage power-line, and the negative electrode of this first diode electrically connects
It is connected to this first high-voltage power-line.
5. ESD protection circuit as claimed in claim 1, wherein this first trigger element divides with this second trigger element
It is not a phase inverter, and respectively this phase inverter has an input.
6. ESD protection circuit as claimed in claim 5, respectively this phase inverter includes a p-type metal-oxide respectively
Semiconductor transistor and one second N-type metal oxide semiconductor transistor, described P-type mos transistor
The grid of grid and described second N-type metal oxide semiconductor transistor be electrically connected to the input of respectively this phase inverter,
And the source electrode of described P-type mos transistor to be respectively and electrically connected to this first high-voltage power-line second high with this
Voltage source line.
7. ESD protection circuit as claimed in claim 5, wherein this electrostatic discharge testing circuit also includes one the 3rd electricity
Appearance, one second resistance and one the 3rd resistance, one end of the 3rd electric capacity is electrically connected with the input of respectively this phase inverter, the other end
It is electrically connected with this second low-tension supply line, and one end of this second resistance is electrically connected with this first high-voltage power-line, other end electricity
Property connect the input of each this phase inverter, one end of the 3rd resistance is electrically connected with this second high-voltage power-line, and the other end is electrical
Connect the input of respectively this phase inverter.
8. ESD protection circuit as claimed in claim 1, wherein said power supply clamped circuit includes:
One first power supply clamped circuit, is electrically connected between this first high-voltage power-line and this first low-tension supply line；
One second source clamped circuit, is electrically connected between this first high-voltage power-line and this second low-tension supply line；
One the 3rd power supply clamped circuit, is electrically connected between this second high-voltage power-line and this first low-tension supply line；And
One the 4th power supply clamped circuit, is electrically connected between this second high-voltage power-line and this second low-tension supply line.
9. ESD protection circuit as claimed in claim 8, wherein this first power supply clamped circuit includes one the 3rd gold medal
Belonging to oxide semi conductor transistor and one second diode, this second source clamped circuit includes one the 4th metal-oxide
Semiconductor transistor and one the 3rd diode, and the 3rd metal oxide semiconductor transistor and the 4th metal-oxide
Semiconductor transistor is for bearing one first voltage that this first high-voltage power-line is provided.
10. ESD protection circuit as claimed in claim 9, wherein this trigger point of this first power supply clamped circuit is for being somebody's turn to do
The base stage of the 3rd metal oxide semiconductor transistor, and this trigger point of this second source clamped circuit is the 4th metal oxygen
The base stage of compound semiconductor transistor.
11. ESD protection circuits as claimed in claim 9, wherein this trigger point of this first power supply clamped circuit is for being somebody's turn to do
The grid of the 3rd metal oxide semiconductor transistor, and this trigger point of this second source clamped circuit is the 4th metal oxygen
The grid of compound semiconductor transistor.
12. ESD protection circuits as claimed in claim 9, wherein the negative electrode of this second diode be electrically connected to this
One high-voltage power-line, the anode of this second diode is electrically connected to this first low-tension supply line, and the moon of the 3rd diode
Pole is electrically connected to this first high-voltage power-line, and the anode of the 3rd diode is electrically connected to this second low-tension supply line.
13. ESD protection circuits as claimed in claim 8, wherein the 3rd power supply clamped circuit includes a five metals
Belonging to oxide semi conductor transistor and one the 4th diode, the 4th power supply clamped circuit includes one the 6th metal-oxide
Semiconductor transistor and one the 5th diode, and this fifth metal oxide semi conductor transistor and the 6th metal-oxide
Semiconductor transistor is for bearing one second voltage that this second high-voltage power-line is provided.
14. ESD protection circuits as claimed in claim 13, wherein this trigger point of the 3rd power supply clamped circuit is
The base stage of this fifth metal oxide semi conductor transistor, and this trigger point of the 4th power supply clamped circuit is the 6th metal
The base stage of oxide semi conductor transistor.
15. ESD protection circuits as claimed in claim 13, wherein this trigger point of the 3rd power supply clamped circuit is
The grid of this fifth metal oxide semi conductor transistor, and this trigger point of the 4th power supply clamped circuit is the 6th metal
The grid of oxide semi conductor transistor.
16. ESD protection circuits as claimed in claim 13, wherein the negative electrode of the 4th diode is electrically connected to this
Second high-voltage power-line, the anode of the 4th diode is electrically connected to this first low-tension supply line, and the 5th diode
Negative electrode is electrically connected at this second high-voltage power-line, and the anode of the 5th diode is electrically connected at this second low-tension supply line.
17. ESD protection circuits as claimed in claim 1, also include a connecting line, are electrically connected with the inspection of this static discharge
Slowdown monitoring circuit and each trigger point in multiple trigger points of the plurality of power supply clamped circuit.
18. ESD protection circuits as claimed in claim 1, wherein this at least two source line group also includes one the 3rd high pressure
Power line and one the 3rd low-tension supply line, and this electrostatic discharge testing circuit also includes one the 3rd trigger element, is electrically connected with
Each trigger point to the 3rd high-voltage power-line multiple trigger points with the plurality of power supply clamped circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110106372.9A CN102761115B (en) | 2011-04-27 | ESD protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110106372.9A CN102761115B (en) | 2011-04-27 | ESD protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102761115A CN102761115A (en) | 2012-10-31 |
| CN102761115B true CN102761115B (en) | 2016-11-30 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829411A (en) * | 2005-02-24 | 2006-09-06 | 三星电子株式会社 | Electrostatic discharge circuit |
| CN1933155A (en) * | 2005-09-13 | 2007-03-21 | 冲电气工业株式会社 | Semiconductor device |
| CN101421896A (en) * | 2006-04-21 | 2009-04-29 | 沙诺夫公司 | ESD clamp control by detection of power state |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829411A (en) * | 2005-02-24 | 2006-09-06 | 三星电子株式会社 | Electrostatic discharge circuit |
| CN1933155A (en) * | 2005-09-13 | 2007-03-21 | 冲电气工业株式会社 | Semiconductor device |
| CN101421896A (en) * | 2006-04-21 | 2009-04-29 | 沙诺夫公司 | ESD clamp control by detection of power state |
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