CN102761115A - Electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection circuit Download PDFInfo
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- CN102761115A CN102761115A CN2011101063729A CN201110106372A CN102761115A CN 102761115 A CN102761115 A CN 102761115A CN 2011101063729 A CN2011101063729 A CN 2011101063729A CN 201110106372 A CN201110106372 A CN 201110106372A CN 102761115 A CN102761115 A CN 102761115A
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Abstract
The invention relates to an electrostatic discharge protection circuit which comprises an electrostatic discharge detection circuit an a plurality of power clamp circuit, wherein the electrostatic discharge detection circuit is electrically connected to a first high-voltage power line, a second high-voltage power line and at least one low-voltage power line, and is used for detecting the static electricity of the first high-voltage power line and the static electricity of the second high-voltage power line; and the electrostatic discharge detection circuit comprises a first trigger unit and a second trigger unit, which are respectively electrically connected to the first high-voltage power line and the second high-voltage power line; and each power clamp circuit is respectively provided with a trigger point, and the trigger point is electrically connected to the first trigger unit and the second trigger unit.
Description
Technical field
The present invention relates to a kind of ESD protection circuit, relate in particular to a kind of ESD protection circuit that is used to protect the integrated circuit that is electrically connected at least two source line group.
Background technology
Along with scientific and technological progress, integrated circuit processing technique also constantly progresses greatly thereupon, but therefore various electronic circuit aggregations/form on the one chip.IC chip can be divided into core circuit and input/output circuitry at present, and core circuit uses the voltage source of different sizes to drive respectively with input/output circuitry.In order to make core circuit and input/output circuitry can receive extraneous voltage source, can be provided with the core power supply connection pad and the I/O power supply connection pad of conduction on the IC chip.
Yet; When chip encapsulation, test, transportation, processing, etc. in the process; These connection pads also are easy to because contact with the static power supply in the external world, and the improper electric power of static is conducted to chip internal, and and then cause the damage of chip internal circuit; This phenomenon be so-called static discharge (electrostatic discharge, ESD).Therefore, be used for protecting IC chip to avoid the ESD protection circuit of damage of electrostatic discharge (ESD protection circuit), also therefore become more important along with improving of integrated circuit technology.
Please refer to Fig. 1, Fig. 1 is the circuit diagram that becomes known for protecting the ESD protection circuit of the integrated circuit that uses two groups of source line group.As shown in Figure 1; Each is organized source line group 10 and has a high-voltage power-line 10a and a low-tension supply line 10b respectively; And electrostatic discharge event possibly occur in each high-voltage power-line 10a and each low-tension supply line 10b, and flows to other high-voltage power-lines 10a and low-tension supply line 10b.In order to protect the integrated circuit that uses these two groups of source line group 10; Known ESD protection circuit 12 electrically connects two groups of source line group 10 so far; And comprise four power supply clamped circuits 14, be electrically connected at respectively between each high-voltage power-line 10a and each the low-tension supply line 10b.And each power supply clamped circuit 14 includes an electric capacity 16, a resistance 18, one the one N type metal oxide semiconductor (NMOS) transistor 20, one the 2nd N type metal oxide semiconductor transistor 22 and a diode 24 respectively.Each electric capacity 16 is electrically connected at respectively between the grid of corresponding high-voltage power-line 10a and each N type metal oxide semiconductor transistor 20, and each resistance 18 is electrically connected at respectively between the grid of corresponding low-tension supply line 10b and each N type metal oxide semiconductor transistor 20.By this; In each power supply clamped circuit 14; When static discharge occurs in high-voltage power-line 10a; The resistance-capacitance circuit that is made up of electric capacity 16 and resistance 18 can provide the grid of a high-voltage to a N type metal oxide semiconductor transistor 20, to open a N type metal oxide semiconductor transistor 20.In addition; Drain electrode of each N type metal oxide semiconductor transistor 20 and the base stage that source electrode is electrically connected to corresponding high-voltage power-line 10a and each the 2nd N type metal oxide semiconductor transistor 22 respectively; Therefore when a N type metal oxide semiconductor transistor 20 is unlocked; The static that occurs in high-voltage power-line 10a can pass through a N type metal oxide semiconductor transistor 20; And trigger the 2nd N type metal oxide semiconductor transistor 22, the 2nd N type metal oxide semiconductor transistor 22 is unlocked.The drain electrode and the source electrode of each the 2nd N type metal oxide semiconductor transistor 22 are electrically connected to corresponding high-voltage power-line 10a and low-tension supply line 10b respectively, and the grid of each the 2nd N type metal oxide semiconductor transistor 22 is electrically connected to corresponding low-tension supply line 10b.When the 2nd N type metal oxide semiconductor transistor 22 is unlocked; The static that occurs in high-voltage power-line 10a can pass through the 2nd N type metal oxide semiconductor transistor 22; And be directed to low-tension supply line 10b, by this can be with electrostatic guide to the low-tension supply line 10b of high-voltage power-line 10a.In addition, the anode of each diode 24 and negative electrode are electrically connected to corresponding low-tension supply line 10b and high-voltage power-line 10a respectively, make the static of low-tension supply line 10b can be led to high-voltage power-line 10a.
Hence one can see that; Need to electrically connect a power supply clamped circuit 14 between each high-voltage power-line 10a and each the low-tension supply line 10b and guide the static that occurs in each high-voltage power-line 10a; And each power supply clamped circuit 14 need be provided with electric capacity 16 and a resistance 18; Detect the static that occurs in each high-voltage power-line 10a as testing circuit, so that the grid of high potential to a N type metal oxide semiconductor transistor 20 to be provided.Therefore, be example with two groups of source line group 10, need four power supply clamped circuits 14 to protect.Therefore and when the group number of source line group 10 increased to three groups, the quantity of power supply clamped circuit 14 then need increase to nine, also must increase by nine electric capacity 16 and nine resistance 18 are used as testing circuit.Yet; In known IC chip; Electric capacity 16 accounts for a certain proportion of area of IC chip with resistance 18; Therefore get over for a long time when the quantity of the required source line group 10 of IC chip, the electric capacity 16 of ESD protection circuit 12 also must be many more with the quantity of resistance 18, and then the size of limit ic chip.
In view of this, reducing the electric capacity of ESD protection circuit and the quantity of resistance is an important issue of industry in fact.
Summary of the invention
One of main purpose of the present invention is to provide a kind of ESD protection circuit, to reduce the quantity of electric capacity and resistance.
For reaching above-mentioned purpose, the present invention provides a kind of ESD protection circuit, is electrically connected at least two source line group.Source line group comprises one first high-voltage power-line, one first low-tension supply line, one second high-voltage power-line and one second low-tension supply line.ESD protection circuit includes an electrostatic discharge testing circuit and a plurality of power supply clamped circuit.Electrostatic discharge testing circuit is electrically connected at least one of first high-voltage power-line, second high-voltage power-line and the first low-tension supply line and the second low-tension supply line; Be used to detect the static of first high-voltage power-line and the static of second high-voltage power-line; And electrostatic discharge testing circuit includes one first trigger element and one second trigger element, is electrically connected to first high-voltage power-line and second high-voltage power-line respectively.The power supply clamped circuit is electrically connected to source line group, and has a trigger point respectively, and wherein the trigger point is electrically connected to first trigger element and second trigger element.
ESD protection circuit of the present invention is through being arranged at single electrostatic discharge testing circuit the outer size of avoiding increasing because of the quantity of power supply clamped circuit limit ic of each power supply clamped circuit.
Description of drawings
Fig. 1 is the circuit diagram that becomes known for protecting the ESD protection circuit of the integrated circuit that uses two groups of power supplys.
Fig. 2 is the block schematic diagram of the ESD protection circuit of first preferred embodiment of the invention.
Fig. 3 is the sketch map of the electrostatic discharge testing circuit of first preferred embodiment of the invention.
Fig. 4 is the sketch map of the power supply clamped circuit of first preferred embodiment of the invention.
Fig. 5 is the sketch map of the electrostatic discharge testing circuit of second preferred embodiment of the invention.
Fig. 6 is an embodiment of the electrostatic discharge testing circuit of second preferred embodiment of the invention.
Fig. 7 is the sketch map of the power supply clamped circuit of second preferred embodiment of the invention.
Fig. 8 is the sketch map of the ESD protection circuit of third preferred embodiment of the invention.
[main element symbol description]
10 source line group 10a high-voltage power-lines
10b low-tension supply line 12 ESD protection circuits
14 power supply clamped circuits, 16 electric capacity
18 resistance 20 a N type metal oxide half
The conductor transistor
22 the 2nd N type burnings, 24 diodes
The thing semiconductor transistor
100 ESD protection circuits, 102 first source line group
The 102a first high-voltage power-line 102b first low-tension supply line
104 second source line group 104a, second high-voltage power-line
The 104b second low-tension supply line 106 electrostatic discharge testing circuits
108 power supply clamped circuit 108a, the first power supply clamped circuit
108b second source clamped circuit 108c the 3rd power supply clamped circuit
108d the 4th power supply clamped circuit 108e the 5th power supply clamped circuit
108f the 6th power supply clamped circuit 108g the 7th power supply clamped circuit
108h the 8th power supply clamped circuit 108i the 9th power supply clamped circuit
110 trigger points, 112 connecting lines
114 first trigger elements, 116 second trigger elements
118 the one N type burnings, 120 first electric capacity
The thing semiconductor transistor
122 second electric capacity, 124 first resistance
125 first diodes 126 the 3rd metal-oxide semiconductor (MOS)
Transistor
128 second diodes 130 the 4th metal-oxide semiconductor (MOS)
Transistor
132 the 3rd diodes, 1 34 five metals belongs to oxide semiconductor
Transistor
136 the 4th diodes 138 the 6th metal-oxide semiconductor (MOS)
Transistor
140 the 5th diodes, 150 inverters
152 electrostatic discharge testing circuits 154 the 3rd electric capacity
156 second resistance 158 the 3rd resistance
160 P type metal oxides are partly led 162 the 2nd N type metal oxides half
Body transistor conductor transistor
170 the 3rd source line group 170a the 3rd high-voltage power-line
170b the 3rd low-tension supply line 172 ESD protection circuits
174 electrostatic discharge testing circuits 176 the 3rd trigger element
178 the 4th electric capacity 180 the 7th metal-oxide semiconductor (MOS)
Transistor
B base stage D drain electrode
G grid S source electrode
Embodiment
Please refer to Fig. 2, Fig. 2 is the circuit diagram of the ESD protection circuit of first preferred embodiment of the invention.As shown in Figure 2, ESD protection circuit 100 is electrically connected at least two source line group 102,104, to be used to protect the various static discharge patterns that occur in source line group 102.Source line group 102,104 comprises one first source line group 102 and a second source line group 104; Wherein first source line group 102 has one first high-voltage power-line 102a and one first low-tension supply line 102b, and second source line group 104 has one second high-voltage power-line 104a and one second low-tension supply line 104b.In the present embodiment, the first high-voltage power-line 102a provides one first voltage, for example: and 2.5 volts or 3.3 volts, and the first low-tension supply line 102b is an earth terminal then, makes first source line group 102 can be used for driving I/O (I/O) circuit.The second high-voltage power-line 104a provides one second voltage; For example: 1.0 volts; And the second low-tension supply line 104b is another earth terminal, makes first voltage greater than second voltage, and second source line group 104 can be used for driving the withstand voltage core circuit low than input/output circuitry by this.The first high-voltage power-line 102a of the present invention and the second high-voltage power-line 104a are not limited to provide above-mentioned voltage.And; ESD protection circuit 100 comprises an electrostatic discharge testing circuit 106 and a plurality of power supply clamped circuit 108; Wherein each power supply clamped circuit 108 has a trigger point (triggernode) 110 respectively, and each power supply clamped circuit 108 is respectively applied for static to the first low-tension supply line 102b and the second low-tension supply line 104b that release occurs in the first high-voltage power-line 102a and the second high-voltage power-line 104a.Electrostatic discharge testing circuit 106 is electrically connected at least one and each trigger point 110 of the first high-voltage power-line 102a, the second high-voltage power-line 104a, the first low-tension supply line 102b and the second low-tension supply line 104b, to be used to detect an electrostatic discharge event that occurs in the first high-voltage power-line 102a and another electrostatic discharge event that occurs in the second high-voltage power-line 104a.In addition; ESD protection circuit 100 also comprises a connecting line 112; Be used to electrically connect the trigger point 110 of electrostatic discharge testing circuit 106 and each power supply clamped circuit 108; The triggering signal that electrostatic discharge testing circuit 106 is produced can be passed to each power supply clamped circuit 108, and opens each power supply clamped circuit 108.
Please refer to Fig. 3, and in the lump with reference to figure 2.Fig. 3 is the sketch map of the electrostatic discharge testing circuit of first preferred embodiment of the invention.Like Fig. 2 and shown in Figure 3, electrostatic discharge testing circuit 106 comprises one first trigger element 114 and one second trigger element 116.First trigger element 114 is electrically connected to the first high-voltage power-line 102a and trigger point 110; And one first triggering signal to connecting line 112, electrostatic discharge testing circuit 106 is provided when detecting the electrostatic discharge event that occurs in the first high-voltage power-line 102a; Make the power supply clamped circuit 108 that is electrically connected to connecting line 112 triggered and to open, and then provide electrostatic discharging path to discharge the static that occurs in the first high-voltage power-line 102a by first triggering signal.In addition; Second trigger element 116 is electrically connected to the second high-voltage power-line 104a and trigger point 110; And one second triggering signal to connecting line 112, electrostatic discharge testing circuit 106 is provided when detecting the electrostatic discharge event that occurs in the second high-voltage power-line 104a; Make the power supply clamped circuit 108 that is electrically connected to connecting line 112 triggered and to open, and then provide electrostatic discharging path to discharge the static of the second high-voltage power-line 104a by second triggering signal.In the present embodiment, first trigger element 114 and second trigger element 116 can be respectively one the one N type metal oxide semiconductor (NMOS) transistor 118.Wherein, The grid G of each N type metal semiconductor transistor 118 is electrically connected to each other; The drain D of each N type metal semiconductor transistor 118 is electrically connected to the first high-voltage power-line 102a and the second high-voltage power-line 104a respectively; And the source S of each N type metal oxide semiconductor transistor 118 is electrically connected to connecting line 112, to be electrically connected to each trigger point 110.And; Electrostatic discharge testing circuit 106 also comprises one first electric capacity 120, one second electric capacity 122 and one first resistance 124, to be used to detect electrostatic discharge event that occurs in the first high-voltage power-line 102a and the electrostatic discharge event that occurs in the second high-voltage power-line 104a.First electric capacity 120 is electrically connected between the grid G of the first high-voltage power-line 102a and a N type metal oxide semiconductor transistor 118; And second electric capacity 122 is electrically connected between the grid G of the second high-voltage power-line 104a and a N type metal oxide semiconductor transistor 118, and first resistance 124 is electrically connected between the grid G and the second low-tension supply line 104b of each N type metal oxide semiconductor transistor 118.In other embodiments of the invention, first resistance 124 also can be electrically connected between the grid G and the first low-tension supply line 102b of a N type metal oxide semiconductor transistor 118.Perhaps; Electrostatic discharge testing circuit 106 also can also comprise a resistance except first resistance 124 is electrically connected between grid G and the second low-tension supply line 104b of a N type metal oxide semiconductor transistor 118, be electrically connected between the grid G and the first low-tension supply line 102b of a N type metal oxide semiconductor transistor 118.
Hence one can see that; First electric capacity 120 and first resistance 124 constitute a resistance-capacitance circuit (RC circuit); Be electrically connected between the first high-voltage power-line 102a and the second low-tension supply line 104b; Therefore when electrostatic discharge event occurred in the first high-voltage power-line 102a, static can promote the current potential of the grid G of each N type metal oxide semiconductor transistor 118 through first electric capacity 120, and then opens a N type metal oxide semiconductor transistor 118.By this, static can be directed to connecting line 112 from the first high-voltage power-line 102a, with each power supply clamped circuit 118 of further triggering.Likewise; Second electric capacity 122 also constitutes another resistance-capacitance circuit with first resistance 124; Be electrically connected between the second high-voltage power-line 104a and the second low-tension supply line 104b; Therefore when electrostatic discharge event occurred in the second high-voltage power-line 104a, each N type metal oxide semiconductor transistor 118 can be unlocked.By this, static can be directed to connecting line 112 from the second high-voltage power-line 104a, with each power supply clamped circuit 108 of further triggering.In addition; The electrostatic discharge testing circuit 106 of present embodiment also comprises one first diode 125; And the anode of first diode 125 and negative electrode are electrically connected to the second high-voltage power-line 104a and the first high-voltage power-line 102a respectively; Being used to promote the electrostatic discharge capacity of the second high-voltage power-line 104a, and protection is born the lower core circuit of voltage capability and is avoided electrostatic breakdown effectively.
In other embodiments of the invention; ESD protection circuit 100 can comprise two diodes in addition; Anode of one of them and negative electrode are electrically connected to the first high-voltage power-line 102a and the second high-voltage power-line 104a respectively; And wherein another person's anode and negative electrode are electrically connected to the second high-voltage power-line 104a and the first high-voltage power-line 102a respectively, make the static of the first high-voltage power-line 102a or the second high-voltage power-line 104a can be directed to the second high-voltage power-line 104a or the first high-voltage power-line 102a.In addition; ESD protection circuit 100 also can comprise two diodes in addition; Anode of one of them and negative electrode are electrically connected to the first low-tension supply line 102b and the second low-tension supply line 104b respectively; And wherein another person's anode and negative electrode are electrically connected to the second low-tension supply line 104b and the first low-tension supply line 102b respectively, can be directed to the second low-tension supply line 104b or the first low-tension supply line 102b with the static of the first low-tension supply line 102b or the second low-tension supply line 104b.
Please refer to Fig. 4, and in the lump with reference to figure 2, Fig. 4 is the sketch map of the power supply clamped circuit of first preferred embodiment of the invention.Like Fig. 2 and shown in Figure 4, the power supply clamped circuit 108 of present embodiment comprises one first power supply clamped circuit 108a, a second source clamped circuit 108b, one the 3rd power supply clamped circuit 108c and one the 4th power supply clamped circuit 108d.The first power supply clamped circuit 108a is electrically connected between the first high-voltage power-line 102a and the first low-tension supply line 102b; Be used to provide two electrostatic discharging paths, respectively from first high-voltage power-line 102a to the first low-tension supply line 102b and from first low-tension supply line 102b to the first high-voltage power-line 102a.Second source clamped circuit 108b is electrically connected between the first high-voltage power-line 102a and the second low-tension supply line 104b; Be used to provide two electrostatic discharging paths, respectively from first high-voltage power-line 102a to the second low-tension supply line 104b and from second low-tension supply line 104b to the first high-voltage power-line 102a.The 3rd power supply clamped circuit 108c is electrically connected between the second high-voltage power-line 104a and the first low-tension supply line 102b; Be used to provide two electrostatic discharging paths, respectively from second high-voltage power-line 104a to the first low-tension supply line 102b and from first low-tension supply line 102b to the second high-voltage power-line 104a.The 4th power supply clamped circuit 108d is electrically connected between the second high-voltage power-line 104a and the second low-tension supply line 104b; Be used to provide two electrostatic discharging paths, respectively from second high-voltage power-line 104a to the second low-tension supply line 104b and from second low-tension supply line 104b to the second high-voltage power-line 104a.By this, the first power supply clamped circuit 108a, a second source clamped circuit 108b, one the 3rd power supply clamped circuit 108c and one the 4th power supply clamped circuit 108d can protect the integrated circuit that is electrically connected at the first high-voltage power-line 102a, the first low-tension supply line 102b, the second high-voltage power-line 104a and the second low-tension supply line 104b.
The first power supply clamped circuit 108a includes one the 3rd metal oxide semiconductor transistor 126 and one second diode 128, and second source clamped circuit 108b includes one the 4th metal oxide semiconductor transistor 130 and one the 3rd diode 132.The 3rd power supply clamped circuit 108c includes a five metals and belongs to oxide semi conductor transistor 134 and one the 4th diode 136, and the 4th power supply clamped circuit 108d includes one the 6th metal oxide semiconductor transistor 138 and one the 5th diode 140.In the present embodiment, the 3rd metal oxide semiconductor transistor 126, the 4th metal oxide semiconductor transistor 130, five metals belongs to oxide semi conductor transistor 134 and the 6th metal oxide semiconductor transistor 138 is N type metal oxide semiconductor transistor.And the source S of the 3rd N type metal oxide semiconductor transistor 126 and grid G are electrically connected to the first low-tension supply line 102b, and the drain D of the 3rd N type metal oxide semiconductor transistor 126 is electrically connected to the first high-voltage power-line 102a.The source S of the 4th N type metal oxide semiconductor transistor 130 and grid G are electrically connected to the second low-tension supply line 104b, and the drain D of the 4th N type metal oxide semiconductor transistor 130 is electrically connected to the first high-voltage power-line 102a.The source S of the 5th N type metal oxide semiconductor transistor 134 and grid G are electrically connected to the first low-tension supply line 102b, and the drain D of the 5th N type metal oxide semiconductor transistor 134 is electrically connected to the second high-voltage power-line 104a.The source S of the 6th N type metal oxide semiconductor transistor 138 and grid G are electrically connected to the second low-tension supply line 104b, and the drain D of the 6th N type metal oxide semiconductor transistor 138 is electrically connected to the second high-voltage power-line 104a.By this; The static of the first high-voltage power-line 102a can be released into the first low-tension supply line 102b and the second low-tension supply line 104b via opening the 3rd N type metal oxide semiconductor transistor 126 and the 4th N type metal oxide semiconductor transistor 130, and the static of the second high-voltage power-line 104a can be released into the first low-tension supply line 102b and the second low-tension supply line 104b via opening the 5th N type metal oxide semiconductor transistor 134 and the 6th N type metal oxide semiconductor transistor 138.The 3rd metal oxide semiconductor transistor 126 of the present invention, the 4th metal oxide semiconductor transistor 130, five metals belongs to oxide semi conductor transistor 134 and the 6th metal oxide semiconductor transistor 138 is not limited to N type metal oxide semiconductor transistor; Also can be P-type mos (PMOS) transistor; And its electric connection mode is for to be electrically connected to corresponding high-voltage power-line with transistorized source electrode of each P-type mos and grid, and its drain electrode then is electrically connected to corresponding low-tension supply line.
In the present embodiment; The trigger point 110 of the first power supply clamped circuit 108a is the base stage B of the 3rd N type metal oxide semiconductor transistor 126; The trigger point 110 of second source clamped circuit 108b is the base stage B of the 4th N type metal oxide semiconductor transistor 130; The trigger point 110 of the 3rd power supply clamped circuit 108c is the base stage B of the 5th N type metal oxide semiconductor transistor 134, and the trigger point 110 of the 4th power supply clamped circuit 108d is the base stage B of the 6th metal oxide semiconductor transistor 138.That is; The transistor that the 3rd N type metal oxide semiconductor transistor 126, the 4th N type metal oxide semiconductor transistor 130, the 5th N type metal oxide semiconductor transistor 134 and the 6th N type metal oxide semiconductor transistor 138 trigger for matrix, but not as limit.And; The 3rd N type metal oxide semiconductor transistor 126 and the 4th N type metal oxide semiconductor transistor 130 designed to be used and bear first voltage that the first high-voltage power-line 102a is provided; That is receive electrostatic breakdown for fear of the core circuit that is electrically connected to identical voltage; The 3rd N type metal oxide semiconductor transistor 126 is identical with the thickness of the grid oxic horizon of the 4th N type metal oxide semiconductor transistor 130, and first voltage that needs to cooperate the first high-voltage power-line 102a to be provided is done design.Likewise, the 5th N type metal oxide semiconductor transistor 134 and the 6th N type metal oxide semiconductor transistor 138 designed to be used and bear second voltage that the second high-voltage power-line 104a is provided.That is; Input/output circuitry for fear of being electrically connected to identical voltage receives electrostatic breakdown, and the 5th N type metal oxide semiconductor transistor 134 is done design with second voltage that the thickness of the grid oxic horizon of the 6th N type metal oxide semiconductor transistor 138 need cooperate the second high-voltage power-line 104a to be provided.
In addition; The anode of second diode 128 and negative electrode are electrically connected to the first low-tension supply line 102b and the first high-voltage power-line 102a respectively; The anode of the 3rd diode 132 and negative electrode are electrically connected to the second low-tension supply line 104b and the first high-voltage power-line 102a respectively; The anode of the 4th diode 136 and negative electrode are electrically connected to the first low-tension supply line 102b and the second high-voltage power-line 104a respectively, and the anode of the 5th diode 140 and negative electrode are electrically connected to the second low-tension supply line 104b and the second high-voltage power-line 104a respectively.By this; The static of the first low-tension supply line 102b can be released into the first high-voltage power-line 102a and the second high-voltage power-line 104a via second diode 128 and the 4th diode 136 respectively, and the static of the second low-tension supply line 104b can be released into the first high-voltage power-line 102a and the second high-voltage power-line 104a via the 3rd diode 132 and the 5th diode 140 respectively.
From the above; The ESD protection circuit 100 of present embodiment is electrically connected at least two source line group 102,104; And single electrostatic discharge testing circuit 106 is arranged at outside each power supply clamped circuit 108, can avoids increasing the size of limit ic by this because of the quantity of power supply clamped circuit 108.And; The single electrostatic discharge testing circuit 106 of present embodiment to each source line group 102,104 first trigger element 114 is set respectively and second trigger element 116 produces triggering signal; And triggering signal is passed to each power supply clamped circuit 108 through connecting line 112; Therefore can open each power supply clamped circuit 108, carrying out static discharge, and protection simultaneously is electrically connected to the core circuit and the input/output circuitry of different voltages.
Electrostatic discharge testing circuit of the present invention and power supply clamped circuit do not exceed with the foregoing description.Hereinafter will continue to disclose other embodiments of the invention or change shape, so for the purpose of simplifying the description and highlight each embodiment or change the difference between the shape hereinafter use same numeral mark similar elements, and no longer counterweight again part give unnecessary details.
Please refer to Fig. 5, Fig. 5 is the sketch map of the electrostatic discharge testing circuit of second preferred embodiment of the invention.As shown in Figure 5, compared to first preferred embodiment, first trigger element 114 and second trigger element 116 of present embodiment are respectively an inverter 150, and each inverter 150 has an input 150a and an output 150b.And the input 150a of each inverter 150 is electrically connected to each other, and the output 150b of each inverter 150 is electrically connected to connecting line 112.In addition; The electrostatic discharge testing circuit 152 of present embodiment comprises one the 3rd electric capacity 154, one second resistance 156 and one the 3rd resistance 158; Wherein the 3rd electric capacity 154 is electrically connected between the input 150a and the second low-tension supply line 104b; Second resistance 156 is electrically connected between the first high-voltage power-line 102a and the input 150a, and the 3rd resistance 158 is electrically connected between the second high-voltage power-line 104a and the input 150a.
In order to clearly demonstrate the inverter of present embodiment, please refer to Fig. 6, and in the lump with reference to figure 5.Fig. 6 is an embodiment of the electrostatic discharge testing circuit of second preferred embodiment of the invention.Like Fig. 5 and shown in Figure 6, each inverter 150 of present embodiment comprises a P-type mos transistor 160 and one the 2nd N type metal oxide semiconductor transistor 162 respectively.Wherein, The grid G of each P-type mos transistor 160 electrically connects with the grid G of each the 2nd N type metal oxide semiconductor transistor 162 respectively; And the grid G of each P-type mos transistor 160 is electrically connected to each other, and as each input 150a.By this; The 3rd electric capacity 154 is electrically connected between the grid G and the second low-tension supply line 104b of each P-type mos transistor 160; Second resistance 156 is electrically connected between the grid G of the first high-voltage power-line 102a and P-type mos transistor 160, and the 3rd resistance 158 is electrically connected between the grid G of the second high-voltage power-line 104a and P-type mos transistor 160.The drain D of each P-type mos transistor 160 is electrically connected to the drain D of each the 2nd N type metal oxide semiconductor transistor 162 respectively; And respectively as each output 150b, and the drain D of each P-type mos transistor 160 is electrically connected to connecting line 112 respectively.In addition; The source S of each P-type mos transistor 160 is electrically connected to the first high-voltage power-line 102a and the second high-voltage power-line 104a respectively, and the source S of each the 2nd N type metal oxide semiconductor transistor 162 is electrically connected to the second low-tension supply line 104b respectively.In other embodiments of the invention; The 3rd electric capacity 154 also can be electrically connected between the grid G and the first low-tension supply line 102b of P-type mos transistor 160, and the source S of each the 2nd N type metal oxide semiconductor transistor 162 then is electrically connected to the first low-tension supply line 102b.
In the present embodiment, when electrostatic discharge event occurred in the first high-voltage power-line 102a, the current potential of the grid G of each P-type mos transistor 160 was in electronegative potential, therefore opened each P-type mos transistor 160.By this, being electrically connected to the P type metal semiconductor transistor 160 of the first high-voltage power-line 102a can be with electrostatic guide to connecting line 112, with each power supply clamped circuit 108 of further triggering.Likewise; When electrostatic discharge event occurs in the second high-voltage power-line 104a; The grid G of each P-type mos transistor 160 is in electronegative potential and is unlocked, and with electrostatic guide to the connecting line 112 with the second high-voltage power-line 104a, therefore triggers each power supply clamped circuit 108.
Please refer to Fig. 7, Fig. 7 is the sketch map of the power supply clamped circuit of second preferred embodiment of the invention.As shown in Figure 7; Compared to first preferred embodiment; The trigger point 110 of the first power supply clamped circuit 108a of present embodiment is the grid G of the 3rd N type metal oxide semiconductor transistor 126, and the trigger point 110 of second source clamped circuit 108b is the grid G of the 4th N type metal oxide semiconductor transistor 130.And; The trigger point 110 of the 3rd power supply clamped circuit 108c of present embodiment is the grid G of the 5th N type metal oxide semiconductor transistor 134, and the trigger point 110 of the 4th power supply clamped circuit 108d is the grid G of the 6th N type metal oxide semiconductor transistor 138.
In addition; ESD protection circuit of the present invention is not limited to the foregoing description; In other embodiments of the invention; ESD protection circuit also can be made up of the electrostatic discharge testing circuit of first preferred embodiment and the power supply clamped circuit of second preferred embodiment, and perhaps ESD protection circuit can be made up of the electrostatic discharge testing circuit of second preferred embodiment and the power supply clamped circuit of first preferred embodiment.
In addition, the present invention is not limited to be only applicable to two groups of source line group, also applicable to the plural groups source line group.Please refer to Fig. 8, Fig. 8 is the sketch map of the ESD protection circuit of third preferred embodiment of the invention.As shown in Figure 8, compared to first preferred embodiment, the source line group of present embodiment also comprises one the 3rd source line group 170, and the 3rd source line group 170 has one the 3rd high-voltage power-line 170a and one the 3rd low-tension supply line 170b.In the ESD protection circuit 172 of present embodiment; Electrostatic discharge testing circuit 174 also comprises one the 3rd trigger element 176 and one the 4th electric capacity 178; And the 3rd trigger element 176 is one the 7th metal oxide semiconductor transistor 180; Wherein the 7th metal oxide semiconductor transistor 180 can be N type metal oxide semiconductor transistor, but is not limited thereto.The grid G of the 7th N type metal oxide semiconductor transistor 180 is electrically connected to the grid G of each N type metal oxide semiconductor transistor 118, and the drain D of the 7th N type metal oxide semiconductor transistor 180 and source S are electrically connected to the 3rd high-voltage power-line 170a and connecting line 112 respectively.And the 4th electric capacity 178 is electrically connected between the grid G and the 3rd high-voltage power-line 170a of the 7th N type metal oxide semiconductor transistor 180.In addition; The power supply clamped circuit 108 of present embodiment also comprises one the 5th power supply clamped circuit 108e, one the 6th power supply clamped circuit 108f, one the 7th power supply clamped circuit 108g, one the 8th power supply clamped circuit 108h and one the 9th power supply clamped circuit 108i, is electrically connected between the first high-voltage power-line 102a and the 3rd low-tension supply line 170b respectively, between the second high-voltage power-line 104a and the 3rd low-tension supply line 170b, between the 3rd high-voltage power-line 170a and the first low-tension supply line 102b, between the 3rd high-voltage power-line 170a and the second low-tension supply line 104b and between the 3rd high-voltage power-line 170a and the 3rd low-tension supply line 170b.Because each power supply clamped circuit of present embodiment also comprises a N type metal oxide semiconductor transistor AND gate one diode respectively; Only be to be electrically connected between different high-voltage power-lines and the low-tension supply line with the difference of first preferred embodiment, therefore repeat no more at this.
In other embodiments of the invention; First resistance 124 also can be electrically connected between the grid G and the first low-tension supply line 102b of a N type metal oxide semiconductor transistor 118, or is electrically connected between the grid G and the 3rd low-tension supply line 170b of a N type metal oxide semiconductor transistor 118.Perhaps; Electrostatic discharge testing circuit 106 also can also comprise at least one resistance except first resistance 124 is electrically connected between grid G and the second low-tension supply line 104b of a N type metal oxide semiconductor transistor 118, be electrically connected between grid G and the first low-tension supply line 102b of a N type metal oxide semiconductor transistor 118 or between the grid G and the 3rd low-tension supply line 170b of a N type metal oxide semiconductor transistor 118.Perhaps; Electrostatic discharge testing circuit 106 also can also comprise two resistance except first resistance 124 is electrically connected between grid G and the second low-tension supply line 104b of a N type metal oxide semiconductor transistor 118, be electrically connected between grid G and the first low-tension supply line 102b of a N type metal oxide semiconductor transistor 118 respectively and between the grid G and the 3rd low-tension supply line 170b of a N type metal oxide semiconductor transistor 118.
Hence one can see that, and compared to first preferred embodiment, the source line group of present embodiment is only added one group, protects the integrated circuit that is electrically connected to source line group but ESD protection circuit need increase by five power supply clamped circuits.
The ESD protection circuit of present embodiment with electrostatic discharge testing circuit be arranged at each power supply clamped circuit outside; And only in single electrostatic discharge testing circuit, increase a metal oxide semiconductor transistor and an electric capacity in addition and promptly can be used for triggering each power supply clamped circuit, therefore can decrease in the area that the required increase of electrostatic discharge testing circuit is set in each power supply clamped circuit.
In sum, ESD protection circuit of the present invention is through being arranged at single electrostatic discharge testing circuit the outer size of avoiding increasing because of the quantity of power supply clamped circuit limit ic of each power supply clamped circuit.
The above is merely the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (19)
1. ESD protection circuit; Be electrically connected at least two source line group; Said source line group comprises one first high-voltage power-line, one first low-tension supply line, one second high-voltage power-line and one second low-tension supply line, and this ESD protection circuit includes:
One electrostatic discharge testing circuit; Be electrically connected at least one of this first high-voltage power-line, this second high-voltage power-line and this first low-tension supply line and this second low-tension supply line; Be used to detect an electrostatic discharge event that occurs in this first high-voltage power-line and another electrostatic discharge event that occurs in this second high-voltage power-line; And this electrostatic discharge testing circuit includes one first trigger element and one second trigger element, is electrically connected to this first high-voltage power-line and this second high-voltage power-line respectively; And
A plurality of power supply clamped circuits are electrically connected to said source line group, and have a trigger point respectively, and wherein said trigger point is electrically connected to this first trigger element and this second trigger element.
2. ESD protection circuit as claimed in claim 1; Wherein this first trigger element and this second trigger element are respectively one the one N type metal oxide semiconductor transistor; The transistorized grid of a said N type metal oxide semiconductor is electrically connected to each other; Respectively a N type metal oxide semiconductor transistor drain is electrically connected to this first high-voltage power-line and this second high-voltage power-line respectively, and the transistorized source electrode of a said N type metal oxide semiconductor is electrically connected to said trigger point.
3. ESD protection circuit as claimed in claim 2; Wherein this electrostatic discharge testing circuit also comprises one first electric capacity, one second electric capacity and one first resistance; This first electric capacity is electrically connected between this first high-voltage power-line and the transistorized grid of a said N type metal oxide semiconductor; This second electric capacity is electrically connected between this second high-voltage power-line and the transistorized grid of a said N type metal oxide semiconductor, and this first resistance is electrically connected between this second low-tension supply line and the transistorized grid of a said N type metal oxide semiconductor.
4. ESD protection circuit as claimed in claim 1, wherein this electrostatic discharge testing circuit also comprises one first diode, and the anode of this first diode and negative electrode are electrically connected to this second high-voltage power-line and this first high-voltage power-line respectively.
5. ESD protection circuit as claimed in claim 1, wherein this first trigger element and this second trigger element are respectively an inverter, and respectively this inverter has an input.
6. ESD protection circuit as claimed in claim 5; Wherein respectively this inverter comprises a P-type mos transistor and one the 2nd N type metal oxide semiconductor transistor respectively; Transistorized grid of said P-type mos and the transistorized grid of said the 2nd N type metal oxide semiconductor are electrically connected to said input, and the transistorized source electrode of said P-type mos is electrically connected to this first high-voltage power-line and this second high-voltage power-line respectively.
7. ESD protection circuit as claimed in claim 5; Wherein this electrostatic discharge testing circuit also comprises one the 3rd electric capacity, one second resistance and one the 3rd resistance; The 3rd electric capacity is electrically connected between said input and this second low-tension supply line, and this second resistance and the 3rd resistance is electrically connected between this first high-voltage power-line and the said input respectively and between this second high-voltage power-line and the said input.
8. ESD protection circuit as claimed in claim 1, wherein said power supply clamped circuit comprises:
One first power supply clamped circuit is electrically connected between this first high-voltage power-line and this first low-tension supply line;
One second source clamped circuit is electrically connected between this first high-voltage power-line and this second low-tension supply line;
One the 3rd power supply clamped circuit is electrically connected between this second high-voltage power-line and this first low-tension supply line; And
One the 4th power supply clamped circuit is electrically connected between this second high-voltage power-line and this second low-tension supply line.
9. ESD protection circuit as claimed in claim 8; Wherein this first power supply clamped circuit includes one the 3rd metal oxide semiconductor transistor and one second diode; This second source clamped circuit includes one the 4th metal oxide semiconductor transistor and one the 3rd diode, and the 3rd metal oxide semiconductor transistor and the 4th metal oxide semiconductor transistor are used to bear one first voltage that this first high-voltage power-line is provided.
10. ESD protection circuit as claimed in claim 9; Wherein this trigger point of this first power supply clamped circuit is the base stage of the 3rd metal oxide semiconductor transistor, and this trigger point of this second source clamped circuit is the base stage of the 4th metal oxide semiconductor transistor.
11. ESD protection circuit as claimed in claim 9; Wherein this trigger point of this first power supply clamped circuit is the grid of the 3rd metal oxide semiconductor transistor, and this trigger point of this second source clamped circuit is the grid of the 4th metal oxide semiconductor transistor.
12. ESD protection circuit as claimed in claim 9; Wherein the negative electrode of this second diode and anode are electrically connected to this first high-voltage power-line and this first low-tension supply line respectively, and the negative electrode of the 3rd diode and anode are electrically connected to this first high-voltage power-line and this second low-tension supply line respectively.
13. ESD protection circuit as claimed in claim 8; Wherein the 3rd power supply clamped circuit includes a five metals and belongs to oxide semi conductor transistor and one the 4th diode; The 4th power supply clamped circuit includes one the 6th metal oxide semiconductor transistor and one the 5th diode, and this five metals belongs to oxide semi conductor transistor and the 6th metal oxide semiconductor transistor is used to bear one second voltage that this second high-voltage power-line is provided.
14. ESD protection circuit as claimed in claim 13; Wherein this trigger point of the 3rd power supply clamped circuit is the base stage that this five metals belongs to oxide semi conductor transistor, and this trigger point of the 4th power supply clamped circuit is the base stage of the 6th metal oxide semiconductor transistor.
15. ESD protection circuit as claimed in claim 13; Wherein this trigger point of the 3rd power supply clamped circuit is the grid that this five metals belongs to oxide semi conductor transistor, and this trigger point of the 4th power supply clamped circuit is the grid of the 6th metal oxide semiconductor transistor.
16. ESD protection circuit as claimed in claim 13; Wherein the negative electrode of the 4th diode and anode are electrically connected to this second high-voltage power-line and this first low-tension supply line respectively, and the negative electrode of the 5th diode and anode are electrically connected at this second high-voltage power-line and this second low-tension supply line respectively.
17. ESD protection circuit as claimed in claim 1 also comprises a connecting line, electrically connects this electrostatic discharge testing circuit and said trigger point.
18. ESD protection circuit as claimed in claim 1; Wherein this at least two source line group also comprises one the 3rd high-voltage power-line and one the 3rd low-tension supply line; And this electrostatic discharge testing circuit also comprises one the 3rd trigger element, is electrically connected to the 3rd high-voltage power-line and said trigger point.
19. an ESD protection circuit includes:
One electrostatic discharge testing circuit includes two trigger elements, is used to control two source line group; And
A plurality of power supply clamped circuits are electrically connected to this electrostatic discharge testing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110106372.9A CN102761115B (en) | 2011-04-27 | ESD protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110106372.9A CN102761115B (en) | 2011-04-27 | ESD protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102761115A true CN102761115A (en) | 2012-10-31 |
| CN102761115B CN102761115B (en) | 2016-11-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024016416A1 (en) * | 2022-07-21 | 2024-01-25 | 长鑫存储技术有限公司 | Electrostatic protection circuit, and memory |
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| CN1829411A (en) * | 2005-02-24 | 2006-09-06 | 三星电子株式会社 | Electrostatic discharge circuit |
| CN1933155A (en) * | 2005-09-13 | 2007-03-21 | 冲电气工业株式会社 | Semiconductor device |
| US20090009917A1 (en) * | 2007-07-03 | 2009-01-08 | Hynix Semiconductor, Inc. | Electrostatic discharge device |
| CN101421896A (en) * | 2006-04-21 | 2009-04-29 | 沙诺夫公司 | ESD clamp control by detection of power state |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1829411A (en) * | 2005-02-24 | 2006-09-06 | 三星电子株式会社 | Electrostatic discharge circuit |
| CN1933155A (en) * | 2005-09-13 | 2007-03-21 | 冲电气工业株式会社 | Semiconductor device |
| CN101421896A (en) * | 2006-04-21 | 2009-04-29 | 沙诺夫公司 | ESD clamp control by detection of power state |
| US20090009917A1 (en) * | 2007-07-03 | 2009-01-08 | Hynix Semiconductor, Inc. | Electrostatic discharge device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024016416A1 (en) * | 2022-07-21 | 2024-01-25 | 长鑫存储技术有限公司 | Electrostatic protection circuit, and memory |
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