CN102749574B - Scan test method and scan test circuit - Google Patents
Scan test method and scan test circuit Download PDFInfo
- Publication number
- CN102749574B CN102749574B CN201210249748.6A CN201210249748A CN102749574B CN 102749574 B CN102749574 B CN 102749574B CN 201210249748 A CN201210249748 A CN 201210249748A CN 102749574 B CN102749574 B CN 102749574B
- Authority
- CN
- China
- Prior art keywords
- test
- ram
- scan
- scan chain
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a scan test method to perform scan test on a scan chain with RAM (random access memory), which comprises the following steps: RAM is initialized to enable RMA to be at a predetermined value; the scan chain is under a shift register state to input test vectors, and the RMA predetermined value is maintained; the scan chain is under a working state to load excitation to a primary input end of the scan chain so as to capture the test output value of the scan chain; and the scan chain is under the shift register state to output the test output value. Through the scan test method, the predetermined value of the RAM output end can be obtained without a plurality of test periods, so that the test periods are effectively reduced, and the test time is reduced.
Description
Technical field
The present invention relates to integrated circuit testing and test circuit field, more particularly, relate to a kind of scan testing methods and circuit.
Background technology
Along with the enhancing of chip functions of integrated circuit and the appearance of continuous expansion, the especially SOC (system on a chip) of integrated scale (SOC, System On a Chip), the test of chip becomes more and more difficult.In order to reach certain test coverage, cause the continuous lengthening of test duration, thereby cause testing expense often taller than design cost.Testing cost has become the important component part of product development cost, and the length of test duration also directly has influence on time to market (TTM), and then affects economic benefit.
The fundamental way that solves chip testing efficiency is the method for designing that changes test,, in primary stage of integrated circuit (IC) design just using measurability as one of design object, and sweep test is a kind of design for Measurability technology being most widely used, this technology can just can obtain very high test failure coverage rate within the shorter test duration.
Sweep test is when design, the timing unit in circuit to be transformed into and can be controlled and observable unit, and these timing units are connected into one or more shift registers, is referred to as scan chain.These scan chains can be inputted circuit is set to particular state (controllability) by gated sweep, and the content of scan chain can be shifted out and be observed (observability) by output terminal.
As shown in Figure 1, be the sweep test structural representation based on scan chain.Sweep test is to carry out the residing state of control circuit (shift register state and duty) by scan enable signals (ScanEn).When scan enable signals is effective, the timing unit in scan chain is controlled as shift register state; When scan enable signals is invalid, all timing units in scan chain are controlled as normal operating conditions.Under shift register state, first timing unit of scan chain can be directly by primary input terminal PI(Primary Input) be set to particular value, last timing unit can be at elementary output PO(Primary Output) be directly observed.Therefore, we just can be set to the timing unit scan chain from primary input terminal PI the original state of any needs by the shift function of shift register, and arbitrary internal state of shift register can be moved out to primary output terminal PI, to observe.Now, the input of each timing unit can be regarded the elementary input PPI(Pseudo of a puppet Primary Input as), output can be regarded the elementary output PPO(Pseudo of a puppet Primary Output as), the test Generating Problems of circuit just changes into the test Generating Problems of a combinational circuit.
Sweep test can greatly improve the coverage rate of chip within the shorter test duration, but due to a large amount of RAM(Random Access Memory in SOC system) existence, seriously affected to a certain extent the fault coverage of sweep test.Because the embedded RAM function in SOC is unknown, we are referred to as black box (black box) them, the one-level trigger of the most close RAM black box is referred to as to the shade logic (shadow logic) of RAM to the combinational logic between RAM black box, as shown in Figure 2, the input of black box (B1, B2 ... Bm) logical value change can not be reflected to initial output terminal, namely not observable, thus cause the shade logical one of input end to test; The output of black box (C1, C2 ... Cn) be uncontrollable, thereby also cause the shade logic 2 of output terminal to test.Therefore,, due to the immeasurability of combinational logic shade, it is not very high causing there is the coverage rate of sweep test of the SOC system of a large amount of RAM.
For what solve combinational logic shade, can not survey problem, a kind of reasonable method is the scan testing methods based on RAM model at present, can effectively improve the coverage rate of sweep test.As shown in Figure 3, the method is by " RAM black box " replaced with to " RAM model ", thereby the output that makes combinational logic 1 can be observed and make the input of combinational logic 2 to be controlled, therefore by this RAM model substitute mode, combinational logic can be surveyed.
Yet, at the above-mentioned scan testing methods based on RAM model, generally include scanning input, parallel measurement, parallel value and scanning several stages of output, for combinational logic 2 is tested, need to make value in RAM in the concurrent working stage in certain value, and conventionally adopt at present the mode of the serial input of test vector, make RAM in certain value, but this mode needs a plurality of test periods to realize, and can lengthen the test duration like this.
Summary of the invention
The embodiment of the present invention provides a kind of scan testing methods and circuit, for having the scan chain of RAM, reduces its test duration.
For achieving the above object, the embodiment of the present invention provides following technical scheme:
A scan testing methods, carries out sweep test to having the scan chain of RAM, comprising:
RAM is carried out to initialization, so that RAM is in predetermined value;
Scan chain, in shift register state, carries out the input of test vector, and keeps RAM predetermined value;
Scan chain is in running order, excitation is loaded on to the primary input terminal of scan chain, catches the test output valve of scan chain;
Scan chain, in shift register state, is tested the output of output valve.
Alternatively, by scan enable signals, control the duty of RAM.
Alternatively, obtaining test output valve and testing between the output of output valve, also comprise: scan chain is in running order, carry out first-in-chain(FIC) output, with first output terminal to scan chain, detect.
Alternatively, sweep test has a plurality of test periods, and the output of the input of the test vector of n test period and the test output valve of n+1 test period is carried out simultaneously.
In addition, the present invention also provides a kind of scan test circuit, comprises the scan chain with RAM, and RAM predetermined value maintenance module, for when carrying out the input of test vector, keeps the predetermined value of RAM.
Alternatively, described RAM predetermined value keep module comprise first with door, described first with the clock signal of an input termination scan chain of door, another input termination scan enable signals, described first with the clock signal of the output termination RAM of door.
Compared with prior art, technique scheme has the following advantages:
The scan testing methods of the embodiment of the present invention, by before testing process starts, RAM is carried out to initialized operation, RAM is worth in reservation, and this predetermined value is remained to scan chain when in running order, make the combinational logic of RAM output terminal in scan chain there is observability, owing to not needing to obtain by a plurality of test periods the predetermined value of RAM output terminal, thereby effectively reduce minimizing test duration test period.
Accompanying drawing explanation
Shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.In whole accompanying drawings, identical Reference numeral is indicated identical part.Deliberately by physical size equal proportion convergent-divergent, do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 be based on scan chain can slowdown monitoring circuit schematic diagram;
Fig. 2 is the schematic diagram with the circuit that can not survey combinational logic shade;
Fig. 3 eliminates the schematic diagram of the scan test circuit that can not survey combinational logic shade by RAM model in prior art;
Fig. 4 is the schematic diagram in prior art with test vector operation in the sweep test of scan chain of RAM;
Fig. 5 is the process flow diagram of scan testing methods provided by the invention;
Fig. 6 is the schematic diagram of scan test circuit provided by the invention;
Fig. 7 is the sweep test sequential chart of scan test circuit provided by the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, so the present invention is not subject to the restriction of following public specific embodiment.
In background technology, mention, in the scan testing methods of the existing scan chain with RAM, have the test duration problem of looking, below by making a concrete analysis of from the flow process of existing scan testing methods, cause the test duration reason place of looking.As shown in Figure 4, in this scan testing methods, the schematic diagram of test vector operation, in sweep test, the operation of each test vector can be divided into scanning input, parallel measurement, parallel value, first-in-chain(FIC) output, scanning output double teacher, wherein first and the last stage be work in series mode, central three can be concurrent working mode.
Conventionally sweep test has a plurality of test periods, test vector of each periodic duty, that is to say in test has a plurality of input vectors to move, in order to improve testing efficiency, scanning input and scanning output are carried out simultaneously, in this two each and every one in stage, scan enable signals continuously effective, make scan chain in shift register state, test vector serial " immigration " is inner to scan chain circuits, the result serial of a upper test period " was shifted out " simultaneously, and survey at scanning output end.During parallel measurement, scan enable signals is invalid, and scan chain is in normal operating conditions, and this stage does not have clock signal, and test vector is own through being moved into chip internal, and measured device is known state in oneself.Enter the parallel value stage, circuit-under-test is still in normal operating conditions, and scan enable signals is still invalid, in this stage, clock signal is activated once, like this, trigger in scan chain captures test response, at next scan period serial-shift, outputs to scanning output end.In first-in-chain(FIC) output stage, scan enable signals is always invalid, there is no clock signal, at scanning output end, carries out one-time detection, and increasing this cycle is in order to prevent the loss of first result of scan chain.
And for the fault of combinational logic that can testing ram output terminal, in concurrent working stage (parallel measurement and parallel value), need to make the output of RAM in controlled definite value state, that is, make RAM in predetermined value.From the workflow of sweep test, can see: at scanning input phase, test vector is moved into serial in scan chain, the output of RAM also can change along with the input of test vector, the output that the serial input by test vector can make RAM in the concurrent working stage in a controlled definite value, but this needs the serial input of many test vectors, just that is to say in order to make RAM need a plurality of test periods to complete in this controlled definite value.And the RAM value by k serial input test vector through establishing can move into and make the value of RAM that less desirable change occur due to the serial of k+1 test vector, in order again to reach this value, needs again a plurality of test periods.By to thering is the analysis of the sweep test workflow of RAM, therefore, can be clear that: this for the input method that makes RAM sentence the serial test vector of certain value be to cause the basic reason that its test duration lengthens.
In order to address the above problem, the present invention proposes a kind of scan testing methods, to thering is the scan chain of RAM, carry out sweep test, this method of testing comprises:
RAM is carried out to initialization, so that RAM is in predetermined value;
Scan chain, in shift register state, carries out the input of test vector, and keeps RAM predetermined value;
Scan chain is in running order, excitation is loaded on to the primary input terminal of scan chain, catches the test output valve of scan chain;
Scan chain, in shift register state, is tested the output of output valve.
Method of testing of the present invention is for the scan testing methods with the scan chain of RAM, that is to say, tested object is scan chain, has RAM in scan chain, and normally, RAM is at the middle part of scan chain, and its input and output are all connected with the circuit in scan chain.
By before testing process starts, RAM is carried out to initialized operation, RAM is worth in reservation, and this predetermined value is remained to scan chain when in running order, make the combinational logic of RAM output terminal in scan chain there is observability, owing to not needing to obtain by a plurality of test periods the predetermined value of RAM output terminal, thereby effectively reduce minimizing test duration test period.
Wherein, to concrete test scan chain, RAM is first carried out to initialized operation, make RAM in predetermined value, even if the output of RAM is in certain value, concrete predetermined value can be carried out emulation according to concrete circuit model and determined, after having determined predetermined value, can this predetermined value be moved into the output terminal of RAM by the primary input terminal of scan chain, thereby make RAM in predetermined value.
State for scan chain, by scan enable signals, come gated sweep chain in shift register state or duty, when scan enable signals is effective, make scan chain in shift register state, when scan enable signals is invalid, make scan chain in running order.
After carrying out initialization, first, enter scanning input phase, in this stage, scan enable signals is effective, and scan chain is in shift register state, carry out the input of test vector, by primary input terminal, test vector is moved into each input end in scan chain serially, now, keeps RAM predetermined value constant.Then, measure and the value stage, can be for what walk abreast, in this stage, scan enable signals is invalid, scan chain is in running order, first excitation is loaded into the primary input terminal of scan chain, tested scan chain is in known state, then, circuit clock signal in scan chain is activated, and scan chain response test also captures the test output valve of scan chain.Then, preferably, scan enable signals is invalid, and scan chain is in running order, carries out first-in-chain(FIC) output, with first output terminal to scan chain, detects, and increasing this step is in order to prevent the loss of first result of scan chain.Then, enter scanning output stage, scan enable signals is effective, scan chain is in shift register state, test the output of output valve, by primary output terminal just the test output valve of each unit in scan chain be moved out to serially primary output terminal, thereby realize the sweep test of whole circuit.Can find out, scan enable signals (ScanEn) is effective in test vector input and test result output stage, and invalid at acquisition phase, therefore, can adopt scan enable signals to control the duty of RAM.
In addition, when sweep test need to be carried out a plurality of test period, in order to improve testing efficiency, test vector input and test result output can be carried out simultaneously, that is to say, the output of the input of the test vector of n test period and the test output valve of n+1 test period is carried out simultaneously.
Above scan testing methods of the present invention is described, the present invention is by before testing process starts, RAM is carried out to initialized operation, RAM is worth in reservation, overcome the problem that causes its test duration lengthening in prior art due to the input method in order to make RAM sentence the serial test vector of certain value, reduce the test duration, improved testing efficiency.
In addition, the present invention also provides a kind of scan test circuit, comprises the scan chain with RAM, and RAM predetermined value maintenance module, for when carrying out test vector input, keeps RAM predetermined value.
In one embodiment, as shown in Figure 6, this scan test circuit comprises the scan chain 600 with RAM, the input end of scan chain comprises primary input terminal SI, for test vector is input to scan chain, scan enable signals ScanEn and clock signal clk, the output terminal of scan chain comprises primary output terminal PO, for by the output of scan chain test result.RAM predetermined value keep module comprise first with door 700, described first with 700 one input termination scan enable signals ScanEn of door, the clock signal of another input termination scan chain, described first with the clock signal of output termination RAM of door, like this, can control by controlling clock the duty of RAM.
As shown in Figure 7, for thering is the sweep test sequential chart of two test periods (the first and second test periods), in the diagram of this embodiment, the effective value of scan enable signals ScanEn is " 1 ", invalid value is " 0 ", before the first test period, RAM is carried out to initialization operation, in first test period, ScanEn is effective, a test vector serial input, and there is no clock CLK input, therefore, RAM does not work, and then kept the predetermined value of RAM, then ScanEn is invalid, after excitation being loaded into the primary input terminal PI of scan chain, send a clock signal, RAM is in running order, capture test output valve, then, scanning input phase second test period, the test output valve serial of first test period is outputed to primary output terminal PO, the clock CLK2 of RAM is connect and is controlled behind the door by the clock CLK of ScanEn and scan chain, make like this RAM not in running order at input and output stage.This circuit can be controlled by controlling clock the duty of RAM, and then reduces the test duration, improves testing efficiency, and in addition, the input clock of RAM does not have saltus step at the input phase of test vector, thereby makes the dynamic power consumption of test circuit have certain reduction yet.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (5)
1. a scan testing methods, carries out sweep test to having the scan chain of RAM, it is characterized in that, is applied to have the sweep circuit that RAM predetermined value keeps module, and RAM predetermined value keeps module for when carrying out the input of test vector, keeps the predetermined value of RAM; Described RAM predetermined value keep module comprise first with door, described first with the clock signal of an input termination scan chain of door, another input termination scan enable signals, described first with the clock signal of the output termination RAM of door; Comprise:
RAM is carried out to initialization, so that RAM is in predetermined value;
Scan chain, in shift register state, carries out the input of test vector, and keeps RAM predetermined value;
Scan chain is in running order, excitation is loaded on to the primary input terminal of scan chain, catches the test output valve of scan chain;
Scan chain, in shift register state, is tested the output of output valve.
2. scan testing methods according to claim 1, is characterized in that, controls the duty of RAM by scan enable signals.
3. scan testing methods according to claim 1, it is characterized in that, obtaining test output valve and testing between the output of output valve, also comprise: scan chain is in running order, carry out first-in-chain(FIC) output, with first output terminal to scan chain, detect.
4. according to the scan testing methods described in any one in claim 1-3, it is characterized in that, sweep test has a plurality of test periods, and the output of the input of the test vector of n test period and the test output valve of n+1 test period is carried out simultaneously.
5. a scan test circuit, is characterized in that, comprises the scan chain with RAM, and
RAM predetermined value keeps module, for when carrying out the input of test vector, keeps the predetermined value of RAM;
Described RAM predetermined value keep module comprise first with door, described first with the clock signal of an input termination scan chain of door, another input termination scan enable signals, described first with the clock signal of the output termination RAM of door.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210249748.6A CN102749574B (en) | 2012-07-18 | 2012-07-18 | Scan test method and scan test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210249748.6A CN102749574B (en) | 2012-07-18 | 2012-07-18 | Scan test method and scan test circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102749574A CN102749574A (en) | 2012-10-24 |
| CN102749574B true CN102749574B (en) | 2014-11-12 |
Family
ID=47029924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210249748.6A Active CN102749574B (en) | 2012-07-18 | 2012-07-18 | Scan test method and scan test circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102749574B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108957301B (en) * | 2017-05-27 | 2021-02-09 | 深圳市中兴微电子技术有限公司 | Test method and device for testable chip and built-in circuit of testable chip |
| CN108153964B (en) * | 2017-12-21 | 2021-11-09 | 北京兆芯电子科技有限公司 | On-chip clock circuit |
| CN110514981B (en) * | 2018-05-22 | 2022-04-12 | 龙芯中科技术股份有限公司 | Clock control method and device of integrated circuit and integrated circuit |
| CN111381148B (en) * | 2018-12-29 | 2023-02-21 | 华润微集成电路(无锡)有限公司 | System and method for realizing chip test |
| CN117607666B (en) * | 2023-12-28 | 2024-04-12 | 芯弦半导体(苏州)有限公司 | Pseudo-random test parameter generation method, aging test method and scan chain circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2520068Y (en) * | 2001-11-12 | 2002-11-06 | 深圳市中兴集成电路设计有限责任公司 | Digital control oscillator based digital phaselooked loop circuit |
| CN101226767A (en) * | 2008-02-18 | 2008-07-23 | 华为技术有限公司 | Read-write control circuit, method and apparatus for two-port RAM |
| CN101297208A (en) * | 2005-10-24 | 2008-10-29 | Nxp股份有限公司 | IC testing methods and apparatus |
| CN101719088A (en) * | 2009-11-23 | 2010-06-02 | 北京龙芯中科技术服务中心有限公司 | Device and method for detecting processor chip on line |
| CN102156259A (en) * | 2011-04-02 | 2011-08-17 | 北京大学深圳研究生院 | Test method of integrated circuit and integrated circuit (IC) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5450455A (en) * | 1993-06-28 | 1995-09-12 | Tandem Computers Incorporated | Method and apparatus for including the states of nonscannable parts in a scan chain |
-
2012
- 2012-07-18 CN CN201210249748.6A patent/CN102749574B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2520068Y (en) * | 2001-11-12 | 2002-11-06 | 深圳市中兴集成电路设计有限责任公司 | Digital control oscillator based digital phaselooked loop circuit |
| CN101297208A (en) * | 2005-10-24 | 2008-10-29 | Nxp股份有限公司 | IC testing methods and apparatus |
| CN101226767A (en) * | 2008-02-18 | 2008-07-23 | 华为技术有限公司 | Read-write control circuit, method and apparatus for two-port RAM |
| CN101719088A (en) * | 2009-11-23 | 2010-06-02 | 北京龙芯中科技术服务中心有限公司 | Device and method for detecting processor chip on line |
| CN102156259A (en) * | 2011-04-02 | 2011-08-17 | 北京大学深圳研究生院 | Test method of integrated circuit and integrated circuit (IC) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102749574A (en) | 2012-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102749574B (en) | Scan test method and scan test circuit | |
| CN103091620B (en) | Optimization method of capturing power consumption in scan test | |
| CN101788644B (en) | Device and method for testing system-on-chip chip with multiple isomorphic IP cores | |
| JP6544772B2 (en) | Integrated circuit capable of generating test mode control signals for scan testing | |
| CN103675641B (en) | Failure of chip localization method, Apparatus and system | |
| US20180203067A1 (en) | Clock gating circuits and scan chain circuits using the same | |
| CN102419415B (en) | TAP (Test Access Port) interface optimization circuit based on boundary scanning circuit | |
| CN102332306A (en) | Embedded static random access memory (SRAM) test structure and test method based on institute of electrical and electronics engineers (IEEE) 1500 | |
| CN101975922A (en) | Low power consumption scanning test circuit and operation method | |
| US6815977B2 (en) | Scan cell systems and methods | |
| CN110007217A (en) | A kind of low-power consumption boundary scanning test method | |
| CN102353893B (en) | Improved scan chain unit and online testing method based on improved scan chain unit and clock control logic | |
| CN104749515A (en) | Low power scan testing method and device based on sequential equal segmentation | |
| US7231565B2 (en) | Method for performing built-in and at-speed test in system-on-chip | |
| US8230283B2 (en) | Method to test hold path faults using functional clocking | |
| CN103023467A (en) | Register resetting method and device based on scanning mode | |
| CN105067993B (en) | A kind of detachable method of testing for on-chip system SOC | |
| CN202120623U (en) | Embedded static random access memory (SRAM) testing structure based on institute of electrical and electronic engineers (IEEE) 1500 | |
| CN107345997B (en) | IP core testing method based on testing shell | |
| CN102156259B (en) | Test method of integrated circuit and integrated circuit (IC) | |
| CN105824351B (en) | The testability clock circuit and its test method of CPU | |
| CN203573309U (en) | Testing structure for embedded system memory | |
| CN102340304B (en) | TAP (test access port) interface optimization circuit | |
| Singh et al. | Area overhead and power analysis of March algorithms for memory BIST | |
| US7334172B2 (en) | Transition fault detection register with extended shift mode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |