CN1027470C - Integrated poly-phase power meter - Google Patents

Abstract

A high accuracy power meter capable of measuring power supplied or consumed in multiple phases of a distribution system is fabricated as an integrated circuit. Voltage and current sensing transducers coupled to the power meter provide input signals having a potential proportional to the voltage and current in the distribution system. A low charge injection pulse width amplitude multiplier using a digitally-synthesized triangular wave is provided for each phase. Each multiplier receives the input signals and provides an output signal having a current proportional to the product of voltage and current in that phase of the distribution system. Charge from the multiplier output currents for all phases is accumulated in a capacitor connected across an autozeroing amplifier, which corrects for its own offset voltage. The amplifier output controls a switch connected between a reference potential and the capacitor. When the switch is closed, a reference current is supplied to the accumulating capacitor to balance the charge from the multiplier for each phase.

Description

Integrated poly-phase power meter

The present invention relates to some devices, be used to measure power that consumes by the user or the power that provides by power plant.More particularly, the present invention relates to an integrated circuit, when it is coupled to one in the distribution system voltage changer and power pack on the time, it will provide the data of relevant electric power in this distribution system.

Watt-hour meter is used for measuring the electric energy by an application-specific unit consumption or supply.In Alternating Current Power Supply or distribution system, one hour watt-hour meter of the watt of electricapparatus uses at large.One hour current in the world use of watt-hour meter of this well-known watt to measure the consumption or the supply of power.Though this kind watt-hour meter is highly reliable, their physical construction has limited the scope of the increase function that they can finish significantly.For example, in one day different time, perhaps under different applied load situations, it is difficult loading different rate of load condensates, goes to control a load or a generating set because be with watt-hour meter itself.In addition, go to finish this many functions if produce this kind mechanical watt-hour meter, that will be very expensive.

Except not having integrated circuit, some perfect electronic instruments that are used to measure power are at U.S. patent documents № .4, and 015,140, № .4 describes on 066960 and № .4,217,546 to some extent.The technology has here been used the product of well-known " scale-Range Amplitude " or the product of " pulse width-pulse height ", and therein, the amplitude of pulse waveform is to be proportional to a variable, and the width of pulse is to be proportional to second variable.In power measurement, if a variable is supply voltage or load voltage, and another variable is to flow to electric current load or that returned by load, and so, the mean value of waveform is proportional to power.Usually, the width of pulse is decided by the comparer of a voltage that receives a triangular waveform and supply or come from loading.

Regrettably, these technology have many shortcomings, have reduced the then degree of accuracy of amount when surveying low-power measurement.Multiplier iunjected charge described in these patents is to circuit downstream, this circuit improperly with it as an effective signal, therefore, in power measurement, cause significant error.Be shown in № .4, the method for 066,960 patent is to rely on a resistance-capacitance network that frequency source is provided.From the value of a high-quality capacitors, it is disadvantageous doing like this.And under the underload situation, the influence of operational amplifier variation is not eliminated.

Because solid-state circuit is cheap for manufacturing cost, volume is little, with height reliability is arranged, there have been many trials to come the design power measuring appliance with integrated circuit, the all functions of a power checker are concentrated on one or more integrated circuit chip can reduce manufacturing cost, and the method that can use a kind of past not accomplish is taken the information data of the consumption or the supply of relevant power.For example, if be used to increase various numerations from the information of power checker, specific numeration takes the different electricity charge to go on record for the electricity consumption in rush hour in the time according to one day arrangement of time so, and this is easily.And, can be sent to immediately at a distance so that be used for from the electric signal of this ammeter and to keep accounts or other purposes.

Use a kind of method that solid components makes power checker in the WO85/00893 of Patent Cooperation Treaty and WO85/00894 number, to describe to some extent.Described here system relies on the width of pulse and the product of height, and it is used a multiplier circuit and finishes, and this circuit produces a direct proportion in the marking current of the product of current measured and voltage.Electric current one frequency converter is accepted this electric current, and provides an output signal to be used to encourage a display.

At the multiplier that is shown on Patent Cooperation Treaty WO85/00893 number two major defects are arranged.Mos field effect transistor (MOSFET) switch arrays that combine with the resistance of current channel series connection inject an additional electric current that is proportional to a triangular wave signal frequency, and this triangular wave signal has been added on the voltage that applies.Inject for reducing this load, the frequency of triangular wave signal is reduced, and therefore, has unfortunately reduced the multiplier frequency span.And, even under low frequency like this, also need a total load injection to minimize tuning.

Be shown in the WO85/00894 patent of Patent Cooperation Treaty, the offset voltage of operational amplifier in electric current-frequency converter is eliminated by open circuit and closed circuit switch, and this switch is added on the capacitor offset voltage.Regrettably, when these switches are in this position, thereby the dialysis from the circuit of electric current-frequency converter is measured less than power.If spike occurs just at this moment, it does not have measured come out yet.And though this technology has been eliminated offset voltage, it causes that load injects metering circuit, therefore, has produced measuring error.

The significant disadvantage of this circuit is the Frequency Synchronization that the frequency in the electrical power distribution system may be eliminated offset voltage with this.Make load inject metering circuit and reduce to minimum, the low-limit frequency that may reach for the elimination variation meets the requirements.Yet when the frequency of offsetting was lowered, the frequency of counteracting became can integrally resolve into multiple frequency, appears in the electrical power distribution system, caused the measurement of electricity consumption or power supply electric energy that the error of a few percent is arranged.Another shortcoming of this circuit is to need external voltage with reference to the source.

Other known proper technologies are described in appended explanation.

An aspect of of the present present invention comprises a system that is used for the metering circuit electric energy, includes: voltage check device, and its consumption is incorporated on the circuit, in order to first signal of voltage on the relevant circuit to be provided;

Current sensing means, it is coupled on the circuit, in order to the secondary signal of electric current on the relevant circuit to be provided;

Multiplier, it connects into and receives first signal and secondary signal, and one the 3rd signal is provided, and an electric current of representing first signal and secondary signal product is arranged in this signal;

Conversion equipment, it connects into and receives the 3rd signal, and provides one the 4th signal, the 4th signal to have a frequency corresponding to first signal and secondary signal product; And

The converting means here comprises the sign bit device, be used for providing a sign bit digital signal to multiplier, when current flowing in the circuit during at first direction this digital signal be in first state, and when the current flowing in the circuit in the opposite direction the time this digital signal be in second state.

Fig. 1 is the synoptic diagram of the embodiment of a poly-phase power meter, illustrates mutually that with of electrical power distribution system it interknits;

One first node, it connects into and can receive a marking current, makes it to be transformed to a signal with a certain frequency corresponding to this marking current;

The electric charge accumulation device, it is connected between first node and second node, so that accumulation is from the electric charge of marking current;

One it receives first node by first switchgear with reference to current source, be used to provide one to this marking current opposite polarity with reference to electric current;

Control device, it is connected between first node and second node, is used to detect the electric charge of accumulation, and provides a control signal to remove to control first switchgear in view of the above, makes with reference to current source and is attached to first node;

Pick-up unit, it is connected to second node, when the polarity of reference current source and marking current when being identical, detects and provide in view of the above a NP signal with it.

The present invention also has further aspect, comprises a system, and it provides an output current corresponding to electric current on circuit and voltage product, and it comprises:

Voltage check device, it is coupled on the circuit, is used to provide first signal corresponding to voltage in the circuit;

Current sensing means, it is coupled on the circuit, is used to provide a secondary signal corresponding to electric current in the circuit;

Signal generation apparatus comprises the digital-analog conversion apparatus, is used for the generating period variable signal;

Comparison means, it is connected into and can receives two signals, be cycle variable signal and second signal one of (in first signal and the secondary signal), and when the cycle variable signal be in selected first signal and secondary signal in one of when having predetermined relationship, it provides the signal of a comparison means output in view of the above; And

Kong Zhi current-source arrangement switchably, it is connected into another signal that can receive among first signal and the secondary signal, and the 3rd signal is provided under the control of comparison means output signal;

The present invention also has other aspects in addition, comprise the system that is used for the metering circuit electric energy, one of them first signal is effectively corresponding to the voltage in the circuit, and a secondary signal is effectively corresponding to the electric current in the circuit (it is stopped separately), and this system comprises:

Comparator device, it is connected into and can receives first signal and receive a variable signal, and this comparator device provides a switching signal according to the relation between predetermined first signal and the variable signal; With

Kong Zhi current-source arrangement switchably, it is connected into and can receives secondary signal and an electric current is provided under the control of switching signal in view of the above.

A further aspect of the present invention, a kind of method that comprises electric energy in the metering circuit, it comprises: the voltage and current in the testing circuit, and provide first signal of a representative voltage and electric current product, the polarity of this electric current to be decided by that circuit confesses electric current or accept electric current;

At the electric charge of first node accumulation from first signal;

Detect the polarity of electric current;

According to the electric charge accumulation, switchably connect a polarity reversing signal to first node, serve as zero to keep the first node mean charge; And

Measure the length that polarity reversing signal is added on first node time, can obtain the tolerance of electric energy in the circuit in view of the above.

A further aspect of the present invention, comprises waveform generator, and it comprises:

Potential generator is in order to provide a plurality of different current potentials;

Switchgear, it connects into the reception input control signal, and responds in view of the above and first current potential from voltage generation circuit is coupled to first node, and second current potential from voltage generation circuit is coupled to second node; With

Adder, it is connected on each first node and second node, in order to an output signal to be provided on output terminal, adds numerical value to show first current potential and second current potential after merging.

The present invention also has other aspects, comprises a waveform generator, and it comprises:

Potential generator is used for providing simultaneously a plurality of different potentials;

Counting assembly, it is connected on the potential generator, is used for variant current potential sequentially is connected to first node and these two nodes of second node;

Add counting apparatus, it is received on each node of first node and second node, in order to weigh the voltage at first node and second node, provides the current potential that is weighted in view of the above; And

Adder, it is connected to and adds on the counting apparatus, is used to merge the voltage of institute's weighting, and an output signal is provided in view of the above.

One aspect of the present invention comprises waveform generator, and it comprises:

The digital-analog conversion device is used to produce the effective voltage of maximum and the effective voltage of minimum; With

Charge-transfer device is used for merging maximum effectively voltage and minimum effectively voltage, so that an output signal to be provided.

The present invention comprises the method for a speciogenesis triangular wave on the other hand, and it comprises:

A plurality of discontinuous current potentials take place;

Select a pair of discontinuous current potential, this comprises maximum effective current potential and minimum effective current potential to current potential;

The current potential of addend maximum is poor with minimum effective current potential, thereby a pair of addend signal is provided;

On an output node, close this weighted signal of And, a discontinuous output signal is provided; And

Repeat above-mentioned steps, go to provide a triangular waveform so that a series of discontinuous output signal to be provided.

The present invention also further comprises an amplifier, and it comprises:

A main amplifier, it has first end that is connected in an input node, second end and one first output terminal that is connected in the first electric charge accumulation device; And

The amplifier of a subordinate, it has first end that is connected in the input node, and second end and one second output terminal that is connected in the first electric charge accumulation device, this end switchably are connected on one of them of the first and second electric charge accumulation devices.

The present invention also comprises an amplifier, and it comprises:

A source;

A control transistor, it has first electrode on the source of being coupled to;

The electric charge accumulation device, it is coupling between the control utmost point of reference voltage and control triode;

One first load triode, it is connected to one second electrode of control triode, and has a control electrode, and this electrode is coupled on second electrode of load triode;

One second load triode, it has first electrode that is connected on the reference voltage, and has the control electrode that a control that is connected to first triode is extremely gone up;

A pair of difference triode, it comprises one the 4th triode, the 4th triode has first electrode that is coupled in first load, also has the control electrode that is coupled to an input end, and one the 5th triode, it has one and is connected to first electrode that second of the 3rd triode is extremely gone up, and also has one and is coupled to second with reference to the control electrode on the current potential;

A current source, it receives second utmost point of the 4th triode and second utmost point of the 5th triode, so that electric current is provided herein; And

An output terminal, it is connected to second of the 3rd triode and extremely goes up.

Fig. 1 is the synoptic diagram of the embodiment of a poly-phase power meter, illustrates mutually that with of electrical power distribution system it interknits;

Fig. 2 is a block scheme, and the whole pulse width range amplifier circuit of this power checker is described;

Fig. 3 is a time diagram, and the work that is shown in Fig. 2 circuit is described;

Fig. 4 is the circuit theory diagrams of the triangular-wave generator 35 of Fig. 2;

Fig. 5 is a time diagram, the work of the source shape generator of key diagram 4;

Fig. 6 is the schematic diagram of the voltage comparator circuit 30 of Fig. 2;

Fig. 7 is a time diagram, the work of the circuit of key diagram 6;

Fig. 8 is the circuit theory diagrams that are shown in the switch 40 of Fig. 2;

Fig. 9 is the block scheme that is connected to three current-voltage amplifiers of current-frequency converter;

Figure 10 is a time diagram, the work of key diagram 9;

Figure 11 is the block scheme that is applied to the automatic zero loop of the operational amplifier 150 among Fig. 9;

Figure 12 is a block scheme, and the autobias technology that is applied among Fig. 9 is described;

Figure 13 is a time diagram, and the work of Figure 12 is described;

Figure 14 is the circuit theory diagrams of the operational amplifier 150 among Fig. 9; And

Figure 15 is the circuit theory diagrams of reference voltage line.

Fig. 1 is a block scheme, and connecting each other of an electrical power distribution system 5 and a power checker 10 is described.Power checker 10 is measured and is consumed by specific application units 15 or the electric energy of supply (or consume and supply both).Application units generally are electricity consumption user such as dwelling house or enterprise, or give supply of electrical energy user's supplier such as the generating plant.User or generating plant shown in application units 15 are connected in the electrical power distribution system with single-phase, two-phase or three.In Fig. 1, a uniline only is shown, it is made up of the lead of a pair of interchange, sets up voltage U (t) between them.More than single-phase, all phases all similarly are connected with measuring appliance 10 in an embodiment of the present invention.In a further embodiment, each is sampled respectively mutually, and adds to measuring appliance 10 by multiplexer channel.

Determine that electric power is that the unit of being employed 15 consumes or produces, need to determine by voltage U (t) and current generated I(t) product, the power that n consumes mutually or produces is:

P（t）＝∑Ui（t）·Ii（t） （1）

Power checker 10 comes the relevant data of rated output by measuring electric current I (t) with voltage U (t).Voltage in the place of measuring in the detection distribution system is to use transformer 20(voltage divider or mutual inductance transducer.Equally, detect from application units 15 flow out or the electric current that flows to is to use current transformer 24(mutual inductor) or other known devices.

Transformer or voltage divider 20 are carried a voltage V _v(t) to power checker 10, its characteristic is with the voltage constant K of transformer 20 _vExpression.Equally, current transformer 24 carries a direct proportion in the voltage of tested phase current.The characteristic of current transformer output is with the current transformer constant K _cWith shunt resistance R _ShExpression.Provide current data to have zero mean value with hypothesis current transformer 24 and come design power measuring appliance 10.(this is not extreme restriction, because nearly all current transformer and mutual inductor are not always the case).Transformer provides a voltage data V _v(t), its direct proportion voltage poor between the tested phase and the neutral line, perhaps tested phase and other mutually between voltage poor, shown in following equation 2.Current transformer 24 provides the voltage data V of direct proportion electric current in mutually simultaneously _v(t), shown in following equation 3.

V _v（t）＝K _v·U（t） （2）

V _c（t）＝K _c·R _sh·I（t） （3）

Then, power checker 10 makes V _c(t) and V _v(r) multiply each other effectively, obtain an electric signal V _p(t), its direct proportion is in this power.Its relational expression is shown in following equation (4).

V _p（t）＝K _v·K _c·R _sh·U（t）·I（t） （4）

So this power data can be multiplied by a constant K p and be transformed to frequency data Fp(t)

F _p（t）＝K _pV _p（t） （5）

From the whole time integral frequency data of O to T, so obtain mean value F _mFor:

F _m＝1/T∫ ^T _OF _p（t）dt （6）

Simultaneously, its umber of pulse N is:

N＝F _m·T （7）

Therefore, in the whole cycle of the T time of being calculated in the output of power checker, the number of pulse is that direct proportion is in the electric energy that consumes or supply.

Fig. 2 is the block scheme of power checker 10.As shown in Figure 2, power checker receives voltage data V on lead 27 _v(t) received current data V and on lead 29 _c(t).This system comprises a voltage comparator 30, is used for a voltage data on the comparison lead 27 and a signal data on lead 32 that produces from the triangular wave signal generator.Though theoretically, the voltage sensor depressor can be switched mutually with the current transformer on being coupled to voltage comparator, consider from its dynamic range and the characteristic of triangular wave, still encourage in lead 27 relatively good with voltage data.And it is more favourable encouraging in lead 29 with current transformer, because resistance-switch-resistance system (R ₂, 40, R ₁) on the thirty carry of the whole scope of pumping signal at least, be highly linear.This makes and obtain correct measurement in the very great dynamic range of electric current.Even, also be enough to de-energisation frequency changer 50 for the little electric current that comes from current transformer output.And, output signal V _c(t) be single-ended, tangible difference arranged with the both-end output or the output of bridge shape of the current transformer of above-mentioned United States Patent (USP).

Output signal from voltage comparator 30 comes out combines with a sign bit signal NP, by an inconsistent OR door 45, removes to control a complementary metal oxide semiconductor (CMOS) cmos switch 40.These symbol figure place indication application units 15 are power consumption or generating.Switch 40 is connected on resistance R ₂And R ₁Between.When switch 40 is closure, an electric current I _p(t) arrive current-frequency converter 50 by this switch, this transducer 50 makes this signal provide power data.This current-frequency converter 50 counters of general excitation or at a display of measuring appliance 10 appearances, yet, these data can also be used for other purposes, such as the power consumption or the production of application unit 15 are controlled, the electric power that is delivered to the distant place are calculated etc.

With reference to the time diagram of figure 3, can be more prone to understand the whole system operation situation that is shown in Fig. 2.For convenience of explanation, in the whole cycle of in Fig. 3, being narrated, putative signal V _v(t) and V _c(t) be constant.(However, it should be understood that the signal V of alternating current in distribution system 5 _v(t) and V _c(t) in the extremely short time, be constant only).

Triangular wave signal generator 35 produces a triangular wave signal, and it has a voltage V who changes apace _Tw(t), V _Tw(t) vibrate in-V _RefAnd V _RefBetween.This triangular wave signal has a frequency, and this frequency is significantly greater than the frequency of signals in the distribution system 5.For example, the frequency that has of general triangular wave signal is greater than about 20 times of desired highest frequency in the distribution system.And, as mentioned above because the interference of local oscillator, the triangular wave frequency can not with the frequency phase lock of measured signal.Therefore, for the distribution system of 60 cycles, can be with 1000 hertz triangular wave frequency.In addition, the maximum voltage V of triangular wave _RefBe provided with serious offense from the maximum voltage V of the transformer 20 of desired measurement _v(t).Though only described a triangular wave here, other equivalent oscillator signals (for example zigzag wave) also are adaptable.

As shown in Figure 2, triangular wave is added to and delivers to comparer 30 on the lead 32.Comparer 30 is this voltage with from the signal voltage V of transformer or voltage divider 20 _c(t) compare, and provide an output signal to indicate these relevant current potentials in view of the above.This output signal simultaneously, is used for showing application units or consumed power or another input end of sign bit NP signal excitation (OR door 45) of production electric energy by an input end of an XOR gate 45 of lead 44 excitations.Sign bit NP signal rises in a circuit of current-frequency converter 50 inside.The if symbol position is zero, so, and as input voltage V _v(t) greater than triangular wave signal voltage V _Tw(t), switch 40 closures, and voltage V _c(t) cause that an electric current passes through R ₁And R ₂Two resistance.As voltage V _v(t) less than triangular wave signal voltage V _Tw(t), so, switch 40 open circuits do not have electric current I _p(t) flow to current-frequency converter 50.Comparer 30 produces a series of pulses with interacting of switch 40, and shown in Fig. 3 lower part label 47, this pulse has direct proportion in V _o(t) amplitude and direct proportion are in V _v(t) perdurability.The hachure area of Fig. 3 is according to electric current I _p(t) mean value I _p

In Fig. 3, time T ₁Corresponding to V _Tw(t) surpass V _v(t) time.Time t ₂Corresponding to the time that keeps, in the meantime in, triangular wave is at V _v(t) below the horizontal line, and time t _xBe at t ₁Till afterwards when triangular waveform becomes negative value.Therefore, at t ₁+ t ₂The fundamental relation of electric current and voltage product is during this time:

t _x＝（t ₂-t ₁）/4 （8）

At t ₁+ t ₂During this time, suppose that voltage is constant and equals spike amplitude K _vV _m, draw:

K _V·V _m=V _ref[ (t ₂-t ₁)/(t ₂+t ₁) ]（9）

Therefore,

(t ₂)/(t ₁+t ₂) = 1/2 [1+ (K _V·V _m)/(V _ref) ]（10）

(t ₁)/(t ₁+t ₂) = 1/2 [1- (K _V·V _m)/(V _ref) ]（11）

If R _sBe the resistance of switch 40, with R ₁And R ₂Series connection, R=R _s+ R ₁+ R ₂, and work as t ₂Switch is closed during this time, so, supposes that electric current I p flows into virtual earth, then relevant with power electric current I _pMean value be:

I _P= 1/(R) · 1/(t ₁+t ₂) ${\&Integral;}_{t_1}^{{\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="881039403\_DRIMG2.png,881039403\_DRIMG4.png"\; state="\{\{state\}\}">t</figure-callout>}}_1\mathrm{+\; t}{}_2}$ V _c(t)dt (12)

If at t ₁Switch is closed during this time, then electric current I _pMean value be:

I _P= 1/(R) · 1/(t ₁+t ₂) ${\&Integral;}_o^{t_1}$ V _c(t)dt (13)

Suppose at whole t ₁+ t ₂Current constant and equal amplitude I during this time _mPeak value, equation 10 and 12 is combined, draw:

R· I _P= (R _sh·K·I _m)/2 + (K _V·V _m·R _sh·R _c·I _m)/(2V _ref) （14）

Equation 11 and 13 is combined, draws,

R· I _P= (R _sh·K _c·I _m)/2 - (K _V·V _m·R _sh·R _c·I _m)/(2V _ref) （15）

For a plurality of sine wave signals, between whole time T long-term, T significantly is longer than (t ₁+ t ₂), its average current ξ is:

ξ＝ 1/(T) ${\&Integral;}_O^T$ I _pdt （16）

ξ＝±R _sh·K _v·K _c· (V _m·I _m·cosφ)/2 · 1/(2V _ref) · 1/(R) （17）

Here V _mAnd I _mBe to represent the amplitude kurtosis, and φ is the phase shift of electric current with respect to voltage, equation 14 and 15 first influence are zero, because the average voltage on current transformer secondary side branch road is zero.

Therefore, for positive, electric current I when sign bit is O _pMean value will on the occasion of, and when sign bit is 1 electric current I _pMean value will be negative value.For negative power, electric current I when sign bit is O _pMean value will be negative value, and when sign bit is 1 electric current I _pMean value will on the occasion of.

Triangular wave signal generator 35 shown in the block scheme in Fig. 2 is shown in further detail in Fig. 4.Fig. 5 is the time diagram that is used for the signal of Fig. 4.In Fig. 4, this generator comprises the D-A converter and the charge transfer circuit that is shown in the right side of figure roughly that are shown in the left side of figure roughly.This digital-to-analog converter is at bi-directional counter signal Q ₁, Q1B, Q ₂... Q ₆, Q6B control under a pair of voltage is provided, optionally demarcate and be MSV and LSV, they cause electric charge to accumulate in the capacitor C of different sizes ₁To C ₃, these electric capacity are recharged then and by means of the charge-conduction circuit these combination of charge are got up to produce the signal V of triangular wave _Tw(t).

This transducer partly comprises a string cascade N type metal oxide semiconductor MOS52-79, and they are connected on a string ladder shaped resistance 80-86.Form these resistance with IC regime, the resistance of each resistance 87-86 can be done almost completely identically, and if desired, the technology that can know with many crowds of institute of laser or other are processed.With a voltage Vref(preferably-3.6 volt) be added on the end of uppermost resistance 80, bottom one end of the resistance 86 in bottom of this crosstalk resistance ground connection then.

Two pairs of transistor parallels jump on each resistance (two ends), a pair of on the right, maximum effective voltage side, a pair of on the left side, minimum effective voltage side, for example, transistor 68 and 69 parallel connections are connected across on the resistance 82, and transistor 60 and 61 also is like this.Like this, 61,62,69 and 70 parallel connections are connected across on the resistance 83.Transistor staggered in given ranks all has grid, and they are received on the common input signal source.Therefore, transistor 58,60,62 and 64 is connected, at a control signal Q ₁Down work of control.All the other transistors in these ranks, promptly transistor 59,61,63 and 65 is connected, with control signal Q ₁Complementary control signal Q ₁The control of B is work down.Each transistor to the penetralia ranks is connected on another transistor successively equally.For example, Bing Lian transistor 60 and 61 series connection are received on the transistor 55, by Q ₂B control; Transistor 62 in parallel and 63 series connection are received on the transistor 56, are subjected to Q ₂Control.This column-row arrangement of transistor is continuously to a pair of outlet line, so that maximum and effective voltage minimum to be provided.

Maximum effective voltage is name like this, because capacitor C ₁Has capacitor C ₃The capacity of octuple, therefore, output signal V on lead MSV _Tu(t) voltage is more effective than the voltage on lead LSV.Capacitor C ₂Capacity equal capacitor C ₁And C ₃The capacity sum.The outlet line of MSV and LSV is received charge transfer circuit 90 successively, from producing triangular wave output signal Wtw(t here).Shown in Figure 2, this triangular wave signal is couple to comparer 30 through lead 32 as previously.

Electric charge transmits network and comprises three capacitor C ₁, C ₂And C ₃, they are wire-wrapped in around the operational amplifier 94.This network transmits the weighting electric charge to capacitor C ₁And C ₃ Clock signal φ 1, φ 2, φ 3 and the several switches of φ 4 controls, the switch of mark is sent to capacitor C to electric charge from two output leads like this ₁And C ₃, arrive C then ₂These switches of being controlled by clock signal are to be made of complementary metal oxide semiconductor (CMOS) CMOS, and one of them P type raceway groove and a N type raceway groove are connected in parallel.

The circuit that is shown in Fig. 4 provides and has the triangular wave of consistent spike to the highly linear of the amplitude of spike.For example, use 6 bit changers of putting in marks, the good linearity superpotential linearity 0.1% of the product of electric current and voltage.For ease of testing Manufactured transducer and making the uniform quality of a large amount of integrated circuit, used number-Mo parallel operation and replaced mimic channel.The pulse signal generator of clock 93 of excitation triangular-wave generator is combined on this integrated circuit.The spectral interference of this clock guarantees that the triangular wave frequency is not drawn on the frequency of electrical power distribution system.

The function of bi-directional counter is to select an independent tap on the ladder of resistance, and therefore there is a current potential in eight different potentials to utilize, be used for providing for example effective voltage output of a maximum from transducer, a same independent tap and the correspondent voltage selected is to provide for example minimum effective voltage output of transducer.Maximum and effective voltage minimum are by capacitor C ₁And C ₃Relative capacity come weighting.This circuit is design like this; Be C ₁/ C ₂=8/9, and C ₃/ C ₄=1/9.In integrated circuit structure, be used to form these capacitors with photoetching technique, their ratio can obtain height accurately.In case voltage occurs on the output lead, the switch of clock signal control transmit at once since the electric charge that these voltages produce to capacitor C ₁And C ₃, then successively from each capacitor C ₁And C ₃Enter capacitor C ₂Because capacitor C ₁Capacity be capacitor C ₃Octuple, the voltage on the MSU lead since it be to click from tapping point to a tap to connect, so at output signal V _TwEight big levels of last regulation.Each level in these big levels, the effect of current potential is less on lead LSV, because C ₃Capacity less, in each big level, will limit eight less grade.

Concerning operational amplifier 94, capacitor C ₂Play the feedback control loop effect.After the transient state process process, the output current of amplifier 94 will be zero.Therefore, all electric charges will be stored in capacitor C ₂, and the voltage of exporting at amplifier will be a linear combination maximum and effective voltage minimum.

Fig. 5 illustrates and is added to or from the relation between the signal of the circuit of Fig. 4.Fig. 5 shows signal Q ₁To Q ₆, but their complementary signal is not shown.Illustrate that with an example situation of these signal controlling transducer signal is used in the easiest understanding.Please note the moment of ordering, Q at A ₂Be high, and the signal Q of other opposition ₁, Q ₃-Q ₆Be low.This family curve makes the transistor 53,56 and the 63(that are positioned at minimum effective one side also have other) conducting.And be positioned at maximum effectively on one side transistor 73,77 and 79 conductings.(also have other.Therefore, MSV ground connection, and the branch node between LSV ground connection triode 84 and 85.So MSV is an earth potential, and LSV is lower than earth potential two utmost point (V _RefBe negative).Therefore, this V _TwCurrent potential be that MSV and LSV are together with earlier stages current potential V _TwThe amount of weighted combination.As shown in Figure 5, be t in the time _ChsThe phase place of Shi Biangeng clock signal φ 3 and φ 4 is as waveform V _TwTo be converted when reaching zero, to provide an amplitude at positive V _RefWith negative V _RefBetween the swing triangular wave.

Have clock (control signal) φ 3 for one and be equal to the direct transform that φ 1 and clock (control signal) φ 4 are equal to φ 2, V _TwBe negative value, and load transition is as follows:

Q _C1（n）＝C1·（MSV-V _tw（n））

Q _C3（n）＝C ₃·（LSV-V _tw（n）） （18）

Q _C2（n）＝C ₂·（V _tw（n）-V ₀）

Here Q _C(n) be to be charged to an electric charge on the capacitor when the n cycle, Cn is the capacity of capacitor Cn, V ₀It is the bias voltage of operational amplifier.

When the n+1 cycle begins, a charge charging is arranged immediately to capacitor C ₂So, at capacitor C ₁, C ₂And C ₃Electric charge be:

Q _C1（n+1）＝V ₀C ₁

Q _C2（n+1）＝-V ₀C ₃（19）

Q _C3（n+1）＝Q _C2（n）+△Q

△Q＝C ₃（LSV-V _tw（n）+V ₀C ₃+C ₁（MSV-V _tw（n））+V ₀C ₁

If C ₁+ C ₃=C ₂

So

Vtw(n+1)= (Q _c2(n+1))/(C ₂) +V ₀

Vtw(n+1)=LSV (C ₃)/(C ₂) +MSV (C ₁)/(C ₂) +V ₀（20）

Equation 20 illustrates the influence that the n+1 step is not gone on foot by n.

Have clock (control signal) φ 3 for one and be equal to φ 2, and clock (control signal) φ 4 is equal to the negative conversion of φ 1, V _TwBe on the occasion of, and the calculating of charge conversion is identical, shown in following equation:

△Q＝C ₃（V ₀-LSV）C ₃V _tw（n）+C1（V ₀-MSV）-C1·V _tw（n） （23）

Vtw(N+1)=LSV (C ₃)/(C ₂) -MSV (C ₁)/(C ₂) +V ₀（24）

Be transferred to capacitor C by means of the control electric charge ₂, use phase 3 and φ 4 can produce an output conversion or not conversion.Because offset voltage V ₀Make positive phase and minus phase both phase shifts of triangular wave, the offset voltage of amplifier does not influence the degree of accuracy of multiplier.Simultaneously, transducer is made with same resistor network and same electric capacity, and the negative value that obtains from transducer and on the occasion of quite makes the linear zero passage of output signal.Therefore, though every grade of waveform relates to reference voltage and capacitor C ₁, C ₂And C ₃Capacity, but the quality of these grades and operational amplifier 94 is irrelevant.Because this reason, and because the stability of clock in any given minority cycle period, last triangular wave is a highly linear, capacitor C ₁And C ₃To C ₂Particular ratio be to be related to the figure place n that is used in digital-to-analog converter, its special relationship is:

(C ₃)/(C ₂)=1/ (2 ^N/2+ 1) and (C ₁)/(C ₂)=(2 ^N/2)/(2 ^N/2+ 1) (25)

Triangular wave signal generator 35 is sensitive to the stability of reference voltage source.If this voltage source drift then produces error.Specifically, the spike of triangular wave to the stable dependence of spike the stable of a voltage of putting in marks.In order to obtain desirable stability, a voltage source of putting in marks produces according to mode described in conjunction with Figure 15.A voltage source of putting in marks is made with same integrated circuit, here will describe as another kind of circuit.

Fig. 5 illustrates last triangular wave signal V _Tw(t).For one 7 bit changer (6 positions of putting in marks), this waveform signal has 252 grades of per quart cycles and has 63 grades.Triangular wave spike to the distance of spike is two times an of voltage of putting in marks.

Fig. 6 is the detailed schematic diagram that is shown in voltage comparator in Fig. 2 square frame 30 and produces the signalling channel of switch order signal thereafter, and Fig. 7 is the sequential chart of signal in the key diagram 6.Circuit is with the output voltage V of voltage changer 20 among Fig. 6 _v(t) with triangular wave V _Tw(t) compare, and send a switch order signal according to comparative result and remove operating switch 40.

In Fig. 6, from the signal V of voltage changer 20 outputs _v(t) be added to node 100, simultaneously triangular signal V _Tw(t) be added to node 102. Node 100 and 102 can by the switch transition of clock signal φ 1 and φ 2 controls be connected to capacitor C ₄, what this clock signal and triangular-wave generator were used is identical clock signal, so this comparer is synchronous with triangular-wave generator.Capacitor C ₄Another the level be connected with voltage comparator 30, another node of comparer 30 then under the control of clock signal φ 21 with capacitor C ₄Couple.

Voltage comparator must work in the peak-peak all-wave scope of this triangular signal, this is because do not have wide input common mode voltage with the normal voltage comparer of CMOS technology foundation, and comparer 30 is closely just to be energized during current potential and to produce controlled output at its input voltage.

Why the additional clock signal psi 21 and the φ 11 that are shown in Fig. 6 and 7 so demarcate, it is relativeness according to itself and clock signal φ 1 and φ 2, specifically, φ 21 be in φ 2 ON time a bit of time of conducting (high position), and φ 11 be in φ 1 ON time a bit of time of conducting.When this signal source is connected, each switch closure of controlling by these signals.

The output terminal of comparer 30 is received the XOR(XOR) a door input end of 45, sign bit signal NP is provided to its another input end simultaneously, door 45 is an input end of a D flip-flop 105 of de-energisation again, another input end of trigger 105 is connected to acknowledge(ment) signal φ 11 simultaneously, so that trigger whereby and synchronously.The output of trigger 105 provides switch order signal M φ and its benefit so that excitation cmos switch 40.Giving fixes time because the clock signal φ 1 of excitation D flip-flop 105 always lags follows the tracks of φ 1, so introduce an average delay ts in multiplier.

As shown in Figure 7, make V owing to connecting φ 2 and φ 21 _v(t) by capacitor C ₄, slightly a moment later, φ 1 allows signal V _Tw(t) be added to capacitor C ₄So, at capacitor C ₄On resultant voltage V _iFor

V _i＝V _v（t ₁）-V _tw（t ₂） （26）

Therefore, the output of comparer promptly goes out promptly to be decided by V _TwWith the greater among the V.If V _vLess than zero (the triangular wave amplitude is greater than this input voltage) and this negative power position NP is zero, and then switch order will be zero.In contrast, if V _iGreater than zero, NP is zero simultaneously, and then switch order is 1.

Fig. 8 is the detailed schematic diagram of cmos switch 40 in the square frame of preceding diagrammatic sketch 2.This switch comprises the MOS device 110 and 120 of a pair of complementation, and they connect into switch order signal and the complement signal thereof of reception from the D flip-flop output of Fig. 6.This N and P-channel device 110,120 are connected in parallel and are fed to electric current-frequency converter 50(from power pack 24 and see Fig. 2 with control) electromotive force.This cmos device is designed so that on geometric figure that the electricity of equal value of switch is led and is symmetrical in zero point.This complementary device makes this switch obtain highly linear, promptly has and can ignore the electromotive force V that applies _c(t) equalization characteristic of polarity.This cmos switch 40 does not provide output signal when cut-offfing, and provides when switch closure and add electromotive force V _c(t) Xiang Guan electric current I _p(t).

Shown resistance R among Fig. 8 ₁And R ₂, also shown the grid/source that parasitizes that connects mutually with each N and P-channel device and the electric capacity between grid/leakage.Three main parasitic current sources have reduced to minimum in described switch 40, these electric currents are, owing to be added to electric current in the stray capacitance that the clock switch command signal of each grid of transistor produced, change the electric current that is produced at the electric capacity of grid one raceway groove, and the electric current that produces by reverse bias two utmost points of P and N channel transistor.

With this polysilicon resistance R ₁And R ₂The resistance of equal value of this switch of series connection is designed at input voltage V _c(t) in whole dynamic ranges is steady state value.When this P and the transistorized geometrical factor W/L of N-channel MOS met following equation, electric charge was injected to minimum and resistance of equal value and turns to the best around the linearity of zero line, and W is a width in this formula, L is a length, μ is a mobility, and Cox is the electric capacity of per unit area medium

（ (W)/(L) ）p·μp·Cox＝（ (W)/(L) ）n·μn·Cox （27）

In most preferred embodiment, R ₁And R ₂Be respectively about 5000 ohm, and the resistance in series of switch is about 100 ohm.Because injecting, the electric charge that capacitive coupling caused between the output of the pulse signal of energizing switch 40 and this switch has been eliminated, and because in resistance R ₁And R ₂Between even distributed resistance and make the injection of electric current reduce to minimum.Lacking the designed switch 40 of these considerations, the error that is produced in power measurement is considerablely bigger than allowable value.

Flow through the electric current I of this switch _p(t) with this distribution system in electrical that consume or that produce.How current conversion is become the power of intending mensuration according to institute to change the signal of frequency, will narrate below.

An aforesaid electric current and voltage multiplier circuit is used for every phase of distribution system, and schematic diagram shown in Figure 9 is the wiring that current conversion with one or more multipliers is the equalizing charge converter 50 used of frequency signal.For system shown in Figure 9 is described, suppose that a three-phase system has adopted three multipliers; But clearly, what wanting to measure all is possible mutually.Figure 10 is the sequential chart that is used for key drawing 9 signals.Converter 50 among Fig. 9 can find out it is the signal of accepting to come from three-phase, by the voltage V of every phase current transducer output in the three-phase _c(t) be fed to node 141,142 and 143, switch order signal M φ 1, M φ 2 and M φ 3 are fed to 144,145 and 146 ends, as previously mentioned, each switch order signal removes to control each corresponding switch 40 mutually with negative power signal NP by XOR gate 45, from the signal of each switch output in node NIN addition.There is one to pass through resistance R _rBe couple to reference voltage-V _RefThe 4th switch 177 be connected in parallel with this threephase switch.To explain that below the electric current of this reference switches 177 is as the euqalizing current of each phase switch.

A switch 177 accepting each switch 40 of each phase current and be used for reference voltage is entirely according to the geometric proportion assembling and mated, utilization closely is adjacent to be assemblied in all cmos switches and attached resistance on this integrated circuit modules, temperature effect is compensated, because the influence of the resistance R r that temperature pair and switch 177 link will be with identical to other each resistance.In addition, because long-time temperature instability will change in the same way to the skew that all resistance cause, cancel each other again so influence.

Each phase current is imported, and resistance is R ₁+ R ₂+ R _S, to this reference voltage then resistance be that Rr and switch resistance are Rts, here:

(Rr)/(R ₁+R ₂) = (Rrs)/(Rs) （28）

Used other switch of resistance R r then to use a pair of resistance to 177 on switch, this just can make all switches work in to be about zero potential and make CMOS bulk effect (bodyeffect) to reduce to minimum.It is proportional with load that the electric charge of switch 177 injects influence, and under the full load state, electric charge injects about 5 * 10 ^-9Ampere is far below resetting current Vref/(Rr+Rxs) about 200 * 10 ^-6Ampere.

Always add node NIN and be connected to the ad hoc negative input end that operational amplifier 150 is arranged, and its positive input terminal ground connection, capacitor C ₅Be connected across this amplifier 150 two ends, switch 152 also so connects, and the operation of this switch 152 is subjected to the control of a reseting capacitor signal RCAP.The output terminal INT of amplifier 150 receives the input end of voltage comparator 160, this comparer 160 is controlled a D flip-flop 162 subsequently, and another input end of trigger 162 connects into acceptance from come highly stable of a crystal-controlled oscillator and highly accurate clock signal R1.The output terminal INT of this operational amplifier 150 also receives on the input end of XOR gate 170 by level detector 164 and 165.The output of this XOR gate and signal F2(also are by this crystal-controlled oscillator 51) control another D flip-flop 175 jointly and send out negative power sign bit signal NP.

Circuit working is as follows among Fig. 9.The voltage that reacts each measurement phase current is sent to and always adds node NIN, here by capacitor C ₅(switch 152 is an open-circuit condition) integration.Because electric charge is at capacitor C ₅Last savings is so the output signal of operational amplifier 150 descends.Dropping to when being about zero volt, comparer 160 promptly when next clock signal F1 arrives excitation trigger 162 provide signal IMPRC to remove to connect switch 177.Switch 177 makes reference voltage-V _RefBe switched to and always add node NIN, the negative current of a correction is provided thus, this current balance type from each positive current of coming mutually to holding container C ₅Effect, so, capacitor C ₅On electric charge be removed.Because the current potential on node INT rises, so comparer 160 loses excitation, so that reference voltage is cut off.Then, the electric current that comes from each phase switch causes electric charge to put aside again at capacitor C ₅Go up to repeat this process.The pulse that includes in the IMPRC signal among Figure 10 is how when the current potential that always adds node NIN reaches suitable level said process to be repeated with demonstration.

The satisfactory action of said process be from each measured current symbol of coming mutually must and from reference voltage-V _RefJust set up when the backflow symbol that comes is identical.In this case, the electric charge that is fed to node NIN is not offseted, so at capacitor C ₅On electric charge cumulative, last, the output voltage of operational amplifier 150 will reach Vtn(and see Figure 10), be about 3 volts.This threshold voltage causes XOR gate 170 to encourage trigger 175 when next clock pulse F2 arrives, and makes the sign modification of negative power position NP after being detected by level detector 164,165.Meanwhile, the logical circuit (not shown) makes signal RCAP with capacitor C in turn in addition ₅Restore so that restart this program next time.Because the symbol of position NP is the door on 45 that feeds back to each switch 40 under the control three-phase, thus the work of comparer 160 will along with the polarity of this reference current instead in restarting from the polarity of each multiplier output current.

Through the given time, the amount of time signal IMPRC can play the effect of measuring the electric energy that consumes or confess.This cycle of working can utilize crystal-controlled clock to provide the signal F1 utmost point to measure exactly, if the time cycle is T, and umber of pulse is N, then:

T· ξ= 1/(F ₁) · (V _ref)/((Rr+Rrs)) ·N（29）

Use R _Ref=Rr+Rrs=K(R ₁+ R ₂+ R _S)=KR solves N

Equation 17 substitutions are got

N= (T·F ₁)/(V _ref) · (R _sh·K _V·V _m·K _c·I _m·cosφ)/(4·V _ref) · (R _ref)/(R) （31）

Make each constant of K=and F ₁=1/ (t _Ref) product,

N=T· (K(V _m·I _m·comφ)/(t _ref·V _ref ²) （32）

So this frequency is

(N)/(T) = (K·V _m·I _m·cosφ)/(t _ref·V _ref ²) （33）

Proportional by the pulsation rate that the signal IMPRC that is shown in circuit output among Fig. 9 has with the sum of products of every input voltage that comes mutually and electric current, therefore, to n mutually promptly

F= 1/(t _ref·V ² _rtf) $\underset{n}{\overset{}{\mathrm{\&Sigma;}}}$ K _i·V _mi·I _mi·cosφ（34）

I is the phase label in the formula.This output signal can a simplex winding of direct-drive stepping motor, show the power of electrical equipment consumption in order to realize mechanical digital ground or simulation ground.For the purpose of the power meter on the spot that the conventional simulation that is suitable for using such as the U.S. shows, this output pulse will encourage a simulation machinery showing the power of consumption on a series of scales, or encourage a digital revolution record sheet.If this output pulse follows electronic console to use, then no longer use the output of stepping motor, and this power symbol NP indication allows the tested consumption or the power of supply to separate the application records device, maybe the power that will consume and supply with is used altogether.In addition, this output signal can be applicable to other different consumer, and for example being applied to provides feedback information to be adjusted to the duty of expectation to electricity consumption or power-supply unit.

Figure 11 is for explaining the block scheme of the effect of operational amplifier 150 in the square frame that is shown in Fig. 9.In the block scheme of Figure 11, this operational amplifier 150 includes an input node Vin, and an intrinsic offset voltage Voffset and an output node are supplied with output voltage V out from this node.This feedback control loop comprises having gain G ₃The feedback, of main operational amplifier 183 have gain G ₁ Automatic biasing amplifier 181 and one have gain G ₂Consumption close amplifier 182.If this automatic biasing and coupling amplifier have the level of the opposed polarity that causes for the bias voltage value of not matching △ V, then work as output voltage V _OutWhen being zero, at V _InOn input voltage be this residual voltage V _Res:

△V·G ₂+V _in·G ₁·G ₂+（V _in+V _offset）·G ₃＝V _out（35）

Because of V _Out=0, V _In=V _Res

V _res= (V _offset·G ₃+△V·G ₂)/(G ₁·G ₂+G ₃) （36）

If G ₁And G ₂＞＞G ₃, then

V _res=V _offset· (G ₃)/(G ₁·G ₂) + (△V)/(G ₁) = (△V)/(G ₁) （37）

Get △ V=50 millivolt and G ₁50,000 residual voltages of ≈ will be less than 1 microvolt.

For at G ₁Reduce this G when amplifying this residual voltage ₁Offset voltage Voff to the influence of node NIN, used automatic biasing technique, this point is detailed to be painted among Figure 12.Figure 13 is the sequential chart of signal among Figure 12.Include the gain G of main amplifier operational amplifier 183 in the circuit of Figure 12 ₃, coupling amplifier 182 gain G ₂Gain G with automatic biasing amplifier 181 ₁The representative factor; Gain G ₄Representative should consumption be closed Amplifier Gain from amplifier.Amplifier 181 is connected to BIAS(biasing) switch 187, zERO(make zero) switch 188 and always add node 191; Amplifier 183 is connected to zERO switch 188 and input end NIN and similarly receives second and always adds node 193, receives output terminal INT then; Amplifier 182 is connected the AZ(auto zero) switch 186, capacitor C ₇Always add between the node 193, simultaneously amplifier 184 is connected to ABIAS(and setovers automatically) switch 185, capacitor C ₆Always add node 191.

The operation of circuit among Figure 12 can be described with reference to Figure 13.Connect switch 187 when BIAS signal (offset signal) is the high value, then the input of amplifier 181 promptly is grounded.Connecting switch 187 back stand-by period t _WThereby all additional capacitors are promptly drawn discharge and are avoided the offset information of mistake is sent to amplifier 184.At stand-by period t _WAfterwards, this ABIAS(setovers automatically) connection switch 185 when signal is the high value, the gain G in this loop ₁And G ₄Make capacitor G ₆Be stabilized in current potential V _ABIAS, cause amplifier 181 to remain on and work in the range of linearity of compensation Voff2.

When the BIAS(biasing) drop to low value, switch 187 open circuits, meanwhile, this ZERO(makes zero) switch 188 is connected, so the input voltage of permission on node NIN is fed to amplifier 181; Through after the short time, signal AZ connects switch 186 and closed this backfeed loop.Connect at this offset signal step-down with by signal AZ and to have guaranteed capacitor C during this period of time between the switch 186 ₇The voltage that is kept is relevant separately with residual migration voltage on node NIN, and disturbs irrelevantly with switch, and ABIAS(setovers automatically in time signal) for during the high value, capacitor C ₆Be coupled with voltage V _ABIASSo the input of node NIN is by G ₁Amplify the back with voltage V _AZCapacitor C feeds ₇, this voltage is exaggerated device G again ₂Provide a corrected value to export INT, V to proofread and correct after the amplification to node 193 _AZWorker's capacitor C ₇Go up needed voltage, in order to V _OffBe reduced to by always adding the deviation voltage V of node 193 _Res

Rely on the same manner of identical geometric position and polar transformation and make amplifier G ₂And G ₄Reduce the influence (square formula 34) of this △ V, and to main amplifier G ₃Be provided with one and do not have skew (offstt-free) system.Temperature drift when this structure has also compensated in short-term with length.

Figure 14 is the detailed circuit schematic diagram that is shown in auto zero operational amplifier 150 in Fig. 9 square frame.Amplifier 150 comprises that a main operational amplifier 200 and one are from operational amplifier 210.This circuit connect setovered by described BIAS(), ZERO(makes zero), ABIAS(setovers automatically) and the AZ(auto zero) signal, these signals were said in conjunction with Figure 13.Transistor 185 is these ABIAS switches, and transistor 186 is these AZ switches, and transistor 187 is made for this BIAS switch and transistor 188 makes zero for ZERO() switch.This extra transistor 216 and 217 is empty transistor, is used for balance and is injected into capacitor C ₆And C ₇Electric charge, avoid any this BIAS(biasing that depends on whereby) frequency (about 256 hertz) of signal.

In main operational amplifier 200, position, transistorized reference number end is demarcated with " a ", and position, transistorized reference number end is demarcated with " b " from amplifier.In main amplifier, transistor 304a and 306a provide a cascaded stages, and transistor 300a and 301a form load, and transistor 303a controls this load, transistor 305a and 307a are differential pairs, and transistor 302a is an output stage, and it and transistor 311 1 work as a current source.Transistor 312 provides a current source, this buffer transistor 308 that is used for setovering, capacitor C ₈The open loop stabilization effect is provided.

Main amplifier 200 utilizes and is connected across capacitor C ₇The degree of polarization of the voltage-controlled transistor 3030a at two ends, the latter is a P channel MOS device.Use a P-channel device and without the N channel device be because it can reduce drift characteristic.In contrast, the n channel device is used for differential pair 305a and 307a, because they have high gain.The degree of polarization that changes transistor 305a, 307a can change the behavior of differential pair 305a, 307a, changes the input off-set voltage of main amplifier whereby.

In order to compensate long drift and variation of temperature, expectation changes aptly across capacitor C ₇On voltage, this is the function from amplifier 210, identical from this work of amplifier 210 and main amplifier 200, wherein transistor 303b response is across capacitor C ₆On current potential and control the load 300b, 301b.This will be explained as follows to encourage this output stage 302b(in differential pair 305b, 307b synthetic variation in service), by the AZ(auto zero) switch 186 permission capacitor C ₇On current potential do suitable change.

When biased witch 187 was connected, the grid of transistor 305b and 307b was in the same place by this switch short circuit.So the both is connected to the current potential of accepting on the node NIN.Because biased witch 187 keeps on-state, so biasing (ABIAS) switch 185 promptly is switched on (sequential chart of seeing Figure 13) automatically.When this thing happens, capacitor C ₆Promptly be pulled to node B, and therefore be offset to V _BIASIn fact, capacitor C ₆On current potential periodically refreshed.

By the time switch 185 is opened a way, and this ZERO(makes zero) switch 188 is connected and BIAS(setovers) switch 187 open circuits, so the grid of transistor 305b just is pulled to the grid of 306a and 307a, so that detection is with respect to any potential difference (PD) of transistor 305b.In fact, equal transistor 307a and encouraging transistor 305b.When the AZ(auto zero) when switch 186 was connected, node B was received capacitor C ₇Thereby upgraded the voltage on it, therefore, the offset voltage of this main amplifier is reduced to this residual voltage V _Res

Figure 15 is the circuit theory diagrams that produce reference voltage.As mentioned above, the precision of the precision of power instrument and reference voltage source be closely related (square formula 32).The circuit of being set forth is a band-gap voltage source, and it depends on base-emitter voltage V _BETo the susceptibility of different temperatures and the base of bipolar transistor-emitter voltage V _BEVariation.Specifically, transistor 245 and 246 assembles to such an extent that compare with 244 with transistor 240,241,242 and have different physical dimensions, transistor 240-342 and 244 size are half of transistor 245, it is 1/4 of transistor 246, transistor 244 works in 1/8 electric current of transistor 240-242, transistor 245 is its 1/4 electric current, and transistor 246 is its electric current of 1/2.By resistance R ₃And R ₄(also can comprise semifixed resistor, not shown) constitutes voltage divider, and the emitter that is connected transistor 246 is through transistor 250 to V _SSBetween.An input end of an operational amplifier 260 is connected resistance R ₃And R ₄Between, and its another input end is connected to sending out of transistor 240 and unloads the utmost point.Oxide-semiconductor control transistors 250,251,252,253,254 and 255 is received in the output of this operational amplifier 260.

This bandgap voltage reference generator that is shown in Figure 15 comprises that stacked transistor 244,245 and 246 is to produce a band gap that is three times in independent device.This higher band gap makes the influence of arbitrary offset voltage error that operational amplifier 260 causes reduce to minimum.A series of series-connected stages 255 and 256,254 and 257 etc. provide the calibration current source to transistor 240,241 etc.

As everyone knows, transistorized base-emitter voltage (V _BE) mainly be to change with temperature, for example, the V of a standard bipolar device _BETo give 2 millivolts with 1 ℃ of reduction of the every decline of temperature.Though, in power meter whole service temperature range, having terribly cold and awfully hot environment temperature (40 ℃ to+85 ℃), this variation will cause the variation of reference voltage to arrive the degree of the precision of breakdown power table greatly.Also have a bit and know, be i.e. two transistors that are operated under the different current densities, change in voltage △ V between its base-emitter-base bandgap grading _BEMay have positive temperature coefficient (PTC).Shown circuit combines these two kinds influences and a temperature independent in fact reference voltage is provided, at terminal V _RefOn output voltage alleviated fluctuation and can be used for providing V in Fig. 4 and 9 _Ref

The V of this transistor 240,241,242 _BEFor

V _BE240-2= (KT)/(q) Ln (I ₁)/(Is·A ₁) （38）

Is is a saturation current in the formula, I ₁Be emitter current, and A ₁It is 240,241 and 242 area.Transistor 244,245 and 246 V _BEBe

V _BE244-6=3 (KT)/(q) Ln (I ₁)/(Is·8·A ₁) （39）

So this difference is

△ V _BE=V _BELeft side-V _BEThe Ln8 (40) of right side=(3KT)/(q)

V _Ref=-V _BERight side (R ₃+ R ₄)/(R ₃) (△ V _BB-V ₀) (41)

Temperature to the influence of KT/q be about 85 microvolts/℃, to V _BEInfluence be about-2 millivolts of/℃ (R ₃+ R ₄)/R ₃Be about 11.3.

As mentioned above, power meter meter of the present invention provides the measurement of pin-point accuracy to the consumption of distribution system or the power confessed, though most preferred embodiment of the present invention is set forth in conjunction with appended given circuit, scope of the present invention is then determined with following claims.

Claims (6)

1, be used for measuring the system of electric energy in the circuit (15), it comprises:

Voltage check device (20) is coupled on this circuit, is used for the first signal (V that provides relevant with this circuit current potential _v(t));

Current sensing means (24) is coupled on this circuit, is used for the secondary signal (C that provides current related with this circuit _c(t));

Multiplier (45,40) receives first and second signals, and the 3rd a signal (I with electric current of representing the first secondary signal product is provided _p(t));

Converter apparatus (50) receives the 3rd signal and the 4th signal with frequency relevant with the first secondary signal product is provided;

It is characterized in that:

Converter apparatus (50) comprises sign bit device (170,175), be used for providing the sign bit digital signal to multiplier, when in the circuit-under-test during energy consumption this digital signal be first state, when in the circuit-under-test during supplying energy this digital signal be second state.

2, the system of claim 1, wherein multiplier comprises:

Signal generator device (35) is used to produce the signal of one-period sex change;

Comparison means (30) receives a signal of selecting in the above-mentioned periodically variable signal and first secondary signal, when a signal of selecting in the cycle variable signal and first secondary signal has predetermined the relation, produces a comparison output signal (44);

Switch Control current source apparatus (24,40), it is controlled by comparison output signal, receives another signal in first secondary signal, and produces the 3rd signal.

3, the system of claim 2, wherein comparison output signal is compared by a signal of selecting in the related amplitude value of cyclical variation signal and first secondary signal and is obtained.

4, the system of claim 3, wherein the signal of Xuan Zeing is first signal.

5, the system of claim 2,3 or 4 also comprises logical unit, and it receives the digital signal of comparison output signal and sign bit device, and comes gauge tap Control current source apparatus according to them.

6, the system of claim 5, its logical unit comprises an XOR gate.

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