CN102737974A - 制造多个栅极结构的方法 - Google Patents
制造多个栅极结构的方法 Download PDFInfo
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- CN102737974A CN102737974A CN2011103105232A CN201110310523A CN102737974A CN 102737974 A CN102737974 A CN 102737974A CN 2011103105232 A CN2011103105232 A CN 2011103105232A CN 201110310523 A CN201110310523 A CN 201110310523A CN 102737974 A CN102737974 A CN 102737974A
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本发明涉及集成电路的制造,并且更具体地涉及一种带有多个栅极结构的半导体器件。该制造多个栅极结构的示例性方法包括:提供硅衬底;在衬底上方沉积伪氧化物层;在伪氧化物层上方沉积伪栅电极层;将层图案化,从而限定出多个伪栅极;在多个栅电极上形成含氮的侧壁隔离件;在含氮的侧壁隔离件之间形成层间介电层;通过原子层沉积(ALD)工艺,在层间介电层上选择性地沉积硬掩模层;去除伪栅电极层;去除伪氧化物层;沉积栅极电介质;以及沉积栅电极。本发明还提供了一种制造多个栅极结构的方法。
Description
技术领域
本发明涉及集成电路的制造,并且更具体地涉及一种带有多个栅极结构的半导体器件。
背景技术
随着晶体管尺寸的减小,在栅极长度缩短的情况下必须减小栅极氧化物的厚度来保持性能。然而,为了减少栅极的泄漏,通常要使用具有高介电常数(高-k)的栅极氧化物层,该具有高介电常数的栅极氧化物层允许较大的物理厚度,并同时保有了与在将来的技术节点中使用普通的栅极氧化物所提供的相同的有效厚度。
另外,随着技术节点的缩小,在一些集成电路(IC)的设计中需要利用金属栅电极替代普通的多晶硅栅电极,从而在部件尺寸减小的情况下改善器件的性能。形成金属栅电极的工艺被称作“后栅极”工艺,其中,最终的金属栅电极“最后”形成,从而减少了在栅极形成之后必须实施的,包括高温工艺的后续工艺的数量。
然而,对制造互补金属氧化物半导体(CMOS)而言,仍存在实施这种部件和工艺的挑战。随着栅极长度和器件之间的间隔的减小,这些问题变得严峻。例如,在“后栅极”制造工艺中,由于在湿式蚀刻/干式蚀刻伪栅极之后在层间介电(ILD)层中产生了不期望的凹槽,因此在相邻的晶体管之间难以实现理想的隔离。这些存在于ILD层中的凹槽在后续的工艺中变成了金属的容器,从而增加了电短路和/或器件故障的可能性。
发明内容
在一个实施例中,提供了一种制造多个栅极结构的方法,包括:提供硅衬底;在衬底上方沉积伪氧化物层;在伪氧化物层上方沉积伪栅电极层;将层图案化,从而限定出多个伪栅极;在多个伪栅极上形成含氮的侧壁隔离件;在含氮的侧壁隔离件之间形成层间介电层;通过原子层沉积(ALD)工艺,在层间介电层上选择性地沉积硬掩模层;去除伪栅电极层;去除伪氧化物层;沉积栅极电介质;以及沉积栅电极。
在另一实施例中,提供了一种制造多个栅极结构的方法,包括:提供硅衬底;在衬底上方沉积伪氧化物层;在伪氧化物层上方沉积伪栅电极层;将层图案化,从而限定出多个伪栅极;在多个栅电极上形成含氮的侧壁隔离件;在含氮的侧壁隔离件之间形成层间介电层;通过原子层沉积(ALD)工艺,在层间介电层上选择性地沉积硬掩模层;去除伪栅电极层;通过使伪氧化物层暴露于包含NH3和含氟化合物的蒸汽混合物来去除伪氧化物层;沉积栅极电介质;以及沉积栅电极。
此外,为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种制造多个栅极结构的方法,包括:提供硅衬底;在所述衬底上方沉积伪氧化物层;在所述伪氧化物层上方沉积伪栅电极层;将所述层图案化,从而限定出多个伪栅极;在所述多个伪栅极上形成含氮的侧壁隔离件;在所述含氮的侧壁隔离件之间形成层间介电层;通过原子层沉积(ALD)工艺,在所述层间介电层上选择性地沉积硬掩模层;去除所述伪栅电极层;去除所述伪氧化物层;沉积栅极电介质;以及沉积栅电极。
在该方法中,所述ALD工艺包括一系列的ALD周期。
在该方法中,所述ALD工艺包括将金属前体和羟基前体的交替脉冲提供到反应室。
在该方法中,所述金属前体包括四氯过渡金属复合物。
在该方法中,所述四氯过渡金属复合物包括选自由ZrCl4、HfCl4、和TiCl4构成的组中的化学品。
在该方法中,所述羟基前体包括选自由H2O和H2O2构成的组中的化学品。
在该方法中,在大约120℃至300℃的温度下实施所述ALD工艺。
在该方法中,所述硬掩模层包括金属氧化物。
在该方法中,所述金属氧化物包括选自由氧化锆、氧化铪、或氧化钛构成的组中的材料。
在该方法中,所述含氮的介电层包括氮化硅或氮氧化硅。
在该方法中,通过使所述伪氧化物层暴露于包含NH3和含氟化合物的蒸汽混合物来实施去除所述伪氧化物层的步骤。
在该方法中,所述含氟的化合物选自由HF和NF3构成的组。
在该方法中,所述蒸汽混合物包括NH3和HF。
在该方法中,在10mTorr和25mTorr之间的压力下实施将所述伪氧化物层暴露于蒸汽混合物的步骤。
在该方法中,所述蒸汽混合物包括NH3和NF3。
在该方法中,在2Torr和4Torr之间的压力下实施将伪氧化物层暴露于蒸汽混合物的步骤。
在该方法中,所述蒸汽混合物进一步包括运载气体。
在该方法中,所述运载气体包括惰性气体。
在该方法中,所述惰性气体包括N2、He、或Ar。
在该方法中,进一步包括:在沉积所述栅电极之后,去除所述硬掩模层。
将结合附图在以下的实施例中进行详细描述。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上,为了清楚地论述,各种部件的尺寸可以被任意增加或减少。
图1是示出了根据本发明的各个方面的制造多个栅极结构的方法的流程图;以及
图2A-图2I示出了根据本发明的各个方面的在各个制造阶段中的多个栅极结构的示意性横截面图。
具体实施方式
以下公开提供了各种不同实施例或实例,用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不旨在限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在各个实例中重复参考符号和/或字符。这种重复用于简化和清楚,并且其本身不表示所述各个实施例和/或配置之间的关系。
参考图1,示出了根据本发明的各个方面的制造多个栅极结构的方法100的流程图。该方法100以步骤102开始,其中,提供了硅衬底。方法100继续进行到步骤104,其中,在衬底上沉积伪氧化层。方法100继续进行到步骤106,其中,在伪氧化层上沉积伪栅电极层。方法100继续进行到步骤108,其中,将这些层图案化,从而限定出多个伪栅极。方法100继续进行到步骤110,其中,在多个伪栅极上形成含氮的侧壁隔离件。方法100继续进行到步骤112,其中,在含氮的侧壁隔离件之间形成层间介电层。方法100继续进行到步骤114,其中,通过原子层沉积(ALD)工艺将硬掩模层选择性地沉积在层间介电层上。方法100继续进行到步骤116,其中,将伪栅电极层去除。方法100继续进行到步骤118,其中,去除伪氧化层。方法100继续进行到步骤120,其中,沉积栅极电介质。方法100继续进行到步骤122,其中,沉积栅电极。下面的论述示出了能够根据图1的方法100制造的多个栅极结构的实施例。
参考图2A-图2I,示出了根据本发明的各个方面的在各个制造阶段中的半导体器件200的多个栅极结构230的示意性横截面图。应该注意,图1的方法不能制造完整的半导体器件。可以使用互补金属氧化物半导体(CMOS)技术工艺制造完整的半导体器件200。因此,可以理解,可以在图1的方法100之前、之中以及之后提供附加的工艺,并且在此仅对这些其他的工艺进行简要描述。同时,为了更好地理解本发明的发明构思,图1至图2I被简化。例如,尽管附图示出了多个用于半导体器件200的栅极结构230,但是可以理解,集成电路(IC)可以包括多个其它器件,包括电阻器、电容器、电感器、保险丝等等。
参考图2A,提供了包括有源区域203和隔离区域204的衬底202。在一个实施例中,衬底202包括晶体硅衬底(例如,晶圆)。取决于设计需要(例如,p-型衬底或n-型衬底),衬底202可以包括各种掺杂结构。另外,衬底202包括外延层(epi layer),可以发生应变以增强性能,和/或可以包括绝缘体上硅(SOI)结构。
取决于设计需要,有源区域203包括各种掺杂配置。在一些实施例中,有源区域203可以掺杂有p-型或n-型掺杂剂。例如,有源区域203可以掺杂诸如硼或BF2的p-型掺杂剂;诸如磷或砷的n-型掺杂剂;和/或其组合。该有源区域203可以作为被配置用于N-型金属氧化物半导体晶体管器件(被称作NMOS)的区域,并且可以作为被配置用于P-型金属氧化物半导体晶体管器件(被称作PMOS)的区域。
隔离区域204可以形成在衬底202上,从而隔离各个有源区域203。该隔离区域204可以使用隔离技术,比如,硅的局部氧化(LOCOS)或浅沟槽隔离(STI),来限定并且电隔离多个有源区域203。在本实施例中,隔离区域204包括STI。隔离区域204可以包括氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSC)、低介电常数(low-k)的介质材料、其他适当的材料和/或其组合。可以通过任意适当的工艺形成隔离区域204,本实施例中使用了STI。作为一个实例,STI的形成方式包括:通过光刻工艺图案化半导体衬底202,在衬底202中蚀刻沟槽(例如,使用干式蚀刻、湿式蚀刻、和/或等离子体蚀刻工艺)以及利用介电材料填充沟槽(例如,使用化学汽相沉积工艺)。在一些实施例中,被填充的沟槽可以具有多层结构,比如,填充有氮化硅或氧化硅的热氧化衬垫层。
仍参考图2A,然后,通过在衬底202上相继沉积和图案化伪氧化层212和伪栅电极层214,从而限定出多个伪栅极210。可以使用包括在本文中描述的工艺的任何适当的工艺,来形成多个伪栅极210。在一个实例中,伪氧化层212和伪栅电极层214相继沉积在衬底202上。在本实施例中,伪氧化层212由通过热氧化工艺生长的,厚度为大约至的氧化硅形成。例如,伪氧化层212可以通过迅速热氧化(RTO)工艺生长或在含氧的退火工艺中生长。
在一些实施例中,伪栅电极层214可以包括单层或多层结构。在本实施例中,伪栅电极层214可以包括多晶硅。另外,伪栅电极层214可以相同或不同的掺杂方式掺杂多晶硅。伪栅电极层214包括任意适当的厚度。在本实施例中,伪栅电极层214的厚度处在大约30nm至大约80nm的范围内。使用低压化学汽相沉积(LPCVD)工艺形成该伪电极层214。可以在LPCVD炉中在大约580℃至650℃的温度下和大约200mTorr至1Torr的压力下使用硅烷(SiH4)、乙硅烷(Si2H6)、丙硅烷(Si3H8)或二氯甲硅烷(SiH2Cl2)实施该LPCVD工艺。
然后,在伪栅电极层114上方通过适当的工艺,例如,旋转涂布,来形成光阻层(未示出),并且通过适当的光刻图案化方法进行图案化,从而形成经过图案化的光刻胶部件。经过图案化的光刻胶部件的宽度在大约15nm至45nm的范围内。然后可以使用干式蚀刻工艺将经过图案化的光刻胶部件传递给下方的层(即,伪氧化层212和伪栅电极层214),从而限定出多个伪栅极210。可以在此后去除该光刻胶层。
在另一实例中,硬掩模层(未示出)形成在伪栅电极层214上方;经过图案化的光刻胶层形成在硬掩模层上;光刻胶层的图案被传递给硬掩模层,并且然后被传递给伪栅电极层214和伪氧化层212,从而限定出多个伪栅极210。可以理解,上述实例没有对形成多个伪栅极210的处理步骤进行限制。可以进一步理解,多个伪栅极210可以包括附加的介电层和/或导电层。例如,多个伪栅极210可以包括硬掩模层、界面层、覆盖层、扩散层/阻挡层、其他适当的层、和/或其组合。
参考图2B,多个伪栅极210可以用于补偿轻微掺杂的源极/漏极(LDD)区域206。该LDD区域206形成在衬底202的有源区域203中。可以通过一个或多个诸如工艺,例如,离子注入工艺,将LDD区域206形成在有源区域203中。掺杂种类取决于被制造的器件的类型,比如,NMOS或PMOS器件。例如,LDD区域206可以利用诸如硼或BF2的p-型掺杂剂诸如磷或砷的n-型掺杂剂;和/或其组合进行掺杂。LDD区域可以包括多个掺杂轮廓。在离子注入工艺之后,LDD区域206与多个伪栅极210的外边缘对齐。
在LDD区域206形成之后,含氮的介电层216形成在多个伪栅极210上。含氮的介电层216可以处在多个伪栅极210的每个侧面上,并且作为侧壁隔离件。并且由此可以被称作含氮的侧壁隔离件216。可以通过等离子体沉积,在小于400℃的温度下和大约200mTorr至1Torr的压力下,使用SiH4、NH3和/或N2O作为反应气体,形成该含氮的侧壁隔离件216。该侧壁隔离件216可以包括氮化硅、氮氧化硅、氮碳化硅、和/或其组合。该侧壁隔离件216可以包括多层结构。该侧壁隔离件216可以是任意适当的厚度。在本实施例中,侧壁隔离件216的厚度在大约7nm至大约25nm的范围内。
仍参考图2B,侧壁隔离件216被用于补偿源极/漏极(S/D)区域208(也称作重掺杂的源极/漏极区域)。该S/D区域208可以通过一个或多个诸如离子注入工艺的注入工艺形成在衬底202的有源区域203中。掺杂的种类取决于被制造的器件类型,比如,NMOS或PMOS器件。例如,S/D区域208可以掺杂有诸如硼或BF2的p-型掺杂剂;诸如磷或砷的n-型掺杂剂;和/或其组合。S/D区域208可以包括各种掺杂轮廓,并且在离子注入工艺之后,该S/D区域208与侧壁隔离件216的外边缘对准。在一些实施例中,该S/D区域208可以进一步包括升高的S/D区域。同时,可以在该S/D区域208上通过自对准的硅化工艺形成一个或多个接触部件(例如,硅化物区域)。
参考图2C,可选的接触蚀刻停止层(CESL)218可以通过包括本文所描述的工艺的任意适当工艺,形成在衬底202上方,包括形成在多个伪栅极210上方。CESL 218可以由氧化硅、氮化硅、氮氧化硅、或其组合形成。可以使用等离子体增强CVD(PECVD)混合频率工艺形成该CESL 218。该CESL 218进一步包括任意适当的厚度。在本实施例中,CESL 218的厚度大约为在一些实施例中,不使用CESL 218。
仍参考图2C,在CESL 218形成之后,在CESL层218上形成层间介电层(ILD)220。ILD层220可以包括介电材料。该介电材料可以包括氧化硅、旋涂玻璃(SOG)、氟硅玻璃(FSG)、碳掺杂的氧化硅(例如,SiCOH),BLACK(Santa Clara,California的AppliedMaterials)、其他适当的介电材料、和/或其组合。在一些实施例中,ILD层220可以包括高密度等离子体(HDP)介电材料(例如,HDP氧化物)和/或高纵横比工艺(HARP)介电材料(例如,HARP氧化物)。该ILD层220包括任意适当的厚度。在本实施例中,ILD层220的厚度处于大约至大约的范围内。可以理解,ILD层220可以包括一种或多种介电材料和/或一个或多个介电层。
然后,可以通过化学机械抛光(CMP)工艺对CESL 218和/或ILD层220进行平坦化,直至如图2D中所示处在衬底202上方的多个伪栅极210的顶部暴露出来为止。CMP工艺可以具有高选择性,从而为多个伪栅极210、含氮的侧壁隔离件216、CESL 218以及ILD层220提供基本上平坦的表面。这样,在本实施例中,ILD层220形成在含氮的侧壁隔离件216之间。另外,多个伪栅极210被介电层包围,该介电层包括含氮的侧壁隔离件216、CESL 218以及ILD层220。
在CMP工艺之后,实施栅极替换工艺。使用湿式蚀刻和/或干式蚀刻工艺去除多个伪栅极210,从而形成用于形成多个栅极结构230(如图2I所示)的开口。应该注意,湿式蚀刻和/或干式蚀刻工艺尤其容易去除ILD层220的部分,从而在ILD层220中产生不期望的凹槽。存在于ILD层220中的不期望的凹槽在后续工艺过程中成为金属的容器(receptacle ofmetals),由此增大了电短路和/或器件故障的可能性。相应地,下面参考图2E-图2I所描述的工艺可以保护ILD 220在去除伪栅极210的过程中不受到损害。这样可以减少不期望的凹槽在ILD层中的产生,并且提升器件性能。
图2E示出了在通过原子层沉积(ALD)工艺将硬掩模222选择性地沉积在ILD层上之后的图2D中的半导体器件200。ALD工艺包括向反应室提供金属前体脉冲和羟基前体的交替脉冲。反应物的每个脉冲都以自我限制的方式使表面饱和。
在其中形成了硬掩模层222的示例性ALD工艺包括以下步骤。首先,将半导体衬底装入反应室中。然后,在第一时间段内将羟基前体脉冲注入到装载有半导体衬底202的反应室中。在此,该羟基前体包括选自由H2O和H2O2构成的组中的化学品。由于羟基前体被注入到反应室中,因此,羟基前体的化学吸附层选择性地形成在ILD层220的顶表面上,而不形成在伪栅电极层214的顶表面上。然后,在第二时间段中将剩余的羟基前体从反应室中释放。为了更有效地将剩余的羟基前体从反应室中释放出来,可以在该净化周期中向反应室中注入清扫用气体,其中,该净化气体可以包括基本上的惰性气体,比如,N2、Ar、He或类似的惰性气体。
在将剩余的羟基前体从反应室释放出来之后,在第三时间段中将金属前体脉冲注入到反应室内。在这里,金属前体与羟基前体的化学吸附层反应的可能性很大。作为一个实例,金属前体包括四氯过渡金属复合物。在本实施例中,该四氯过渡金属复合物包括选自由ZrCl4、HfCl4、以及TiCl4构成的组中的化学品。金属前体与羟基前体的化学吸附层在大约120℃至300℃的温度上发生反应。因此,硬掩模层222的原子层形成在ILD层220的顶表面上,而没有形成在伪栅电极层214的顶表面上。在本实施例中,硬掩模层222包括金属氧化物。在一个实施例中,金属氧化物包括选自由氧化锆、氧化铪、或氧化钛构成的组中的材料。
然后,在第四时间段内将所有剩余的的金属前体从反应室中释放出来。为了在第二清扫周期内更有效地将剩余的金属前体从反应室中释放出来,可以向反应室中注入基本上的惰性气体,比如N2、Ar、He或类似的惰性气体。
ALD工艺通常包括一系列的ALD周期,即,第一时间段至第四时间段,如上所述,在这些时间段中每个羟基前体和金属前体被交替地注入到反应室中并且在此之后从反应室中释放出来,当这些时间段合在一起时,则被视作一种成分或层的形成周期。通过多次重复该周期,由此形成带有所期望的厚度的硬掩模层222。该硬质硬膜层222可以具有大约1nm至4nm的厚度。在沉积工艺之后,将硬质掩模层222形成在ILD层220的顶表面上,而不是形成在伪栅电极层214的顶表面上,从而在蚀刻伪栅极210的过程中保护ILD层220。
参考图2F,在将硬掩模层222选择性地沉积在ILD层220上之后,可以将伪栅电极层214从多个被含氮的侧壁隔离件216和ILD层220包围的伪栅极210中去除。伪栅电极层214被去除,从而在含氮的侧壁隔离件216中通过任意适当的工艺包括,在此所述的工艺形成开口224。可以使用湿式蚀刻和/或干式蚀刻工艺去除伪栅电极层214。在一个实施例中,用于伪多晶硅栅电极层214的湿式蚀刻工艺包括暴露于含有氢氧化铵的氢氧化物溶液、经过稀释的HF、去离子水、和/或其他适当的蚀刻溶液。在其他实施例中,可以在大约650W至800W的源极功率、大约100W至120W的基极功率,以及大约60mTorr至200mTorr的压力下使用Cl2、HBr以及He作为蚀刻气体来为伪多晶硅栅电极层214实施干式蚀刻工艺。
参考图2G,在去除伪栅电极层214之后,通过湿式蚀刻工艺或汽相蚀刻工艺去除伪氧化物层212。在一个实施例中,利用含HF的溶液实施用于伪氧化层212的湿蚀刻工艺。优选地,利用该含HF的溶液蚀刻伪氧化层212,从而几乎不去除或完全不去除侧壁隔离件216和硬掩模层222,由此保护了ILD层220。因此,用于制造栅极结构的方法在ILD层220中几乎不产生凹槽。
在另一实施例中,汽相蚀刻工艺开始将图2F的结构引入到密封的反应室中,在该反应室中汽相蚀刻工艺使用汽相反应物。该蚀刻工艺是自我限制的,其中,通过引入到反应室中的汽相反应物的量确定去除了的材料的量。在一些实施例中,通过使伪氧化物层212暴露于包括NH3以及含氟化合物的蒸汽混合物来实施汽相蚀刻工艺。
该含氟化合物可以是选自由HF或HF3构成的组中的化合物。在一个实施例中,蒸汽混合物包括NH3和HF,并且在10mTorr和25mTorr之间的压力下实施。NH3和HF的蒸汽混合物中NH3和HF的体积比在大约0.1至10之间。在另一实施例中,蒸汽混合物包括NH3和HF,并且在2Torr和4Torr之间的压力下实施。NH3和HF的蒸汽混合物中NH3和HF的体积比在大约0.5至5之间。该蒸汽混合物可以进一步包括运载气体,比如,惰性气体。该惰性气体包括N2、He、或Ar。
优选地,利用该蒸汽混合物蚀刻伪氧化物层212,从而几乎不去除或完全不去除侧壁隔离件216和硬掩模层222。因此,在图2G中所示的汽相蚀刻工艺结束时,该汽相蚀刻工艺可以完全去除伪氧化层212,暴露出硅衬底202,并且在含氮的侧壁隔离件216中形成开口226。因此,用于制造栅极结构的方法在ILD层220几乎不产生凹槽。
参考图2H,在去除伪氧化层212之后,沉积栅极电介质232和栅电极234,以完全填满开口226,从而形成多个栅极结构230。在一些实施例中,栅极电介质232可以包括氧化硅、氮氧化硅、高-k介电层、或其组合。高-k介电材料被限定为介电常数大于SiO2(即,大于3.9)的介电材料。该高-k介电层包括金属氧化物。该金属氧化物选自由Li的氧化物、Be的氧化物、Mg的氧化物、Ca的氧化物、Sr的氧化物、Sc的氧化物、Y的氧化物、Zr的氧化物、Hf的氧化物、Al的氧化物、La的氧化物、Ce的氧化物、Pr的氧化物、Nd的氧化物、Sm的氧化物、Eu的氧化物、Gd的氧化物、Tb的氧化物、Dy的氧化物、Ho的氧化物、Er的氧化物、Tm的氧化物、Yb的氧化物、Lu的氧化物以及其组合构成的组中的金属氧化物。该高-k介电层232具有大约1nm至大约4nm的厚度。栅极介电层232可以进一步包括界面层,从而减小栅极介电层232和衬底202之间的损伤。该层间层可以包括氧化硅。在一些实施例中,栅电极234包括选自由Al、Cu、AiTi、TiN、TiCN、TaN、TaCN、WN以及WCN构成的组中的材料。
图2I示出在诸如化学机械抛光(CMP)工艺的平坦化工艺之后的图2H的衬底202。该CMP工艺可以去除栅电极234、栅极电介质232以及硬掩模层222的部分,直到到达ILD层220的顶表面。保留下的栅电极234和栅极电介质232组合在一起并且在下文中称作多个栅极结构230。然后,必须在形成多个栅极结构230之后实施包括互连工艺的后续工艺,从而完成半导体器件200的制造。
虽然通过实例并且根据优选的实施例描述了本发明,但可以理解本发明不限于所公开的实施例。相反,这些实施例旨在涵盖各种改变和类似的布置(对本领域的技术人员而言是显而易见的)。因此,所附的权利要求的范围应符合最广泛的解释,从而包括所有这些改变和类似的布置。
Claims (10)
1.一种制造多个栅极结构的方法,包括:
提供硅衬底;
在所述衬底上方沉积伪氧化物层;
在所述伪氧化物层上方沉积伪栅电极层;
将所述层图案化,从而限定出多个伪栅极;
在所述多个伪栅极上形成含氮的侧壁隔离件;
在所述含氮的侧壁隔离件之间形成层间介电层;
通过原子层沉积(ALD)工艺,在所述层间介电层上选择性地沉积硬掩模层;
去除所述伪栅电极层;
去除所述伪氧化物层;
沉积栅极电介质;以及
沉积栅电极。
2.根据权利要求1所述的方法,其中,所述ALD工艺包括一系列的ALD周期。
3.根据权利要求1所述的方法,其中,所述ALD工艺包括将金属前体和羟基前体的交替脉冲提供到反应室。
4.根据权利要求3所述的方法,其中,所述金属前体包括四氯过渡金属复合物,
所述四氯过渡金属复合物包括选自由ZrCl4、HfCl4、和TiCl4构成的组中的化学品,或者
其中,所述羟基前体包括选自由H2O和H2O2构成的组中的化学品。
5.根据权利要求1所述的方法,其中,在大约120℃至300℃的温度下实施所述ALD工艺,或者
其中,所述硬掩模层包括金属氧化物,
所述金属氧化物包括选自由氧化锆、氧化铪、或氧化钛构成的组中的材料,或者
其中,所述含氮的介电层包括氮化硅或氮氧化硅。
6.根据权利要求1所述的方法,其中,通过使所述伪氧化物层暴露于包含NH3和含氟化合物的蒸汽混合物来实施去除所述伪氧化物层的步骤。
7.根据权利要求6所述的方法,其中,所述含氟的化合物选自由HF和NF3构成的组,或者
其中,所述蒸汽混合物包括NH3和HF,
在10mTorr和25mTorr之间的压力下实施将所述伪氧化物层暴露于蒸汽混合物的步骤,或者
其中,所述蒸汽混合物包括NH3和NF3,
在2Torr和4Torr之间的压力下实施将伪氧化物层暴露于蒸汽混合物的步骤。
8.根据权利要求6所述的方法,其中,所述蒸汽混合物进一步包括运载气体。
9.根据权利要求8所述的方法,其中,所述运载气体包括惰性气体,
所述惰性气体包括N2、He、或Ar。
10.根据权利要求1所述的方法,进一步包括:在沉积所述栅电极之后,去除所述硬掩模层。
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