CN102693948B - Packing structure with monolayer circuit - Google Patents
Packing structure with monolayer circuit Download PDFInfo
- Publication number
- CN102693948B CN102693948B CN201110078203.9A CN201110078203A CN102693948B CN 102693948 B CN102693948 B CN 102693948B CN 201110078203 A CN201110078203 A CN 201110078203A CN 102693948 B CN102693948 B CN 102693948B
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- Prior art keywords
- layer
- wire
- perforate
- welding resisting
- pad
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- Expired - Fee Related
Links
- 238000012856 packing Methods 0.000 title claims abstract description 12
- 239000002356 single layer Substances 0.000 title 1
- 238000003466 welding Methods 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 238000005728 strengthening Methods 0.000 claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 14
- 239000000084 colloidal system Substances 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 4
- 239000003755 preservative agent Substances 0.000 claims description 4
- 230000002335 preservative effect Effects 0.000 claims description 4
- 238000002386 leaching Methods 0.000 claims description 3
- 230000002787 reinforcement Effects 0.000 abstract 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 150000001879 copper Chemical class 0.000 description 4
- 230000001771 impaired effect Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
The invention provides a packing structure, which comprises a dielectric layer provided with opposite first surface and second surface and a plurality of through holes penetrating through the first surface and the second surface, a reinforcement layer arranged on the dielectric layer, a line layer arranged on the dielectric layer and provided with a plurality of routing pads and reballing pads connected with the routing pads, a first anti-welding layer arranged on the dielectric layer and provided with a plurality of first openings for the exposure of the routing pads, a second anti-welding layer arranged on the dielectric layer and provided with a plurality of second openings for the exposure of the reballing pads, and a semiconductor chip arranged on the first anti-welding layer and connected with the routing pads exposed out of the through holes by a wire. Therefore, the openings are not etched for a long time, and the routing pads and the reballing pads are not damaged due to the forming of the openings; and as the surface of the reinforcement layer is not damaged, the first anti-welding layer formed on the reinforcement layer is flat and smooth, and when being arranged on the first anti-welding layer, the semiconductor chip can maintain stable and does not shift.
Description
Technical field
The present invention relates to a kind of encapsulating structure, particularly relate to and a kind ofly make semiconductor chip held stationary and the encapsulating structure that do not offset of position.
background technology
Along with the evolution of semiconductor packaging, weld (Wire bonding) except conventional link and cover except the semiconductor packaging of crystalline substance (Flip chip), different encapsulation forms developed by current semiconductor device (Semiconductor device), such as directly in a base plate for packaging (package substrate), be embedded into a chip, this kind of packaging part can reduce the volume of overall package structure and promote electrical functionality, and various packing forms can be coordinated to do to change.
Refer to shown in Figure 1A to Fig. 1 D, this is the method for making schematic diagram of encapsulating structure in prior art.As shown in Figure 1A, the encapsulating structure of prior art provides a copper base 10, and copper base 10 has relative first surface 10a and second surface 10b, patterning photoresist layer 110 and resistance layer 111 is formed respectively on this first surface 10a and second surface 10b, again corrosion process is carried out to this copper base 10, to form a storage tank 12a and multiple groove 12b.As shown in Figure 1B, on the wall of this storage tank 12a, plate the first metal layer 120a, and on the wall of this groove 12b, plate the second metal level 120b, then remove this patterning photoresist layer 110 and resistance layer 111.As shown in Figure 1 C, the first metal layer 120a bottom this storage tank 12a is coated with mucigel 15 and puts semiconductor chip 13 with glutinous, this semiconductor chip 13 has multiple electronic pads 130, is electrically connected this second metal level 120b by wire 14.Then, on this copper base 10, packing colloid 17 is formed, with this semiconductor chip 13 coated and wire 14.As shown in figure ip, remove this copper base 10, to expose this first metal layer 120a and the second metal level 120b, and this second metal level 120b is as convex contact 16.Electronic pads 130 on this semiconductor chip 13 can be external to printed circuit board (PCB) via wire 14 and convex contact 16.
But, in the prior art, because this storage tank 12a and groove 12b formed through corrosion process, result in bottom land and must produce irregular phenomenon, so that when this semiconductor chip 13 is placed in this storage tank 12a, can cause steadily and the problem of skew; And this packaging body is without reinforced structure, meet the flexible distortion of external force.
And, when this copper base 10 of erosion removal, because of the difference in thickness between this storage tank 12a and convex contact 16, need more etching time, easily cause this first metal layer 120a and the second metal level 120b impaired.
Therefore, how to avoid the disadvantages of encapsulating structure in prior art, really become the problem of desiring most ardently solution at present.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, an object of the present invention is to provide a kind of encapsulating structure, can make its semiconductor chip held stationary and position does not offset, and makes encapsulating structure have some strength not easily flexural deformation.
Another object of the present invention is to provide a kind of encapsulating structure, can not be impaired when its routing can be made to be padded on encapsulation.
For achieving the above object, the invention provides a kind of encapsulating structure, wherein, comprising:
Dielectric layer, has relative first surface and second surface, and has multiple perforation running through this first and second surface;
Strengthening layer, is located on the first surface of this dielectric layer;
Line layer, is located on the second surface of this dielectric layer, and this line layer have multiple expose to described perforation wire pad and be electrically connected this wire pad plant ball pad;
First welding resisting layer, on the first surface being located at this dielectric layer and strengthening layer, and this first welding resisting layer forms multiple first perforate, exposes to described first perforate to make described wire pad;
Second welding resisting layer, on the second surface being located at this dielectric layer and line layer, and this second welding resisting layer forms multiple second perforate, exposes to described second perforate to plant ball pad described in making; And
Semiconductor chip, is located on this first welding resisting layer, and this semiconductor chip is electrically connected the wire pad exposing to described perforation by wire.
According to design of the present invention, wherein, this semiconductor chip has relative acting surface and non-active face, and this acting surface has the electronic pads of the described wire of multiple electric connection, and this non-active face is bonded on this first welding resisting layer.
According to design of the present invention, wherein, also comprise surface-treated layer, be located at this wire pad and plant on ball pad.
According to design of the present invention, wherein, the material forming this surface-treated layer is selected from and soaks by electronickelling/gold, chemical nickel plating/gold, change nickel the group that gold (ENIG), change nickel palladium leaching golden (ENEPIG), chemical plating stannum (ImmersionTin) and organic solderability preservative (OSP) form.
According to design of the present invention, wherein, also comprise soldered ball, be located at planting on ball pad in this second perforate.
According to design of the present invention, wherein, also comprise packing colloid, be located on this first welding resisting layer, the first perforate and perforation in, to cover semiconductor chip, wire and described wire pad.
In sum, encapsulating structure of the present invention is not damaged because of the surface of this strengthening layer, and the first welding resisting layer thus formed thereon keeps smooth.Compared to prior art, when this semiconductor chip is placed on this first welding resisting layer, this semiconductor chip can held stationary and position not offset.And, because the perforation run through through long-time corrosion, must can not hurt wire pad and plant ball pad, thus promote the quality of electric connection after making formation perforate.
Accompanying drawing explanation
Figure 1A to Fig. 1 D is the cutaway view of the method for making of encapsulating structure in prior art;
Fig. 2 A to Fig. 2 E is the cutaway view of the method for making of encapsulating structure of the present invention;
Fig. 3 A is the upward view that encapsulating structure of the present invention does not form packing colloid;
Fig. 3 B is the vertical view that encapsulating structure of the present invention does not form packing colloid.
Main element symbol description
Encapsulating structure 1,2
Copper base 10
First surface 10a, 20a
Second surface 10b, 20b
Patterning photoresist layer 110
Resistance layer 111
Storage tank 12a
Groove 12b
The first metal layer 120a
Second metal level 120b
Semiconductor chip 13,23
Electronic pads 130,230
Wire 14,24
Mucigel 15
Convex contact 16
Packing colloid 17,27
Dielectric layer 20
Metal level 200
Perforation 201
Strengthening layer 21a
Opening 210a
Line layer 21b
Wire pad 210
Plant ball pad 211
First welding resisting layer 22a
Second welding resisting layer 22b
First perforate 220a
Second perforate 220b
Acting surface 23a
Non-active face 23b
Surface-treated layer 25
Soldered ball 26
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is described in further detail.
Refer to shown in Fig. 2 A to Fig. 2 E, this is the cutaway view of wherein a kind of method for making of encapsulating structure 2 provided by the present invention.
As shown in Figure 2 A, encapsulating structure 2 provided by the invention comprises a dielectric layer 20, has relative first surface 20a and second surface 20b, and has strengthening layer 21a and metal level 200 respectively on first and second surperficial 20a, 20b of this dielectric layer 20.Wherein, the material forming this strengthening layer 21a is metal material, such as: copper.
As shown in Figure 2 B, this is patterning process, line layer 21b is formed to make this metal level 200, and this line layer 21b there is multiple wire pad 210 and be electrically connected this wire pad 210 plant ball pad 211, and formed multiple to should the opening 210a of wire pad 210 on this strengthening layer 21a, to expose outside the part first surface 20a of this dielectric layer 20.
As shown in Figure 2 C, formation first welding resisting layer 22a on the first surface 20a and strengthening layer 21a of this dielectric layer 20, and on the second surface 20b and line layer 21b of this dielectric layer 20 formation second welding resisting layer 22b; And formed multiple to opening 210a and size being less than the first perforate 220a of this opening 210a, to expose outside the part first surface 20a of this dielectric layer 20 on this first welding resisting layer 22a.On this second welding resisting layer 22b, formation is multiple again exposes the second perforate 220b that this plants ball pad 211.
As shown in Figure 2 D, in this first perforate 220a, the perforation 201 running through this dielectric layer 20 is formed, to expose outside described wire pad 210.
As shown in Figure 2 E, in conjunction with semiconductor chip 23 on this first welding resisting layer 22a, and this semiconductor chip 23 by wire 24 through this perforation 201 to be electrically connected described wire pad 210, again on this first welding resisting layer 22a, the first perforate 220a and perforation 201 in form packing colloid 27, to cover semiconductor chip 23, wire 24 and described wire pad 210; Finally, can plant in conjunction with soldered ball 26 on ball pad 211, for being electrically connected to printed circuit board (PCB) in this second perforate 220b.
But, before this wire 24 of formation with soldered ball 26, and can plant on ball pad 211 and form surface-treated layer 25 prior to this wire pad 210, and the material forming this surface-treated layer 25 is selected from by electronickelling/gold, chemical nickel plating/gold, changes nickel and soak gold (ENIG), change nickel palladium and soak the group that gold (ENEPIG), chemical plating stannum (ImmersionTin) and organic solderability preservative (OSP) form.
In encapsulating structure 2 of the present invention, because the surface of this strengthening layer 21a except opening 210a is not damaged, so the first welding resisting layer 22a be formed on this strengthening layer 21a keeps smooth.Therefore, when this semiconductor chip 23 is placed on this first welding resisting layer 22a, the steady problem with offseting of the prior art can be avoided.
And, do not destroy this wire pad 210 surface because this perforation 201 only runs through this dielectric layer 20, so this wire pad 210 surface keeps smooth; And this perforation 201 is because of dielectric layer 20 consistency of thickness, does not need long-time corrosion, the problem that the metal level of external salient point of the prior art is impaired can be avoided.
From the above, encapsulating structure 2 of the present invention comprises: have the dielectric layer 20 of relative first and second surperficial 20a, 20b, the first welding resisting layer 22a on the strengthening layer 21a be located on the first surface 20a of this dielectric layer 20, the line layer 21b be located on the second surface 20b of this dielectric layer 20, the first surface 20a being located at this dielectric layer 20 and strengthening layer 21a, the second welding resisting layer 22b on the second surface 20b being located at this dielectric layer 20 and line layer 21b and the semiconductor chip 23 be located on this first welding resisting layer 22a.
Described dielectric layer 20 has multiple perforation 201 running through this first and second surperficial 20a, 20b.
Described strengthening layer 21a is in order to support and to strengthen structure.
Described line layer 21b have multiple expose to described perforation 201 wire pad 210 and be electrically connected this wire pad 210 plant ball pad 211.
The first described welding resisting layer 22a formed multiple to should bore a hole 201 the first perforate 220a, expose to described first perforate 220a to make described wire pad 211.
The second described welding resisting layer 22b forms multiple second perforate 220b, exposes to described second perforate 220b to plant ball pad 211 described in making.
Described semiconductor chip 23 has relative acting surface 23a and non-active face 23b, and this acting surface 23a has multiple electronic pads 230 to be electrically connected the wire pad exposing to described perforation by wire 24, and this non-active face 23b is bonded on this first welding resisting layer 22a.
Described encapsulating structure 2 also comprises surface-treated layer 25, be located at this wire pad 210 and plant on ball pad 211, and the material forming this surface-treated layer 25 is selected from by electronickelling/gold, chemical nickel plating/gold, changes the group that nickel soaks gold (ENIG), change nickel palladium soaks gold (ENEPIG), chemical plating stannum (Immersion Tin) and organic solderability preservative (OSP) forms.
Described encapsulating structure 2 also comprises soldered ball 26, is located at planting on ball pad 211 in this second perforate 220b.
Described encapsulating structure 2 also comprises packing colloid 27, be located on this first welding resisting layer 22a, the first perforate 220a and perforation 201 in, to cover semiconductor chip 23, wire 24 and described wire pad 210.
In sum, encapsulating structure of the present invention is not damaged because of the surface of this strengthening layer, so the first welding resisting layer formed thereon keeps smooth.Therefore, when this semiconductor chip is placed on this first welding resisting layer, this semiconductor chip can held stationary and position not offset, and is beneficial to connecing of wire and puts and promote the quality of electric connection.
And, because the perforation run through does not destroy this wire pad surface, so this wire pad surface keeps smooth; And this perforation because of medium thickness consistent, do not need long-time corrosion, and cause this wire pad impaired, be beneficial to electrically conduct and promote the quality of electric connection.
The foregoing is only better possible embodiments of the present invention, non-ly therefore limit to protection scope of the present invention, therefore the equivalence techniques change that all utilization the present invention do, be all contained in protection scope of the present invention.
Claims (7)
1. there is an encapsulating structure for individual layer circuit, it is characterized in that, comprising:
Dielectric layer, has relative first surface and second surface, and has multiple perforation running through this first and second surface;
Strengthening layer, is located on the first surface of this dielectric layer, and this strengthening layer is in order to support and to strengthen structure;
Line layer, is located on the second surface of this dielectric layer, and this line layer have multiple expose to described perforation wire pad and be electrically connected this wire pad plant ball pad;
First welding resisting layer, on the first surface being located at this dielectric layer and strengthening layer, and this first welding resisting layer forms multiple first perforate, exposes to described first perforate to make described wire pad;
Second welding resisting layer, on the second surface being located at this dielectric layer and line layer, and this second welding resisting layer forms multiple second perforate, exposes to described second perforate to plant ball pad described in making; And
Semiconductor chip, is located on this first welding resisting layer, and this semiconductor chip is electrically connected the wire pad exposing to described perforation by wire.
2. there is the encapsulating structure of individual layer circuit as claimed in claim 1, it is characterized in that, this semiconductor chip has relative acting surface and non-active face, and this acting surface has the electronic pads of the described wire of multiple electric connection, and this non-active face is bonded on this first welding resisting layer.
3. there is the encapsulating structure of individual layer circuit as claimed in claim 1, it is characterized in that, also comprise surface-treated layer, be located at this wire pad and plant on ball pad.
4. there is the encapsulating structure of individual layer circuit as claimed in claim 3, it is characterized in that, the material forming this surface-treated layer is selected from by electronickelling/gold, chemical nickel plating/gold, changes the group that nickel leaching is golden, change nickel palladium leaching gold, chemical plating stannum and organic solderability preservative form.
5. the encapsulating structure with individual layer circuit as described in claim 1 or 3, is characterized in that, also comprise soldered ball, is located at planting on ball pad in this second perforate.
6. the encapsulating structure with individual layer circuit as described in claim 1 or 3, is characterized in that, also comprise packing colloid, be located on this first welding resisting layer, the first perforate and perforation in, to cover semiconductor chip, wire and described wire pad.
7. there is the encapsulating structure of individual layer circuit as claimed in claim 5, it is characterized in that, also comprise packing colloid, be located on this first welding resisting layer, the first perforate and perforation in, to cover semiconductor chip, wire and described wire pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110078203.9A CN102693948B (en) | 2011-03-24 | 2011-03-24 | Packing structure with monolayer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110078203.9A CN102693948B (en) | 2011-03-24 | 2011-03-24 | Packing structure with monolayer circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102693948A CN102693948A (en) | 2012-09-26 |
| CN102693948B true CN102693948B (en) | 2015-03-04 |
Family
ID=46859305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110078203.9A Expired - Fee Related CN102693948B (en) | 2011-03-24 | 2011-03-24 | Packing structure with monolayer circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN102693948B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI608579B (en) * | 2015-07-17 | 2017-12-11 | 矽品精密工業股份有限公司 | Semiconductor structure and method of manufacture thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1392598A (en) * | 2001-06-19 | 2003-01-22 | 三洋电机株式会社 | Method for producing circuit device |
| CN101515574A (en) * | 2008-02-18 | 2009-08-26 | 旭德科技股份有限公司 | Chip package substrate, chip package body, and method for manufacturing chip package body |
| CN101887879A (en) * | 2009-05-13 | 2010-11-17 | 日月光半导体制造股份有限公司 | Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7985980B2 (en) * | 2007-10-31 | 2011-07-26 | Sharp Kabushiki Kaisha | Chip-type LED and method for manufacturing the same |
-
2011
- 2011-03-24 CN CN201110078203.9A patent/CN102693948B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1392598A (en) * | 2001-06-19 | 2003-01-22 | 三洋电机株式会社 | Method for producing circuit device |
| CN101515574A (en) * | 2008-02-18 | 2009-08-26 | 旭德科技股份有限公司 | Chip package substrate, chip package body, and method for manufacturing chip package body |
| CN101887879A (en) * | 2009-05-13 | 2010-11-17 | 日月光半导体制造股份有限公司 | Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102693948A (en) | 2012-09-26 |
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