CN102683406A - GaN-based MS grid enhancement type high electron mobility transistor and manufacture method thereof - Google Patents
GaN-based MS grid enhancement type high electron mobility transistor and manufacture method thereof Download PDFInfo
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Abstract
The invention discloses a GaN-based MS grid enhancement type high electron mobility transistor and a manufacture method thereof which mainly resolve the problems of low current density and poor reliability of a GaN-based enhancement type device. The structure of the device is that a transition layer (2) and a GaN main buffer layer (3) are sequentially arranged on a lining (1), a groove (4) is etched in the middle of the GaN main buffer layer, an AlGaN main barrier layer (5) is respectively arranged above the GaN mian buffer layer (3) on two sides of the groove, and a GaN auxiliary buffer layer (6) and an AlGaN auxiliary barrier layer (7) are sequentially arranged on the inner wall of the groove and the surface of the AlGaN main barrier layer (5) on two sides of the groove. A source electrode (8), a drain electrode (9), a grid electrode (11) and a medium layer (10) are arranged on the AlGaN secondary barrier layer (7). The source electrode (8) and the drain electrode (9) are respectively located on two sides above the AlGaN auxiliary barrier layer (7), the grid electrode (11) is located in the middle above the AlGaN auxiliary barrier layer (7), and the medium layer (10) is distributed on an area outside the source electrode, the drain electrode and the grid electrode. The transistor has the advantages of being good in enhancement type characteristic, high in current density, high in breakdown voltage, simple and mature in manufacture process and high in reliability, thereby being capable of being used in high temperature switch devices and digital circuits.
Description
Technical field
The invention belongs to microelectronics technology, relate to semi-conducting material, device and manufacture craft thereof.A kind of specifically MS grid enhancement type high electron mobility transistor and manufacture method of GaN base can be used in high temperature high power application scenario and the digital circuit elementary cell.
Background technology
Along with the development of modern weapons equipment and Aero-Space, nuclear energy, the communication technology, automotive electronics, Switching Power Supply, to the demands for higher performance of semiconductor device.Typical case's representative as semiconductor material with wide forbidden band; Characteristics such as the GaN sill has that energy gap is big, the electronics saturation drift velocity high, critical disruptive field intensity is high, thermal conductivity is high, good stability, corrosion-resistant, radioresistance can be used for making high temperature, high frequency and high-power electronic device.In addition, GaN also has good characteristic electron, can form the AlGaN/GaN heterostructure of modulation doping with AlGaN, and this structure at room temperature can obtain to be higher than 1500cm
2The electron mobility of/Vs, and up to 3 * 10
7The peak value velocity of electrons and 2 * 10 of cm/s
7The saturated electrons speed of cm/s, and obtain the two-dimensional electron gas density higher than second generation compound semiconductor heterostructure, being described as is the ideal material of development microwave power device.Therefore, the high electron mobility transistor (HEMT) based on the AlGaN/GaN heterojunction has extraordinary application prospect aspect the microwave high power device.
The development of the growth of AlGaN/GaN heterojunction material and AlGaN/GaN HEMT device is all the time in occupation of the main status of GaN electronic device research.Yet the major part work to the research of GaN base electron device concentrates on depletion-mode AlGaN/GaN HEMT device for over ten years; This is because the existence of strong polarization charge in the AlGaN/GaN heterostructure; Make the enhancement device of making based on GaN become very difficult, so the research of high-performance AlGaN/GaN enhancement mode HEMT have very important significance.At first; It is the ideal material of development microwave power device that the GaN sill is described as; And enhancement device in circuit such as microwave power amplifier and low noise amplifier owing to reduced negative voltage source; Thereby greatly reduce the complexity and the cost of circuit, and AlGaN/GaN enhancement mode HEMT device has good circuit compatibility property at microwave high power device and circuit; Simultaneously, the development of enhancement device makes the digital circuit of the integrated depletion type/enhancement device of monolithic become possibility; And in the power application facet of opening the light, AlGaN/GaN enhancement mode HEMT also has very big application prospect; Thereby the research of high-performance AlGaN/GaN enhancement mode HEMT device has obtained great attention.
At present, no matter be domestic or in the world, the reports about AlGaN/GaN enhancement mode HEMT are arranged all much.At present report mainly contain following several kinds technological:
1.F ion implantation technique; Promptly based on the plasma injection technique of fluoride CF4, people such as the Yong Cai of Hong Kong University of Science and Thchnology have successfully developed the enhancement mode HEMT device based on the F ion implantation technique, and this device is through injecting the F ion in the AlGaN barrier layer under AlGaN/GaN HEMT grid; Because the strong elecrtonegativity of F ion; F ion in the barrier layer can provide stable negative electrical charge, thereby can effectively exhaust the strong two-dimensional electron gas of channel region, when the F number of ions in the AlGaN barrier layer reaches some; The two-dimensional electron gas at grid lower channel place exhausts fully, thereby realizes enhancement mode HEMT device.But the F injection technique inevitably can be introduced the damage of material, and the controllability of device threshold voltage is not high.This device at room temperature the thin layer carrier concentration up to 1.3 * 10
13Cm
-2, mobility is 1000cm
2/ Vs, threshold voltage reaches 0.9V, and maximum drain current reaches 310mA/mm.Referring to document Yong Cai; Yugang Zhou, Kevin J.Chen and Kei May Lau, " High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment "; IEEE Electron Device Lett; Vol.26, No.7, JULY 2005.
2. nonpolar or semi-polarity GaN material is realized enhancement device; People such as Masayuki Kuroda successfully use a face (1120) n-AlGaN/GaNHEMT on r face (1102) sapphire to realize the enhancing of device; Because nonpolar or semi-polarity material is owing to lack polarity effect; Therefore its two-dimensional electron gas is very little even do not have, so have enhanced characteristic based on the AlGaN/GaN HEMT device of nonpolar or semi-polarity material.The threshold voltage of its report is-0.5V, mixes concentration through reduction and can further increase device threshold voltage, but its device property and bad, its electron mobility has only 5.14cm
2/ Vs, room temperature lower block resistance is very big.And its grid leak TV university is little to have reached 1.1 * 10 when Vgs=-10V
-5A/mm.Referring to document Masayuki Kuroda, Hidetoshi Ishida, Tetsuzo Ueda; And Tsuyoshi Tanaka; " Nonpolar (11-20) plane AlGaN/GaN heterojunction field effect transistors on (1-102) plane sapphire ", Journal of Aplied Phisics, Vol.102; No.9, November2007.
3. thin barrier layer technology; 1996; People such as M.Asif Khan have at first realized AlGaN/GaN enhancement mode HEMT device with the thin barrier layer technology of AlGaN of 10nm, and thin barrier layer AlGaN/GaN enhancement mode HEMT device is owing to the barrier layer thickness attenuate, and its polarity effect weakens; The raceway groove place two-dimensional electron gas that is caused by polarity effect reduces, thereby realizes moving to right of device threshold voltage.But the result that they obtain is unsatisfactory, and its peak value mutual conductance has only 23mS/mm.Referring to document M.Asif Khan, Q.Chen, C.J.Sun; J.W.Yang; And M.Blasingame, " Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors " Appl.Phys.Lett, Vol.68; No.4, January 1996.
4. groove gate technique, people such as W.B.Lanford utilize the groove gate technique to make the enhancement device that threshold voltage reaches 0.47V through MOCVD, and this device architecture comprises from bottom to top: the SiC substrate; Nucleating layer, the GaN that 2um is thick, the AlGaN that 3nm is thick; The n-AlGaN that 10nm is thick, the AlGaN that 10nm is thick.This technology is passed through the barrier layer etching certain depth under the grid; Make the attenuation of grid lower barrierlayer, 2DEG concentration reduces under the grid thereby make, and the carrier concentration of source-drain area keeps higher value constant; So both can realize the enhanced characteristic of device, can guarantee certain current density again.Its epitaxial growth of enhancement device that utilizes the groove gate technique to realize is controlled easily, but its control is relatively poor, and etching process can form damage.Referring to document W.B.Lanford, T.Tanaka, Y.Otoki and I.Adesida; " Recessed-gate enhancement-mode GaN HEMT with high threshold voltage "; Electronics Letrers, Vol.41, No.7 March 2005.
In sum, AlGaN/GaN HEMT enhancement device mainly adopts based on the groove gate technique with based on the formation of fluorine ion injection technique in the world at present, and all there is following deficiency in it:
(1) increase of threshold voltage is a cost to reduce current density often, is difficult to the enhancement device of realizing that high threshold voltage and high current density coexist;
(2) the groove gate technique still is that the fluorine ion injection technique all can cause damage to material; Though annealedly can eliminate certain damage; But residual damage still can impact device performance and reliability, and the repeatability of present this technology is also not high simultaneously;
(3) technology difficulty of the short channel device of the short grid length of making is bigger, causes device reliability low.
Summary of the invention
The objective of the invention is to overcome the defective of above-mentioned prior art, propose a kind of MS grid enhancement type high electron mobility transistor and manufacture method of GaN base,, reduce technology difficulty, improve the reliability of device, satisfy practical application to increase the current density of device.
For realizing above-mentioned purpose, the structure of HEMT provided by the invention comprises from bottom to top: comprise from bottom to top: substrate, transition zone and GaN host buffer layer is characterized in that:
The centre of GaN host buffer layer is etched with groove; The bottom surface of this groove is 0001 polar surface; The groove side is non-0001, and the GaN host buffer layer top of groove both sides is AlGaN master's barrier layer, forms main two-dimensional electron gas 2DEG layer on GaN host buffer layer and the AlGaN master's barrier layer interface;
AlGaN master's barrier layer surface of on the bottom surface of groove and the side surface direction and groove both sides is provided with GaN resilient coating and AlGaN barrier layer successively; Form time two-dimensional electron gas 2DEG layer on GaN the resilient coating of groove floor top and the interface of AlGaN barrier layer; GaN resilient coating and AlGaN barrier layer of groove side surface direction top are non-0001 AlGaN/GaN heterojunction, and this heterojunction boundary place forms the two-dimensional electron gas 2DEG layer of enhancement mode; Form auxilliary two-dimensional electron gas 2DEG layer on GaN the resilient coating of groove both sides and the interface of AlGaN barrier layer;
Going up of said AlGaN barrier layer is source class, leakage level, grid and dielectric layer; This source class lays respectively at the both sides above the barrier layer AlGaN time with the leakage level; Grid is positioned at the centre of AlGaN barrier layer top, and dielectric layer is distributed in source class, leaks the zone outside level, the grid level;
The two-dimensional electron gas layer of described auxilliary two-dimensional electron gas 2DEG layer, enhancement mode and inferior two-dimensional electron gas 2DEG layer, through electron stream through forming first conducting channel; The two-dimensional electron gas 2DEG layer of described main two-dimensional electron gas 2DEG layer, enhancement mode and inferior two-dimensional electron gas 2DEG layer through forming second conducting channel, make the zone of groove both sides be the double channel structure through electron stream.
The horizontal level of said two-dimensional electron gas 2DEG layer is lower than the horizontal level of main two-dimensional electron gas 2DEG layer.
Said AlGaN master's barrier layer and AlGaN barrier layer are that doping content is 10 * 10
19Cm
-3N type AlGaN.
For realizing above-mentioned purpose, the MS grid enhancement type high electron mobility transistor and the manufacture method of GaN base of the present invention comprise the steps:
1) in reative cell, substrate surface is carried out preliminary treatment;
2) epitaxial thickness is the GaN host buffer layer of 1.2um-3.2um on substrate;
3) Al that extension N type mixes on the GaN epitaxial loayer
xGa
1-xN master's barrier layer forms AlGaN/GaN heterogenous junction epitaxy layer, this Al on substrate
xGa
1-xN master's barrier layer thickness is 15nm-38nm, and 0.18≤x≤0.4;
4) photoetching AlGaN/GaN heterogenous junction epitaxy layer, and adopt reactive ion etching RIE method, etching shape is grown into 0.5um on the AlGaN/GaN epitaxial loayer, and the degree of depth is the groove of 40nm-160nm;
5) be GaN the resilient coating of 24nm-120nm with the epitaxial loayer after the etching through metal organic chemical vapor deposition MOCVD reative cell secondary epitaxy thickness;
6) adopting MOCVD technology epitaxial thickness on the GaN of secondary epitaxy layer is the Al of 15nm-38nm
xGa
1-xN barrier layer, and 0.18≤x≤0.4;
7) at the Al of secondary epitaxy
xGa
1-xOn N the barrier layer, adopting plasma-reinforced chemical vapor deposition PECVD method deposition thickness is the dielectric layer of 1nm-20nm;
8) on dielectric layer, make source, leakage, gate region by lithography, and etching is removed the dielectric layer under the window, acquisition source, leakage, grid window;
9) make source, drain region by lithography, adopt the metal of electron beam evaporation technique deposit ohmic contact, the row metal of going forward side by side is peeled off;
10) metal ohmic contact is annealed formation source, drain contact electrode;
11) make gate region by lithography, and adopt electron beam evaporation technique deposit gate metal, after peeling off, form schottky gate electrode;
12) photoetching has formed the epitaxial wafer of source, leakage, grid, obtains the thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, accomplishes element manufacturing.
Said step 2) process conditions of extension GaN host buffer layer are in: temperature is 1050 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm, and ammonia flow is 6000sccm, and the gallium source flux is 220sccm.
The process conditions of GaN resilient coating of secondary epitaxy are in the said step 5): temperature is 1050 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm, and ammonia flow is 3000sccm, and the gallium source flux is 150sccm.
Use the process conditions of plasma-reinforced chemical vapor deposition PECVD method dielectric layer deposited to be in the said step 7): ammonia flow is 2.5sccm, and nitrogen flow is 900sccm, and silane flow rate is 200sccm, and temperature is 300 ℃, and pressure is 900mT, and power is 25W.
The present invention has following advantage:
1. the present invention is owing to be etched with groove in the middle of GaN host buffer layer; And the bottom surface of groove is 0001 polar surface; The groove side is non-0001; Therefore along non-0001 GaN the resilient coating of extension on the groove side surface direction and the AlGaN/GaN heterojunction structure of AlGaN barrier layer formation, this structure reduces even has eliminated polarity effect, and the two-dimensional electron gas that this heterojunction boundary place is formed is very low; Even do not have two-dimensional electron gas, make recess sidewall heterojunction boundary place form the two-dimensional electron gas 2DEG layer of enhancement mode; Simultaneously owing on the GaN of groove both sides host buffer layer and AlGaN master's barrier layer interface, form main two-dimensional electron gas 2DEG layer; On GaN resilient coating of groove both sides and AlGaN barrier layer interface, form auxilliary two-dimensional electron gas 2DEG layer; On GaN time on groove floor resilient coating and AlGaN barrier layer interface, form time two-dimensional electron gas 2DEG layer, thereby form first conducting channel during through the two-dimensional electron gas 2DEG layer of assisting two-dimensional electron gas 2DEG layer, enhancement mode and inferior two-dimensional electron gas 2DEG layer when electron stream; When electron stream forms second conducting channel through the two-dimensional electron gas 2DEG layer and the inferior two-dimensional electron gas 2DEG layer of main two-dimensional electron gas 2DEG layer, enhancement mode, make the present invention have the double channel conductive mechanism.
2. the present invention is for first conducting channel; Have only when grid applies positive voltage to a certain degree; The inferior resilient coating of groove side could form the two-dimensional electron gas raceway groove with the two-dimensional electron gas 2DEG layer of the enhancement mode at time barrier layer interface; Thereby realize the conducting of first conductive channel, promptly realized the enhanced characteristic of device.
For second conductive channel; Because the inferior GaN resilient coating of groove side diauxic growth is equivalent to one deck separator; Have only the grid of working as to apply certain positive voltage; In this GaN separator, form strong horizontal drift electric field, can realize conducting, thereby form electric current at this drift field effect lower channel electronics.
Existing AlGaN/GaN HEMT device is because the existence of high concentration two-dimensional electron gas 2DEG, grid voltage be zero in addition during lower negative value device all be conducting state, thereby be difficult to realize the enhancing of device; And HEMT of the present invention is the conducting of first conducting channel or the grid positive voltage that the conducting of second conducting channel all need be certain, so the present invention can realize good enhanced characteristic.
3. the present invention is because the zone of the groove both sides of device is the double channel structure; And the AlGaN barrier layer of second conducting channel top adopts N type even N+ type to mix; Not only can reduce the ohmic contact resistance of device greatly, and greatly reduce the series resistance of device source electrode and drain electrode; Simultaneously owing to introduce the conductive mechanism of second conducting channel; Electron stream is shortened through the distance of the two-dimensional electron gas 2DEG of the enhancement mode of recess sidewall layer greatly; Avoided the low restriction of two-dimensional electron gas 2DEG layer conductivity of the enhancement mode of recess sidewall to electric current; Significantly improved the current density of device, made the present invention have the high current density characteristic; In addition because the power line that rises from gate electrode can end at first conducting channel, N type AlGaN master barrier layer, AlGaN barrier layer of N type and second conductive channel; Power line between grid and raceway groove is disperseed; Electric field strength weakens; Thereby improved the puncture voltage of device, made the present invention have high-breakdown-voltage.
4. the processing step in the device manufacture method of the present invention all is relatively ripe both at home and abroad at present, and technological process is also simple relatively, and cost is low, and the depletion-mode AlGaN/GaN HEMT device preparation technology with ripe is compatible fully.In addition, the present invention has adopted reactive ion etching method to carry out etching, and in follow-up high temperature secondary growth, the surface damage that can form etching is to a certain extent repaired, to reduce the influence of etching injury to device performance and reliability.Compare with groove grid lithographic method commonly used both at home and abroad at present, the more effective material damage of having avoided etching to cause of the present invention's ability, device reliability is higher.
Description of drawings
Fig. 1 is the MS grid enhancement type high electron mobility transistor structure figure of GaN base of the present invention;
Fig. 2 is the MS grid enhancement type high electron mobility transistor process chart that the present invention prepares the GaN base.
Embodiment
With reference to Fig. 1; The MS grid enhancement type high electron mobility transistor of GaN of the present invention base comprises: substrate 1, transition zone 2, GaN host buffer layer 3, groove 4, AlGaN master's barrier layer 5, GaN resilient coating 6, AlGaN barrier layer 7, source class 8, leakage grades 9, dielectric layer 10, grid 11; Substrate 1 top is a transition zone 2; Transition zone 2 tops are GaN host buffer layer 3, and these GaN host buffer layer 3 thickness are 1.2um-3.2um; Groove 4 is etched in the centre of GaN host buffer layer 3, and this groove 4 is long to be 0.5um, and the degree of depth is 40nm-160nm, and the bottom surface of groove 4 is 0001 polar surface, and groove 4 sides are non-0001; The AlGaN master's barrier layer 5 that mixes for the N type in GaN host buffer layer 3 top of groove 4 both sides, the thickness of this AlGaN master's barrier layer 5 is 15nm-38nm, doping content is 10 * 10
19Cm
-3, and 0.18≤x≤0.4; Form main two-dimensional electron gas 2DEG layer 12 on GaN host buffer layer 3 and AlGaN master's barrier layer 5 interfaces; AlGaN master's barrier layer 5 surfaces of on the bottom surface of groove 4 and the side surface direction and groove both sides are GaN resilient coating 6, and the thickness of this GaN time resilient coating 6 is 24nm-120nm; AlGaN the barrier layer 7 that mixes for the N type in GaN resilient coating 6 top, the thickness of this AlGaN time barrier layer 7 is 15nm-38nm, doping content is 10 * 10
19Cm
-3, and 0.18≤x≤0.4; Form time two-dimensional electron gas 2DEG layer 13 on GaN the resilient coating 6 of top, groove 4 bottom surfaces and the interface of AlGaN barrier layer 7, and the horizontal level of this time two-dimensional electron gas 2DEG layer 13 is lower than the horizontal level of main two-dimensional electron gas 2DEG layer (12); Form auxilliary two-dimensional electron gas 2DEG layer 14 on GaN the resilient coating 6 of groove 4 both sides and the interface of AlGaN barrier layer 7; GaN resilient coating 6 on the groove side surface direction is non-0001 AlGaN/GaN heterojunction with AlGaN barrier layer 7, and this heterojunction boundary place forms the two-dimensional electron gas 2DEG layer 15 of enhancement mode; Going up of AlGaN barrier layer 7 is source class 8, leakage level 9, grid 11 and dielectric layer 10; This source class 8 and leakage level 9 lay respectively at the both sides of AlGaN barrier layer 7 tops; Grid 11 is positioned at the centre of AlGaN barrier layer 7 tops; Dielectric layer 10 is distributed in source class, leaks the zone outside level, the grid level, and its thickness is 1nm-20nm; Electron stream is through the two-dimensional electron gas layer 15 of the enhancement mode of inferior two-dimensional electron gas 2DEG layer 13 of the two-dimensional electron gas layer 15 of the enhancement mode of the auxilliary two-dimensional electron gas 2DEG layer 14 in groove left side, groove left side wall, groove floor and groove right side wall, auxilliary two-dimensional electron gas 2DEG layer 14 formation first conducting channel 16 on groove right side; Electron stream makes the zone of groove 4 both sides be the double channel structure through two-dimensional electron gas 2DEG layer 15, inferior two-dimensional electron gas 2DEG layer 13 of groove floor and the two-dimensional electron gas layer 15 of groove right side wall enhancement mode of the enhancement mode of the main two-dimensional electron gas 2DEG layer 12 in groove left side, groove left side wall, main two-dimensional electron gas 2DEG layer 12 formation second conducting channel 17 on groove right side.
With reference to Fig. 2, the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base of the present invention provides following three kinds of embodiment.
Embodiment 1
Being made into GaN host buffer layer thickness is 1.2um, Al
0.4Ga
0.6N master's barrier layer thickness is 15nm, and the recess etched degree of depth is 40nm, and GaN buffer layer thickness is 24nm, Al
0.4Ga
0.6N barrier layer thickness is 15nm, and gate dielectric layer thickness is the MS grid enhancement type high electron mobility transistor of the GaN base of 1nm, the steps include:
Step 1, the heat treatment of substrate and surfaces nitrided:
Sapphire Substrate is placed metal organic chemical vapor deposition MOCVD reative cell, the vacuum degree of reative cell is evacuated to 1 * 10
-2Under the Torr, be that the mixed gas protected of the hydrogen of 1500sccm and ammonia that flow is 2000sccm heat-treated with surfaces nitrided Sapphire Substrate down at flow, heating-up temperature is 1050 ℃, and pressure is 20Torr.
Step 2, extension AlN transition zone:
Adopt the MOCVD technology; In temperature is 1050 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm; Ammonia flow is 2000sccm; The aluminium source flux is under the process conditions of 30sccm, through heat treatment and surfaces nitrided after on the Sapphire Substrate epitaxial thickness be the AlN transition zone of 150nm, like Fig. 2 (a).
Step 3, extension GaN host buffer layer:
Adopting the MOCVD technology, is 1050 ℃ in temperature, and pressure is 20Torr; Hydrogen flowing quantity is 1500sccm, and ammonia flow is 6000sccm, and the gallium source flux is under the process conditions of 220sccm; Epitaxial thickness is the GaN host buffer layer of 1.2um on the AlN transition zone, like Fig. 2 (b).
Step 4, the Al that extension N type mixes
0.4Ga
0.6N master's barrier layer:
Adopting the MOCVD technology, is 920 ℃ in temperature, and pressure is 40Torr; Hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm; The gallium source flux is under the process conditions of 40sccm, and epitaxial thickness is the N type doped with Al of 15nm on the host buffer layer
0.4Ga
0.6N master's barrier layer is through feeding silane SiH in growth course
4Realize that doping content is 10 * 10
19Cm
-3The N type mix, on the AlN transition zone, formed the AlGaN/GaN heterojunction like this, the place has formed two-dimensional electron gas 2DEG, the epitaxial slice structure of formation such as Fig. 2 (c) in the matter junction interface.
Step 5, deposit SiO
2Layer mask layer:
After epitaxial wafer cleaned, adopting electron beam evaporation equipment deposition thickness on epitaxial wafer was the SiO of 150nm
2Layer is like Fig. 2 (d), this SiO
2Layer can form the bilayer mask figure that shields jointly on the epitaxial wafer surface with photoresist, more helps the not protection on etch areas surface.
Step 6, photoetching and etching form groove structure:
In deposit SiO
2On the epitaxial wafer surface of layer, through positive-glue removing, soft baking, exposure and the required notch window of formation etching of developing, and adopt reactive ion etching RIE method, at chlorine Cl
2Flow is 15sccm, and power is 200W, and pressure is etching epitaxial wafer under the process conditions of 10mT, and etching depth is 40nm, forms groove structure, like Fig. 2 (e).
Step 7 is removed photoresist and is removed SiO
2Mask layer:
Remove after the etching remaining positive glue on the epitaxial wafer with acetone soln, then the SiO of deposit in the corrosion step five in HF solution
2Mask cleans with ultra-pure water at last and dries up with nitrogen.
Step 8, the heat treatment of epitaxial wafer and surfaces nitrided:
The vacuum degree of reative cell is evacuated to 1 * 10
-2Under the Torr, be that the mixed gas protected of the hydrogen of 1500sccm and ammonia that flow is 2000sccm heat-treated the epitaxial wafer after cleaning down at flow, heating-up temperature is 1000 ℃, and pressure is 20Torr.
Step 9, GaN resilient coating of secondary epitaxy:
Utilizing the MOCVD technology, is 1050 ℃ in temperature, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm, and ammonia flow is 3000sccm, and the gallium source flux is under the process conditions of 150sccm, and epitaxial thickness is GaN the resilient coating of 24nm on epitaxial wafer, like Fig. 2 (f).
Step 10, secondary epitaxy Al
0.4Ga
0.6N barrier layer:
Utilize the MOCVD technology, adopting temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm, and the gallium source flux is the process conditions of 40sccm, and in growth course, feeds silane SiH
4Realize that doping content is 10 * 10
19Cm
-3The N type mix, extension formation thickness is the N type doped with Al of 15nm on GaN resilient coating
0.4Ga
0.6N barrier layer, like this on groove floor with the Al of groove both sides
0.4Ga
0.6N barrier layer and GaN resilient coating have formed the AlGaN/GaN heterojunction, and this heterojunction boundary place is formed with two-dimensional electron gas 2DEG, delay epitaxial slice structure such as Fig. 2 (g) of formation outward.
Step 11, deposit SiN dielectric layer:
Utilizing plasma-reinforced chemical vapor deposition PECVD method, is 2.5sccm at ammonia flow, and nitrogen flow is 900sccm; Silane flow rate is 200sccm, and temperature is 300 ℃, and pressure is 900mT; Power is under the process conditions of 25W; Deposition thickness is the SiN dielectric layer of 1nm, and this dielectric layer covers whole groove, like Fig. 2 (h).
Step 12 makes source, ornamental perforated window mouth by lithography:
12a) through positive-glue removing, soft baking, exposure and development, the photoetching window of formation source, leakage, grid, and adopt wet etching method to remove the SiN dielectric film under source, leakage, the gate region.
12a) epitaxial wafer of having removed the SiN dielectric film under source, leakage, the gate region is carried out positive-glue removing, soft baking, exposure and development acquisition source, drain region window; And utilize plasma degumming machine to remove the photoresist thin layer that window area does not develop clean, to improve the rate of finished products of metal-stripping.
Step 13, the evaporation metal ohmic contact:
Adopt the electron beam evaporation instrument, in vacuum degree less than 2.0 * 10
-6Pa, power bracket is 600W, and evaporation rate is not more than under the process conditions of 3 dust/seconds evaporates Ti, Al, Ni, four layers of metal ohmic contact of Au, and the thickness of Ti, Al, Ni, Au is respectively 30nm, 180nm, 40nm, 60nm.
Step 14, metal-stripping also carries out ohmic contact annealing:
The epitaxial wafer that at first will evaporate metal ohmic contact soaks 20min in acetone soln; Carry out ultrasonic cleaning then; Then the ultra-pure water flushing dries up with nitrogen, and realizing peeling off of metal, last ohmic contact of in nitrogen atmosphere, under 850 ℃ the temperature, carrying out 30s is annealed; Cheng Yuan, drain contact electrode are like Fig. 2 (i).
Step 15 makes the grid window by lithography:
On the epitaxial wafer after the annealing, carry out positive-glue removing, soft baking, exposure and develop obtaining the grid window.
Step 10 six, evaporation grid metal:
Adopt the electron beam evaporation instrument, deposit Ni, Au double layer of metal, the thickness of Ni, Au is respectively 30nm, 200nm; Subsequently device is immersed in and carries out metal-stripping in the stripper, then wash 2min with ultra-pure water, last nitrogen dries up; The final gate electrode that obtains is like Fig. 2 (j).
Step 10 seven, accomplish element manufacturing:
Photoetching has formed the epitaxial wafer of source, leakage, grid, obtains the thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, accomplishes element manufacturing as shown in Figure 1.
Embodiment 2
Being made into GaN host buffer layer thickness is 2.5um, Al
0.3Ga
0.7N master's barrier layer thickness is 28nm, and the recess etched degree of depth is 100nm, and GaN buffer layer thickness is 70nm, Al
0.3Ga
0.7N barrier layer thickness is 28nm, and gate dielectric layer thickness is the MS grid enhancement type high electron mobility transistor of the GaN base of 10nm, the steps include:
Step 1 is identical with the step 1 of embodiment 1.
Step 2 is identical with the step 2 of embodiment 1.
Step 3, adopting MOCVD technology epitaxial thickness on the AlN transition zone is the GaN host buffer layer of 2.5um, like Fig. 2 (b); The process conditions that extension adopts are: temperature is 1050 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm; Ammonia flow is 6000sccm, and the gallium source flux is 220sccm.
Step 4, adopting MOCVD technology epitaxial thickness on the host buffer layer is the N type doped with Al of 28nm
0.3Ga
0.7N master's barrier layer has formed the AlGaN/GaN heterojunction like this on the AlN transition zone, the place has formed two-dimensional electron gas 2DEG in the matter junction interface; Epitaxial slice structure such as Fig. 2 (c) of forming, the process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr; Hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm; The gallium source flux is 40sccm, and through in growth course, feeding silane SiH
4Realize that doping content is 10 * 10
19Cm
-3The N type mix.
Step 5 is identical with the step 5 of embodiment 1.
Step 6, in deposit SiO
2On the epitaxial wafer surface of layer; Through positive-glue removing, soft baking, exposure and the required notch window of formation etching of developing, and adopt reactive ion etching RIE method etching epitaxial wafer, etching depth is 100nm; Form groove structure such as Fig. 2 (e), the process conditions that etching adopts are: chlorine Cl
2Flow is 15sccm, and power is 200W, and pressure is under the process conditions of 10mT.
Step 7 is identical with the step 7 of embodiment 1.
Step 8 is identical with the step 8 of embodiment 1.
Step 9 is utilized the MOCVD technology, GaN the resilient coating of epitaxial thickness 70nm on epitaxial wafer; Like Fig. 2 (f), the process conditions that extension adopts are: temperature is 1050 ℃, and pressure is 20Torr; Hydrogen flowing quantity is 1500sccm, and ammonia flow is 3000sccm, and the gallium source flux is 150sccm.
Step 10 is utilized MOCVD technology, and extension formation thickness is the N type doped with Al of 28nm on GaN resilient coating
0.3Ga
0.7N barrier layer, like this on groove floor with the Al of groove both sides
0.3Ga
0.7N barrier layer and GaN resilient coating have formed the AlGaN/GaN heterojunction, and this heterojunction boundary place is formed with two-dimensional electron gas 2DEG, delay epitaxial slice structure such as Fig. 2 (g) of formation outward; The process conditions that extension adopts are: temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 6000sccm; Ammonia flow is 5000sccm; The aluminium source flux is 10sccm, and the gallium source flux is 40sccm, and in growth course, feeds silane SiH
4Realize that doping content is 10 * 10
19Cm
-3The N type mix.
Step 11 is utilized plasma-reinforced chemical vapor deposition PECVD method, and deposition thickness is the SiN dielectric layer of 10nm; This dielectric layer covers whole groove, and like Fig. 2 (h), the process conditions that deposit is adopted are: ammonia flow is 2.5sccm; Nitrogen flow is 900sccm, and silane flow rate is 200sccm, and temperature is 300 ℃; Pressure is 900mT, and power is 25W.
Step 12 is identical with the step 12 of embodiment 1.
Step 13 is identical with the step 13 of embodiment 1.
Step 14 is identical with the step 14 of embodiment 1.
Step 15 is identical with the step 15 of embodiment 1.
Step 16, same with the step 10 six phase of embodiment 1.
Step 17 is identical with the step 10 seven of embodiment 1.
Embodiment 3
Being made into GaN host buffer layer thickness is 3.2um, Al
0.18Ga
0.82N master's barrier layer thickness is 38nm, and the recess etched degree of depth is 160nm, and GaN buffer layer thickness is 120nm, Al
0.18Ga
0.82N barrier layer thickness is 38nm, and gate dielectric layer thickness is the MS grid enhancement type high electron mobility transistor of the GaN base of 20nm, the steps include:
Steps A is identical with the step 1 of embodiment 1.
Step B is identical with the step 2 of embodiment 1.
Step C, adopting temperature is 1050 ℃, pressure is 20Torr; Hydrogen flowing quantity is 1500sccm, and ammonia flow is 6000sccm, and the gallium source flux is the process conditions of 220sccm; Through the MOCVD technology, epitaxial thickness is the GaN host buffer layer of 3.2um on the AlN transition zone, like Fig. 2 (b).
Step D, adopting temperature is 920 ℃, pressure is 40Torr; Hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm; The gallium source flux is the process conditions of 40sccm, and through the MOCVD technology, epitaxial thickness is the N type doped with Al of 38nm on the host buffer layer
0.18Ga
0.82N master's barrier layer is through feeding silane SiH in growth course
4Realize that doping content is 10 * 10
19Cm
-3The N type mix, on the AlN transition zone, formed the AlGaN/GaN heterojunction like this, the place has formed two-dimensional electron gas 2DEG, the epitaxial slice structure of formation such as Fig. 2 (c) in the matter junction interface.
Step e is identical with the step 5 of embodiment 1.
Step 6, in deposit SiO
2On the epitaxial wafer surface of layer, through positive-glue removing, soft baking, exposure and the required notch window of formation etching of developing, and adopt reactive ion etching RIE method, at chlorine Cl
2Flow is 15sccm, and power is 200W, and pressure is etching epitaxial wafer under the process conditions of 10mT, and etching depth is 160nm, forms groove structure, like Fig. 2 (e).
Step F is identical with the step 7 of embodiment 1.
Step G is identical with the step 8 of embodiment 1.
Step H is 1050 ℃ in temperature, and pressure is 20Torr; Hydrogen flowing quantity is 1500sccm, and ammonia flow is 3000sccm, and the gallium source flux is under the process conditions of 150sccm; Through the MOCVD technology, GaN the resilient coating of epitaxial thickness 120nm on epitaxial wafer is like Fig. 2 (f).
Step I, adopting temperature is 920 ℃, and pressure is 40Torr, and hydrogen flowing quantity is 6000sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 10sccm, and the gallium source flux is the process conditions of 40sccm, and in growth course, feeds silane SiH
4Realize that doping content is 10 * 10
19Cm
-3The N type mix, utilize the MOCVD technology, extension formation thickness is the N type doped with Al of 38nm on GaN resilient coating
0.18Ga
0.82N barrier layer, like this on groove floor with the Al of groove both sides
0.18Ga
0.82N barrier layer and GaN resilient coating have formed the AlGaN/GaN heterojunction, and this heterojunction boundary place is formed with two-dimensional electron gas 2DEG, delay epitaxial slice structure such as Fig. 2 (g) of formation outward.
Step J is 2.5sccm at ammonia flow, and nitrogen flow is 900sccm; Silane flow rate is 200sccm, and temperature is 300 ℃, and pressure is 900mT; Power is under the process conditions of 25W, utilizes plasma-reinforced chemical vapor deposition PECVD method, and deposition thickness is the SiN dielectric layer of 20nm; This dielectric layer covers whole groove, like Fig. 2 (h).
Step K is identical with the step 12 of embodiment 1.
Step L is identical with the step 13 of embodiment 1.
Step M is identical with the step 14 of embodiment 1.
Step N is identical with the step 15 of embodiment 1.
Step O, same with the step 10 six phase of embodiment 1.
Step P is identical with the step 10 seven of embodiment 1.
The foregoing description several preferred embodiments only of the present invention; Do not constitute any restriction of the present invention; Obviously to those skilled in the art, after having understood content of the present invention and principle, can be under the situation that does not deviate from the principle and scope of the present invention; Carry out various corrections and change on form and the details according to the method for the invention, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Claims (7)
1. the MS grid enhancement type high electron mobility transistor of GaN base, comprise from bottom to top: substrate (1), transition zone (2) and GaN host buffer layer (3) is characterized in that:
The centre of GaN host buffer layer (3) is etched with groove (4); The bottom surface of this groove (4) is 0001 polar surface; Groove (4) side is non-0001; GaN host buffer layer (3) top of groove (4) both sides is AlGaN master's barrier layer (5), forms main two-dimensional electron gas 2DEG layer (12) on GaN host buffer layer (3) and AlGaN master's barrier layer (5) interface;
AlGaN master's barrier layer (5) surface of on the bottom surface of groove (4) and the side surface direction and groove both sides is provided with GaN resilient coating (6) and AlGaN barrier layer (7) successively; Form time two-dimensional electron gas 2DEG layer (13) on GaN the resilient coating (6) of groove floor top and the interface of AlGaN barrier layer (7); GaN resilient coating (6) on the groove side surface direction is non-0001 AlGaN/GaN heterojunction with AlGaN barrier layer (7), and this heterojunction boundary place forms the two-dimensional electron gas 2DEG layer (15) of enhancement mode; Form auxilliary two-dimensional electron gas 2DEG layer (14) on GaN the resilient coating (6) of groove both sides and the interface of AlGaN barrier layer (7);
Said AlGaN barrier layer (7) gone up to source class (8), leaked level (9), grid (11) and dielectric layer (10); This source class (8) and leakage level (9) lay respectively at the both sides of AlGaN barrier layer (7) top; Grid (11) is positioned at the centre of AlGaN barrier layer (7) top, and dielectric layer (10) is distributed in source class, leaks the zone outside level, the grid level;
The two-dimensional electron gas layer (15) of described auxilliary two-dimensional electron gas 2DEG layer (14), enhancement mode and inferior two-dimensional electron gas 2DEG layer (13), through electron stream through forming first conducting channel (16); The two-dimensional electron gas 2DEG layer (15) of described main two-dimensional electron gas 2DEG layer (12), enhancement mode and inferior two-dimensional electron gas 2DEG layer (13) through forming second conducting channel (17), make the zone of groove (4) both sides be the double channel structure through electron stream.
2. enhancement type high electron mobility transistor according to claim 1 is characterized in that, the horizontal level of inferior two-dimensional electron gas 2DEG layer (13) is lower than the horizontal level of main two-dimensional electron gas 2DEG layer (12).
3. enhancement type high electron mobility transistor according to claim 1 is characterized in that, AlGaN master's barrier layer (5) and AlGaN barrier layer (7) are 10 * 10 for doping content
19Cm
-3N type AlGaN.
4. the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base may further comprise the steps:
1) in reative cell, substrate surface is carried out preliminary treatment;
2) epitaxial thickness is the GaN host buffer layer of 1.2um-3.2um on substrate;
3) Al that extension N type mixes on the GaN epitaxial loayer
xGa
L-xN master's barrier layer forms AlGaN/GaN heterogenous junction epitaxy layer, this Al on substrate
xGa
L-xN master's barrier layer thickness is 15nm-38nm, and 0.18≤x≤0.4;
4) photoetching AlGaN/GaN heterogenous junction epitaxy layer, and adopt reactive ion etching RIE method, etching shape is grown into 0.5um on the AlGaN/GaN epitaxial loayer, and the degree of depth is the groove of 40nm-160nm;
5) be GaN the resilient coating of 24nm-120nm with the epitaxial loayer after the etching through metal organic chemical vapor deposition MOCVD reative cell secondary epitaxy thickness;
6) adopting MOCVD technology epitaxial thickness on the GaN of secondary epitaxy layer is the Al of 15nm-38nm
xGa
L-xN barrier layer, and 0.18≤x≤0.4;
7) at the Al of secondary epitaxy
xGa
L-xOn N the barrier layer, adopting plasma-reinforced chemical vapor deposition PECVD method deposition thickness is the dielectric layer of 1nm-20nm;
8) on dielectric layer, make source, leakage, gate region by lithography, and etching is removed the dielectric layer under the window, acquisition source, leakage, grid window;
9) make source, drain region by lithography, adopt the metal of electron beam evaporation technique deposit ohmic contact, the row metal of going forward side by side is peeled off;
10) metal ohmic contact is annealed formation source, drain contact electrode;
11) make gate region by lithography, and adopt electron beam evaporation technique deposit gate metal, after peeling off, form schottky gate electrode;
12) photoetching has formed the epitaxial wafer of source, leakage, grid, obtains the thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, accomplishes element manufacturing.
5. enhancement type high electron mobility transistor according to claim 5 is characterized in that step 2) in the process conditions of extension GaN host buffer layer be: temperature is 1050 ℃; Pressure is 20Torr; Hydrogen flowing quantity is 1500sccm, and ammonia flow is 6000sccm, and the gallium source flux is 220sccm.
6. enhancement type high electron mobility transistor according to claim 5; It is characterized in that; The process conditions of GaN resilient coating of secondary epitaxy are in the step 5): temperature is 1050 ℃, and pressure is 20Torr, and hydrogen flowing quantity is 1500sccm; Ammonia flow is 3000sccm, and the gallium source flux is 150sccm.
7. enhancement type high electron mobility transistor according to claim 5; It is characterized in that use the process conditions of plasma-reinforced chemical vapor deposition PECVD method dielectric layer deposited to be in the step 7): ammonia flow is 2.5sccm, and nitrogen flow is 900sccm; Silane flow rate is 200sccm; Temperature is 300 ℃, and pressure is 900mT, and power is 25W.
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| CN111463259A (en) * | 2020-03-10 | 2020-07-28 | 芜湖启迪半导体有限公司 | High electron mobility field effect transistor and preparation method thereof |
| CN112397584A (en) * | 2019-08-14 | 2021-02-23 | 新唐科技股份有限公司 | Enhanced high electron mobility transistor element |
| US11316038B2 (en) | 2018-11-20 | 2022-04-26 | Stmicroelectronics S.R.L. | HEMT transistor with adjusted gate-source distance, and manufacturing method thereof |
| US20220199802A1 (en) * | 2020-12-22 | 2022-06-23 | Applied Materials, Inc. | Implantation Enabled Precisely Controlled Source And Drain Etch Depth |
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| US11316038B2 (en) | 2018-11-20 | 2022-04-26 | Stmicroelectronics S.R.L. | HEMT transistor with adjusted gate-source distance, and manufacturing method thereof |
| CN112397584A (en) * | 2019-08-14 | 2021-02-23 | 新唐科技股份有限公司 | Enhanced high electron mobility transistor element |
| CN112397584B (en) * | 2019-08-14 | 2023-09-29 | 新唐科技股份有限公司 | Enhanced high electron mobility transistor element |
| CN111463259B (en) * | 2020-03-10 | 2022-09-13 | 安徽长飞先进半导体有限公司 | High electron mobility field effect transistor and preparation method thereof |
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| US20220199802A1 (en) * | 2020-12-22 | 2022-06-23 | Applied Materials, Inc. | Implantation Enabled Precisely Controlled Source And Drain Etch Depth |
| US11721743B2 (en) * | 2020-12-22 | 2023-08-08 | Applied Materials, Inc. | Implantation enabled precisely controlled source and drain etch depth |
| US20230083904A1 (en) * | 2021-09-14 | 2023-03-16 | United Microelectronics Corp. | High electron mobility transistor structure and method of fabricating the same |
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