CN102683353A - Array substrate for display device and producing method of array substrate - Google Patents
Array substrate for display device and producing method of array substrate Download PDFInfo
- Publication number
- CN102683353A CN102683353A CN2012100995824A CN201210099582A CN102683353A CN 102683353 A CN102683353 A CN 102683353A CN 2012100995824 A CN2012100995824 A CN 2012100995824A CN 201210099582 A CN201210099582 A CN 201210099582A CN 102683353 A CN102683353 A CN 102683353A
- Authority
- CN
- China
- Prior art keywords
- scan line
- data wire
- oxide semiconductor
- semiconductor layer
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 230000004888 barrier function Effects 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract 4
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000003672 processing method Methods 0.000 abstract 1
- 239000010409 thin film Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Disclosed are an array substrate for a display device and a producing method of the array substrate. The array substrate for the display device comprises the substrate having a pixel region, a scanning line, a grid electrode, a data line, an insulation layer, an oxide semiconductor layer and a protective layer, wherein the scanning line, the grid electrode and the data line are located on the substrate, the grid electrode is connected with the scanning line, the scanning line and the data line intersect so as to define the pixel region, the data line is broken at the intersection position of the data line and the scanning line, the insulation layer is arranged above the scanning line, the grid electrode and the data line, the insulation layer is provided with a contact hole which is exposed out of a terminal portion of the scanning line, a terminal portion of the data line and two sides of the position where a source electrode and the data line are disconnected with the scanning line, the oxide semiconductor layer is arranged above the insulation layer and the pixel region, the oxide semiconductor layer is connected to the terminal portion of the scanning line, the terminal portion of the data line, the source electrode and the two sides of the data line at the position where the data line is disconnected with the scanning line, and the protective layer is arranged on the oxide semiconductor layer above the grid electrode. An ion implantation method or an annealing processing method is used, so that the oxide semiconductor layer of a region which is outside the protective layer forms a transparent electrode having conductor characteristics.
Description
Technical field
The present invention relates to be used for the array base palte of display device, particularly comprise the array base palte of thin-film transistor with oxide semiconductor layer, and the manufacturing approach of this array base palte.
Background technology
The processing procedure of metal current oxide semiconductor TFT (thin-film transistor) is similar with existing amorphous silicon processing procedure; Remove traditional BCE (Back Channel Etching, back of the body passage etching)) outside the structure, consider characteristic of semiconductor and have ESL (Etch Stop Layer; Etching barrier layer) with Co-Planar coplane framework; Required processing procedure needs five roads or six road light shields, and processing procedure is comparatively complicated, and manufacturing cost is higher.Fig. 1 adopts IGZO (Indium Gallium Zinc Oxide at present; Indium gallium zinc oxide) makes the main ESL structure of thin-film transistor; With the BCE similar of a-Si (amorphous silicon) thin-film transistor, main difference is adding that ESL dielectric protection layer semiconductor layer is to keep good TFT characteristic.
Summary of the invention
Goal of the invention: the problem and shortage to above-mentioned prior art exists, the purpose of this invention is to provide a kind of manufacturing approach that is used for array base palte and this array base palte of display device, can simplify processing procedure, reduce manufacturing cost.
Technical scheme: for realizing the foregoing invention purpose, first kind of technical scheme that the present invention adopts is a kind of array base palte that is used for display device, comprising:
Substrate with pixel region;
Be positioned at scan line, grid and data wire on the said substrate, said grid is connected to said scan line, and said scan line and data wire intersect to limit said pixel region, and said data wire breaks off at the infall with said scan line;
Be positioned at the insulating barrier on said scan line, grid and the data wire, portion of terminal, source electrode and the data wire that this insulating barrier has the portion of terminal of exposing said scan line, a data wire with the contact hole of the both sides of scan line gap;
Be positioned at the oxide semiconductor layer on said insulating barrier and the pixel region, said oxide semiconductor layer be connected to through said contact hole said scan line portion of terminal, data wire portion of terminal, source electrode and data wire with the both sides of scan line gap;
Be positioned at said grid top and be positioned at the protective layer on the oxide semiconductor layer;
Adopt ion to inject or the mode of annealing in process makes and is positioned at protective layer and becomes the transparency electrode with conductor characteristics with the oxide semiconductor layer of exterior domain.
The preferred indium gallium of the material of said oxide semiconductor layer zinc oxide.
The combination of preferred silicon dioxide of the material of said insulating barrier and protective layer or silicon nitride or silicon dioxide and silicon nitride.
Second kind of method that technical scheme is a kind of manufacturing array substrate that the present invention adopts comprises the steps:
(1) first road light shield: form scan line, grid and data wire on the array base palte of pixel region having; Said grid is connected to said scan line; Said scan line and data wire intersect to limit said pixel region, and said data wire breaks off at the infall with said scan line;
(2) on said scan line, grid and data wire, form insulating barrier;
(3) second road light shields: on said insulating barrier, form have the portion of terminal of exposing said scan line, portion of terminal, source electrode and the data wire of data wire with the contact hole of the both sides of scan line gap;
(4) the 3rd road light shields: on said insulating barrier and pixel region, form oxide semiconductor layer, said oxide semiconductor layer be connected to through said contact hole said scan line portion of terminal, data wire portion of terminal, source electrode and data wire with the both sides of scan line gap;
(5) the 4th road light shields: above said grid and on oxide semiconductor layer, form protective layer;
(6) adopt ion to inject or the mode of annealing in process makes and is positioned at protective layer and becomes the transparency electrode with conductor characteristics with the oxide semiconductor layer of exterior domain.
The preferred indium gallium of the material of said oxide semiconductor layer zinc oxide.
The combination of preferred silicon dioxide of the material of said insulating barrier and protective layer or silicon nitride or silicon dioxide and silicon nitride.
Beneficial effect: the present invention can simplify the processing procedure of IGZO semiconductor TFT, is reduced to four road light shields by five to six original road light shields, effectively reduces manufacturing cost.
Description of drawings
Fig. 1 is the transistorized ESL schematic cross-section of prior art metal oxide semiconductor films;
Fig. 2 (A) forms the structural representation of scan line, grid and data wire for the present invention; Fig. 2 (B) is the A-A ' profile of Fig. 2 (A);
Fig. 3 (A) forms the structural representation of insulating barrier and contact hole for the present invention; Fig. 3 (B) is the B-B ' profile of Fig. 3 (A);
Fig. 4 (A) forms the structural representation of IGZO layer for the present invention; Fig. 4 (B) is the C-C ' profile of Fig. 4 (A);
Fig. 5 (A) forms the structural representation of protective layer for the present invention; Fig. 5 (B) is the D-D ' profile of Fig. 5 (A).
Embodiment
Below in conjunction with accompanying drawing and specific embodiment; Further illustrate the present invention; Should understand these embodiment only be used to the present invention is described and be not used in the restriction scope of the present invention; After having read the present invention, those skilled in the art all fall within the application's accompanying claims institute restricted portion to the modification of the various equivalent form of values of the present invention.
Shown in Fig. 2 (A) and Fig. 2 (B); Utilize underlying metal to form scan line, grid and data wire on the array base palte of pixel region having; Said grid is connected to said scan line; Said scan line and data wire intersect to limit said pixel region, and said data wire breaks off at the infall with said scan line;
Shown in Fig. 3 (A) and Fig. 3 (B), on said scan line, grid and data wire, form the insulating barrier of earth silicon material; On said insulating barrier, form have the portion of terminal of exposing said scan line, portion of terminal (not shown), source electrode (be actually subsequent step and form the position that connects source electrode) and the data wire of data wire with the contact hole of the both sides of scan line gap;
Shown in Fig. 4 (A) and Fig. 4 (B); On said insulating barrier and pixel region, form the IGZO layer, said IGZO layer be connected to through said contact hole said scan line portion of terminal, data wire portion of terminal (not shown), source electrode and data wire with the both sides of scan line gap;
Shown in Fig. 5 (A) and Fig. 5 (B), at the protective layer that forms earth silicon material above the said grid and on the IGZO layer; The mode that adopts ion to inject makes and is positioned at protective layer and becomes the transparency electrode with conductor characteristics with the IGZO layer of exterior domain.At this moment; Originally become the IGZO layer bridge joint of transparency electrode at data wire with the disconnection of scan line infall; And being connected to the source electrode that is positioned at the protective layer left side, the IGZO layer on protective layer right side then is connected to the IGZO layer (being pixel electrode) that is positioned at pixel region as drain electrode; The IGZO layer that is positioned at the protective layer below remains semiconductor layer, guarantees that between source electrode and the drain electrode be opening circuit on the electricity.
Claims (6)
1. array base palte that is used for display device comprises:
Substrate with pixel region;
Be positioned at scan line, grid and data wire on the said substrate, said grid is connected to said scan line, and said scan line and data wire intersect to limit said pixel region, and said data wire breaks off at the infall with said scan line;
Be positioned at the insulating barrier on said scan line, grid and the data wire, portion of terminal, source electrode and the data wire that this insulating barrier has the portion of terminal of exposing said scan line, a data wire with the contact hole of the both sides of scan line gap;
Be positioned at the oxide semiconductor layer on said insulating barrier and the pixel region, said oxide semiconductor layer be connected to through said contact hole said scan line portion of terminal, data wire portion of terminal, source electrode and data wire with the both sides of scan line gap;
Be positioned at said grid top and be positioned at the protective layer on the oxide semiconductor layer;
Adopt ion to inject or the mode of annealing in process makes and is positioned at protective layer and becomes the transparency electrode with conductor characteristics with the oxide semiconductor layer of exterior domain.
2. according to the said array base palte that is used for display device of claim 1, it is characterized in that: the material of said oxide semiconductor layer is an indium gallium zinc oxide.
3. according to the said array base palte that is used for display device of claim 1, it is characterized in that: the material of said insulating barrier and protective layer is the combination of silicon dioxide or silicon nitride or silicon dioxide and silicon nitride.
4. the method for a manufacturing array substrate comprises the steps:
(1) first road light shield: form scan line, grid and data wire on the array base palte of pixel region having; Said grid is connected to said scan line; Said scan line and data wire intersect to limit said pixel region, and said data wire breaks off at the infall with said scan line;
(2) on said scan line, grid and data wire, form insulating barrier;
(3) second road light shields: on said insulating barrier, form have the portion of terminal of exposing said scan line, portion of terminal, source electrode and the data wire of data wire with the contact hole of the both sides of scan line gap;
(4) the 3rd road light shields: on said insulating barrier and pixel region, form oxide semiconductor layer, said oxide semiconductor layer be connected to through said contact hole said scan line portion of terminal, data wire portion of terminal, source electrode and data wire with the both sides of scan line gap;
(5) the 4th road light shields: above said grid and on oxide semiconductor layer, form protective layer;
(6) adopt ion to inject or the mode of annealing in process makes and is positioned at protective layer and becomes the transparency electrode with conductor characteristics with the oxide semiconductor layer of exterior domain.
5. according to the method for the said manufacturing array substrate of claim 4, it is characterized in that: the material of said oxide semiconductor layer is an indium gallium zinc oxide.
6. according to the method for the said manufacturing array substrate of claim 4, it is characterized in that: the material of said insulating barrier and protective layer is the combination of silicon dioxide or silicon nitride or silicon dioxide and silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210099582.4A CN102683353B (en) | 2012-04-05 | 2012-04-05 | Array substrate for display device and producing method of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210099582.4A CN102683353B (en) | 2012-04-05 | 2012-04-05 | Array substrate for display device and producing method of array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102683353A true CN102683353A (en) | 2012-09-19 |
| CN102683353B CN102683353B (en) | 2014-12-17 |
Family
ID=46815039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210099582.4A Expired - Fee Related CN102683353B (en) | 2012-04-05 | 2012-04-05 | Array substrate for display device and producing method of array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102683353B (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199094A (en) * | 2013-03-25 | 2013-07-10 | 南京中电熊猫液晶显示科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
| CN103257499A (en) * | 2013-05-28 | 2013-08-21 | 南京中电熊猫液晶显示科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
| CN104793420A (en) * | 2015-05-08 | 2015-07-22 | 厦门天马微电子有限公司 | Array substrate, manufacturing method and display device |
| CN106057818A (en) * | 2016-05-26 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
| CN106201150A (en) * | 2016-08-31 | 2016-12-07 | 武汉华星光电技术有限公司 | Array base palte and touch-control display panel |
| CN106887406A (en) * | 2017-03-29 | 2017-06-23 | 深圳市华星光电技术有限公司 | A kind of preparation method of array base palte |
| CN107425008A (en) * | 2015-11-27 | 2017-12-01 | 南京中电熊猫液晶显示科技有限公司 | A kind of array base palte and its manufacture method |
| CN108008586A (en) * | 2017-12-19 | 2018-05-08 | 深圳市华星光电半导体显示技术有限公司 | Array base palte, array base palte preparation method and display device |
| CN108206182A (en) * | 2017-12-28 | 2018-06-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and its manufacturing method |
| CN111427207A (en) * | 2020-03-31 | 2020-07-17 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114089571A (en) * | 2021-11-30 | 2022-02-25 | 昆山龙腾光电股份有限公司 | Array substrate, manufacturing method and display panel |
| CN114185212A (en) * | 2021-11-30 | 2022-03-15 | 重庆惠科金渝光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478005A (en) * | 2009-02-13 | 2009-07-08 | 北京大学深圳研究生院 | Metal oxide thin-film transistor and manufacturing process thereof |
| US20110073864A1 (en) * | 2009-09-25 | 2011-03-31 | Beijing Boe Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method |
| CN102157563A (en) * | 2011-01-18 | 2011-08-17 | 上海交通大学 | Method for manufacturing metal oxide thin film transistor |
-
2012
- 2012-04-05 CN CN201210099582.4A patent/CN102683353B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478005A (en) * | 2009-02-13 | 2009-07-08 | 北京大学深圳研究生院 | Metal oxide thin-film transistor and manufacturing process thereof |
| US20110073864A1 (en) * | 2009-09-25 | 2011-03-31 | Beijing Boe Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method |
| CN102157563A (en) * | 2011-01-18 | 2011-08-17 | 上海交通大学 | Method for manufacturing metal oxide thin film transistor |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199094B (en) * | 2013-03-25 | 2016-01-20 | 南京中电熊猫液晶显示科技有限公司 | TFT-LCD array substrate and manufacture method thereof |
| CN103199094A (en) * | 2013-03-25 | 2013-07-10 | 南京中电熊猫液晶显示科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
| CN103257499A (en) * | 2013-05-28 | 2013-08-21 | 南京中电熊猫液晶显示科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
| CN104793420A (en) * | 2015-05-08 | 2015-07-22 | 厦门天马微电子有限公司 | Array substrate, manufacturing method and display device |
| CN107425008B (en) * | 2015-11-27 | 2020-04-10 | 南京中电熊猫液晶显示科技有限公司 | Array substrate and manufacturing method thereof |
| CN107425008A (en) * | 2015-11-27 | 2017-12-01 | 南京中电熊猫液晶显示科技有限公司 | A kind of array base palte and its manufacture method |
| US10181422B2 (en) | 2016-05-26 | 2019-01-15 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same, and display apparatus |
| CN106057818A (en) * | 2016-05-26 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
| WO2017202171A1 (en) * | 2016-05-26 | 2017-11-30 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| CN106057818B (en) * | 2016-05-26 | 2019-05-07 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| CN106201150A (en) * | 2016-08-31 | 2016-12-07 | 武汉华星光电技术有限公司 | Array base palte and touch-control display panel |
| CN106201150B (en) * | 2016-08-31 | 2019-04-16 | 武汉华星光电技术有限公司 | Array substrate and touch-control display panel |
| CN106887406B (en) * | 2017-03-29 | 2019-11-15 | 深圳市华星光电半导体显示技术有限公司 | A kind of production method of array substrate |
| CN106887406A (en) * | 2017-03-29 | 2017-06-23 | 深圳市华星光电技术有限公司 | A kind of preparation method of array base palte |
| CN108008586A (en) * | 2017-12-19 | 2018-05-08 | 深圳市华星光电半导体显示技术有限公司 | Array base palte, array base palte preparation method and display device |
| CN108008586B (en) * | 2017-12-19 | 2021-04-30 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, array substrate preparation method and display device |
| CN108206182A (en) * | 2017-12-28 | 2018-06-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and its manufacturing method |
| CN111427207A (en) * | 2020-03-31 | 2020-07-17 | 厦门天马微电子有限公司 | Display panel and display device |
| CN111427207B (en) * | 2020-03-31 | 2022-08-12 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114089571A (en) * | 2021-11-30 | 2022-02-25 | 昆山龙腾光电股份有限公司 | Array substrate, manufacturing method and display panel |
| CN114185212A (en) * | 2021-11-30 | 2022-03-15 | 重庆惠科金渝光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN114089571B (en) * | 2021-11-30 | 2024-01-16 | 昆山龙腾光电股份有限公司 | Array substrate, manufacturing method and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102683353B (en) | 2014-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102683353B (en) | Array substrate for display device and producing method of array substrate | |
| CN102636927B (en) | Array base palte and manufacture method thereof | |
| TW201721720A (en) | TFT array substrate, display panel, display device and method for making the TFT array substrate | |
| CN104952885A (en) | Display baseplate, manufacturing method thereof and display device | |
| CN105097841B (en) | The production method and TFT substrate of TFT substrate | |
| CN103730508A (en) | Vertical thin film transistor structure of display panel and manufacturing method of vertical thin film transistor structure | |
| CN110190031B (en) | Preparation method of thin film transistor substrate | |
| CN104345511B (en) | Dot structure and its manufacture method, display panel | |
| CN107658345A (en) | Oxide thin film transistor and preparation method thereof, array base palte and display device | |
| CN105070764A (en) | TFT, array substrate, display device, and preparation method of TFT | |
| CN104091831A (en) | Thin film transistor, array substrate and display device | |
| CN105655291A (en) | Method for manufacturing array substrate, array substrate and display panel | |
| CN105047611B (en) | Array base palte and preparation method thereof, display device | |
| CN103579357B (en) | Semiconductor structure | |
| CN102664187B (en) | Organic light emitting diode display and manufacture method thereof | |
| CN102723334A (en) | Metal oxide thin-film transistor substrate, manufacture method thereof and liquid crystal display | |
| CN104701254A (en) | Manufacturing method of low-temperature polycrystalline silicon thin-film transistor array substrate | |
| CN101937875B (en) | Complementary metal-oxide-semiconductor (CMOS) transistor and manufacturing method thereof | |
| CN203932068U (en) | A kind of thin-film transistor, array base palte and display unit | |
| CN104253158A (en) | Thin-film transistor and manufacturing method thereof | |
| CN106653695A (en) | Low-temperature polycrystalline silicon array substrate and manufacturing method thereof | |
| CN110224031A (en) | Improve the structure and its production method of metal oxide TFT characteristic | |
| CN105242435A (en) | Array substrate, manufacturing method and liquid crystal display panel | |
| CN102637684B (en) | Array substrate used for display equipment and manufacturing method thereof | |
| CN104733536A (en) | Thin film transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141217 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |