CN104952885A - Display baseplate, manufacturing method thereof and display device - Google Patents
Display baseplate, manufacturing method thereof and display device Download PDFInfo
- Publication number
- CN104952885A CN104952885A CN201510252987.0A CN201510252987A CN104952885A CN 104952885 A CN104952885 A CN 104952885A CN 201510252987 A CN201510252987 A CN 201510252987A CN 104952885 A CN104952885 A CN 104952885A
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- grid
- grid line
- active layer
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a display baseplate, a manufacturing method thereof and a display device. The display baseplate comprises a substrate baseplate, a light shielding metal layer and data lines are arranged on the substrate baseplate, the light shielding metal layer comprises first grid lines and a light shielding layer, second grid lines are arranged at corresponding positions above the light shielding layer, and a pixel unit limited by the first grid lines, the second grid lines and the data lines comprises pixel electrodes and a thin film transistor. The first grid lines and the second grid lines are arranged correspondingly to enable the first grid lines and the second grid lines on different layers to be at same positions, so that area of one grid lines can be saved, aperture ratio is increased, and power consumption is lowered.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of display base plate and preparation method thereof, display unit.
Background technology
In existing Display Technique, liquid crystal display can be described as technology the most ripe, and such as, the products such as mobile phone common in daily life, digital camera, video camera, television set, notebook are all liquid crystal display.Along with people are to the raising of the quality requirements of display frame, the Display Technique of high PPI (Pixels Per Inch, per inch number of pixels) more and more comes into one's own.Therefore, the Display Technique of existing low aperture opening ratio, high power consumption cannot meet the requirement of people.
Summary of the invention
For solving the problem, the invention provides a kind of display base plate and preparation method thereof, display unit, for solving the problem that in prior art, the aperture opening ratio of display floater is low, power consumption is high.
For this reason, the invention provides a kind of display base plate, comprise underlay substrate, described underlay substrate is provided with shading metal level and data wire, described shading metal level comprises the first grid line and light shield layer, the top correspondence position of described light shield layer is provided with the second grid line, and the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.
Optionally, also comprise insulating barrier, described insulating barrier comprises resilient coating and first grid insulating barrier, and described resilient coating is arranged on described light shield layer, and described first grid insulating barrier is arranged on described first grid line.
Optionally, described thin-film transistor includes active layer, source electrode, drain electrode, first grid or second grid, and the constituent material of described active layer comprises polysilicon, amorphous silicon or metal oxide.
Optionally, described light shield layer is arranged on described underlay substrate, described active layer is arranged on described resilient coating, described active layer is provided with second gate insulating barrier, described second grid line and second grid are arranged on described second gate insulating barrier, described second grid line and second grid are provided with interlayer dielectric layer, described interlayer dielectric layer is provided with the first via hole and the second via hole, described source electrode is connected with described active layer by described first via hole, and described drain electrode is connected with described active layer by described second via hole.
Optionally, described first grid line and first grid are arranged on described underlay substrate, described active layer is arranged on described first grid insulating barrier, described active layer is provided with second gate insulating barrier, described second gate insulating barrier is provided with interlayer dielectric layer, described interlayer dielectric layer is provided with the first via hole and the second via hole, described source electrode is connected with described active layer by described first via hole, and described drain electrode is connected with described active layer by described second via hole.
The present invention also provides a kind of display unit, comprises above-mentioned arbitrary display base plate.
The present invention also provides a kind of preparation method of display base plate, comprising:
Underlay substrate is formed shading metal level, and described shading metal level comprises the first grid line and light shield layer;
Above described light shield layer, correspondence position forms the second grid line;
Form data wire, pixel electrode and thin-film transistor, the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.
Optionally, described on underlay substrate, form the step of shading metal level after comprise:
Described shading metal level forms insulating barrier, and described insulating barrier comprises resilient coating and first grid insulating barrier;
The described step forming insulating barrier on described shading metal level comprises:
Described light shield layer forms resilient coating, described first grid line forms first grid insulating barrier.
Optionally, described thin-film transistor includes active layer, source electrode, drain electrode, first grid or second grid, and the constituent material of described active layer comprises polysilicon, amorphous silicon or metal oxide.
Optionally, described on described light shield layer, form the step of resilient coating after comprise:
Described resilient coating forms described active layer;
Described active layer is formed second gate insulating barrier;
The described step that correspondence position forms the second grid line above described light shield layer comprises:
While described second gate insulating barrier forms the second grid line, described second gate insulating barrier forms second grid;
Described on described second gate insulating barrier, form the second grid line while, comprise after described second gate insulating barrier forms the step of second grid:
Described second grid line and second grid form interlayer dielectric layer, described interlayer dielectric layer is formed with the first via hole and the second via hole;
Described interlayer dielectric layer is formed described source electrode and described drain electrode, and described source electrode is connected with described active layer by described first via hole, and described drain electrode is connected with described active layer by described second via hole.
Optionally, the described step forming shading metal level on underlay substrate comprises:
While described underlay substrate is formed the first grid line, described underlay substrate forms first grid;
Described on described first grid line, form the step of first grid insulating barrier after comprise:
Described first grid insulating barrier forms described active layer;
Described active layer is formed second gate insulating barrier;
Described second gate insulating barrier forms interlayer dielectric layer, described interlayer dielectric layer is formed with the first via hole and the second via hole;
Described interlayer dielectric layer is formed described source electrode and described drain electrode, and described source electrode is connected with described active layer by described first via hole, and described drain electrode is connected with described active layer by described second via hole.
The present invention has following beneficial effect:
In display base plate provided by the invention and preparation method thereof, display unit, described display base plate comprises underlay substrate, described underlay substrate is provided with shading metal level and data wire, described shading metal level comprises the first grid line and light shield layer, the top correspondence position of described light shield layer is provided with the second grid line, and the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.First grid line provided by the invention is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
Accompanying drawing explanation
A kind of structural representation of the display floater that Fig. 1 provides for the embodiment of the present invention one;
The another kind of structural representation of the display floater that Fig. 2 provides for the embodiment of the present invention one;
A kind of structural representation of the display floater that Fig. 3 provides for the embodiment of the present invention two;
The another kind of structural representation of the display floater that Fig. 4 provides for the embodiment of the present invention two;
The flow chart of the preparation method of the display base plate that Fig. 5 provides for the embodiment of the present invention four.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with accompanying drawing, display base plate provided by the invention and preparation method thereof, display unit are described in detail.
Embodiment one
A kind of structural representation of the display floater that Fig. 1 provides for the embodiment of the present invention one, the another kind of structural representation of the display floater that Fig. 2 provides for the embodiment of the present invention one.As depicted in figs. 1 and 2, described display base plate comprises underlay substrate 100, described underlay substrate 100 is provided with shading metal level and data wire, and described shading metal level comprises the first grid line 101 and light shield layer 103, and the top correspondence position of described light shield layer 103 is provided with the second grid line 102.The pixel cell that described first grid line 101, second grid line 102 and data wire limit comprises pixel electrode 104 and thin-film transistor.First grid line of described display floater is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
In the present embodiment, described display floater also comprises insulating barrier, and the constituent material of described insulating barrier comprises silicon nitride SiNx or silicon oxide sio 2.Optionally, Dehydroepiandrosterone derivative is carried out to described insulating barrier, not affect the characteristic of semiconductor being arranged on active layer on described insulating barrier.Described insulating barrier comprises resilient coating 105 and first grid insulating barrier 106, and described resilient coating 105 is arranged on described light shield layer 103, and described first grid insulating barrier 106 is arranged on described first grid line 101.
See Fig. 1, described underlay substrate 100 is provided with light shield layer 103, described light shield layer 103 is provided with resilient coating 105.Described resilient coating 105 is provided with active layer, and described active layer comprises polycrystalline silicon active district 107, light doping section 108 and heavily doped region 109, and described light doping section 108 and described heavily doped region 109 are formed by ion implantation technology.Described heavily doped region 109 comprises two parts, and wherein a part of heavily doped region 109 is arranged on one end of described active layer, and another part heavily doped region 109 is arranged on the other end of described active layer.Described polycrystalline silicon active district 107 is arranged between two parts heavily doped region 109, and described polycrystalline silicon active district 107 and described heavily doped region 109 form interval by described light doping section 108.Described polycrystalline silicon active district 107 comprises three parts, and described three partial polysilicon active areas 107 form interval by described light doping section 108.The contact performance of described display floater can be improved in described light doping section 108 and described heavily doped region 109.
In the present embodiment, described active layer is provided with second gate insulating barrier 201, described second gate insulating barrier 201 is provided with the second grid line 102, described second grid line 102 is provided with interlayer dielectric layer 202.Described interlayer dielectric layer 202 is provided with the first via hole and the second via hole, described first via hole runs through described interlayer dielectric layer 202 and described second gate insulating barrier 201, correspondingly with the heavily doped region 109 of described active layer one end arranges.Described second via hole runs through described interlayer dielectric layer 202 and described second gate insulating barrier 201, correspondingly with the heavily doped region 109 of the described active layer other end arranges.Described source electrode 203 is connected with described active layer by described first via hole, and described drain electrode 204 is connected with described active layer by described second via hole.Described source electrode 203 and described drain electrode 204 are provided with resin bed 205, and described resin bed 205 can reduce power consumption.Described resin bed 205 is provided with public electrode 206, described public electrode 206 is provided with passivation layer 207.Described passivation layer 207 is provided with the 3rd via hole, described 3rd via hole runs through described passivation layer 207 and described resin bed 205, and described 3rd via hole is corresponding with described drain electrode 204 to be arranged.Described passivation layer 207 is provided with pixel electrode 104, and described pixel electrode 104 is connected with described drain electrode 204 by described 3rd hole.
See Fig. 2, described underlay substrate 100 is provided with the first grid line 101, described first grid line 101 is provided with first grid insulating barrier 106.Described first grid insulating barrier 106 is provided with active layer, and described active layer comprises polycrystalline silicon active district 107, light doping section 108 and heavily doped region 109, and described light doping section 108 and described heavily doped region 109 are formed by ion implantation technology.Described heavily doped region 109 comprises two parts, and wherein a part of heavily doped region 109 is arranged on one end of described active layer, and another part heavily doped region 109 is arranged on the other end of described active layer.Described polycrystalline silicon active district 107 is arranged between two parts heavily doped region 109, and described polycrystalline silicon active district 107 and described heavily doped region 109 form interval by described light doping section 108.Described polycrystalline silicon active district 107 comprises three parts, and described three partial polysilicon active areas 107 form interval by described light doping section 108.The contact performance of described display floater can be improved in described light doping section 108 and described heavily doped region 109.
In the present embodiment, described active layer is provided with second gate insulating barrier 201, described second gate insulating barrier 201 is provided with interlayer dielectric layer 202.Described interlayer dielectric layer 202 is provided with the first via hole and the second via hole, described first via hole runs through described interlayer dielectric layer 202 and described second gate insulating barrier 201, correspondingly with the heavily doped region 109 of described active layer one end arranges.Described second via hole runs through described interlayer dielectric layer 202 and described second gate insulating barrier 201, correspondingly with the heavily doped region 109 of the described active layer other end arranges.Described source electrode 203 is connected with described active layer by described first via hole, and described drain electrode 204 is connected with described active layer by described second via hole.Described source electrode 203 and described drain electrode 204 are provided with resin bed 205, and described resin bed 205 can reduce power consumption.Described resin bed 205 is provided with public electrode 206, described public electrode 206 is provided with passivation layer 207.Described passivation layer 207 is provided with the 3rd via hole, described 3rd via hole runs through described passivation layer 207 and described resin bed 205, and described 3rd via hole is corresponding with described drain electrode 204 to be arranged.Described passivation layer 207 is provided with pixel electrode 104, and described pixel electrode 104 is connected with described drain electrode 204 by described 3rd hole.
In the display base plate that the present embodiment provides, described display base plate comprises underlay substrate, described underlay substrate is provided with shading metal level and data wire, described shading metal level comprises the first grid line and light shield layer, the top correspondence position of described light shield layer is provided with the second grid line, and the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.The first grid line that the present embodiment provides is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
Embodiment two
A kind of structural representation of the display floater that Fig. 3 provides for the embodiment of the present invention two, the another kind of structural representation of the display floater that Fig. 4 provides for the embodiment of the present invention two.As shown in Figure 3 and Figure 4, described display base plate comprises underlay substrate 100, described underlay substrate 100 is provided with shading metal level and data wire, and described shading metal level comprises the first grid line 101 and light shield layer 103, and the top correspondence position of described light shield layer 103 is provided with the second grid line 102.The pixel cell that described first grid line 101, second grid line 102 and data wire limit comprises pixel electrode 104 and thin-film transistor.First grid line of described display floater is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
In the present embodiment, described display floater also comprises insulating barrier, and the constituent material of described insulating barrier comprises silicon nitride SiNx or silicon oxide sio 2.Optionally, Dehydroepiandrosterone derivative is carried out to described insulating barrier, not affect the characteristic of semiconductor being arranged on active layer on described insulating barrier.Described insulating barrier comprises resilient coating 105 and first grid insulating barrier 106, and described resilient coating 105 is arranged on described light shield layer 103, and described first grid insulating barrier 106 is arranged on described first grid line 101.
See Fig. 3, described underlay substrate 100 is provided with light shield layer 103, described light shield layer 103 is provided with resilient coating 105.Described resilient coating 105 is provided with active layer 208, and the constituent material of described active layer 208 comprises amorphous silicon.Certainly, the constituent material of described active layer 208 also can comprise metal oxide.Described active layer 208 is provided with source electrode 203 and drain electrode 204, described source electrode 203 and described drain electrode 204 are provided with second gate insulating barrier 201, described second gate insulating barrier 201 is provided with the second grid line 102, described second grid line 102 is provided with resin bed 205, and described resin bed 205 can reduce power consumption.Described resin bed 205 is provided with public electrode 206, described public electrode 206 is provided with passivation layer 207.Described passivation layer 207 is provided with the 4th via hole, described 4th via hole runs through described passivation layer 207, described resin bed 205 and second gate insulating barrier 201, and described 4th via hole is corresponding with described drain electrode 204.Described passivation layer 207 is provided with pixel electrode 104, and described pixel electrode 104 is connected with described drain electrode 204 by described 4th hole.
See Fig. 4, described underlay substrate 100 is provided with the first grid line 101, described first grid line 101 is provided with first grid insulating barrier 106.Described first grid insulating barrier 106 is provided with active layer 208, described active layer 208 is provided with source electrode 203 and drain electrode 204, described source electrode 203 and described drain electrode 204 are provided with second gate insulating barrier 201, described second gate insulating barrier 201 is provided with resin bed 205, and described resin bed 205 can reduce power consumption.Described resin bed 205 is provided with public electrode 206, described public electrode 206 is provided with passivation layer 207.Described passivation layer 207 is provided with the 4th via hole, described 4th via hole runs through described passivation layer 207, described resin bed 205 and second gate insulating barrier 201, and described 4th via hole is corresponding with described drain electrode 204.Described passivation layer 207 is provided with pixel electrode 104, and described pixel electrode 104 is connected with described drain electrode 204 by described 4th hole.
In the display base plate that the present embodiment provides, described display base plate comprises underlay substrate, described underlay substrate is provided with shading metal level and data wire, described shading metal level comprises the first grid line and light shield layer, the top correspondence position of described light shield layer is provided with the second grid line, and the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.The first grid line that the present embodiment provides is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
Embodiment three
The present embodiment provides a kind of display unit, and comprise the display base plate that above-described embodiment one or embodiment two provide, particular content can refer to the description of above-described embodiment one or embodiment two, repeats no more herein.
In the display unit that the present embodiment provides, described display base plate comprises underlay substrate, described underlay substrate is provided with shading metal level and data wire, described shading metal level comprises the first grid line and light shield layer, the top correspondence position of described light shield layer is provided with the second grid line, and the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.The first grid line that the present embodiment provides is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
Embodiment four
The flow chart of the preparation method of the display base plate that Fig. 5 provides for the embodiment of the present invention four.As shown in Figure 5, described preparation method comprises:
Step 5001, on underlay substrate, form shading metal level, described shading metal level comprises the first grid line and light shield layer.
See Fig. 2, underlay substrate 100 forms the first grid line 101, described first grid line 101 forms first grid insulating barrier 106.The constituent material of described first grid insulating barrier 106 comprises silicon nitride SiNx or silicon oxide sio 2.Optionally, Dehydroepiandrosterone derivative is carried out to described first grid insulating barrier 106, not affect the characteristic of semiconductor being arranged on active layer on described first grid insulating barrier 106.
Step 5002, above described light shield layer, correspondence position forms the second grid line.
See Fig. 1, described underlay substrate 100 forms light shield layer 103, described light shield layer 103 forms resilient coating 105.The constituent material of described resilient coating 105 comprises silicon nitride SiNx or silicon oxide sio 2.Optionally, Dehydroepiandrosterone derivative is carried out to described resilient coating 105, not affect the characteristic of semiconductor being arranged on active layer on described resilient coating 105.Above described light shield layer 103, correspondence position forms the second grid line 102.The first grid line that the present embodiment provides is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
Step 5003, formation data wire, pixel electrode and thin-film transistor, the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.
See Fig. 1, described resilient coating 105 is formed with active layer, described active layer comprises polycrystalline silicon active district 107, light doping section 108 and heavily doped region 109, and described light doping section 108 and described heavily doped region 109 are formed by ion implantation technology.Described heavily doped region 109 comprises two parts, and wherein a part of heavily doped region 109 is arranged on one end of described active layer, and another part heavily doped region 109 is arranged on the other end of described active layer.Described polycrystalline silicon active district 107 is arranged between two parts heavily doped region 109, and described polycrystalline silicon active district 107 and described heavily doped region 109 form interval by described light doping section 108.Described polycrystalline silicon active district 107 comprises three parts, and described three partial polysilicon active areas 107 form interval by described light doping section 108.The contact performance of described display floater can be improved in described light doping section 108 and described heavily doped region 109.
In the present embodiment, described active layer forms second gate insulating barrier 201, described second gate insulating barrier 201 is formed the second grid line 102, described second grid line 102 forms interlayer dielectric layer 202.Described interlayer dielectric layer 202 is formed the first via hole and the second via hole, and described first via hole runs through described interlayer dielectric layer 202 and described second gate insulating barrier 201, correspondingly with the heavily doped region 109 of described active layer one end arranges.Described second via hole runs through described interlayer dielectric layer 202 and described second gate insulating barrier 201, correspondingly with the heavily doped region 109 of the described active layer other end arranges.Described interlayer dielectric layer 202 is formed source electrode 203 and drain electrode 204, and described source electrode 203 is connected with described active layer by described first via hole, and described drain electrode 204 is connected with described active layer by described second via hole.Described source electrode 203 and described drain electrode 204 form resin bed 205.Described resin bed 205 forms public electrode 206, described public electrode 206 forms passivation layer 207.Described passivation layer 207 forms the 3rd via hole, and described 3rd via hole runs through described passivation layer 207 and described resin bed 205, and described 3rd via hole is corresponding with described drain electrode 204 to be arranged.Described passivation layer 207 forms pixel electrode 104, and described pixel electrode 104 is connected with described drain electrode 204 by described 3rd hole.
See Fig. 2, described first grid insulating barrier 106 is formed with active layer, described active layer comprises polycrystalline silicon active district 107, light doping section 108 and heavily doped region 109, and described light doping section 108 and described heavily doped region 109 are formed by ion implantation technology.Described heavily doped region 109 comprises two parts, and wherein a part of heavily doped region 109 is arranged on one end of described active layer, and another part heavily doped region 109 is arranged on the other end of described active layer.Described polycrystalline silicon active district 107 is arranged between two parts heavily doped region 109, and described polycrystalline silicon active district 107 and described heavily doped region 109 form interval by described light doping section 108.Described polycrystalline silicon active district 107 comprises three parts, and described three partial polysilicon active areas 107 form interval by described light doping section 108.The contact performance of described display floater can be improved in described light doping section 108 and described heavily doped region 109.
In the present embodiment, described active layer forms second gate insulating barrier 201, described second gate insulating barrier 201 forms interlayer dielectric layer 202.Described interlayer dielectric layer 202 is formed the first via hole and the second via hole, and described first via hole runs through described interlayer dielectric layer 202 and described second gate insulating barrier 201, correspondingly with the heavily doped region 109 of described active layer one end arranges.Described second via hole runs through described interlayer dielectric layer 202 and described second gate insulating barrier 201, correspondingly with the heavily doped region 109 of the described active layer other end arranges.Described interlayer dielectric layer 202 is formed source electrode 203 and drain electrode 204, and described source electrode 203 is connected with described active layer by described first via hole, and described drain electrode 204 is connected with described active layer by described second via hole.Described source electrode 203 and described drain electrode 204 form resin bed 205.Described resin bed 205 forms public electrode 206, described public electrode 206 forms passivation layer 207.Described passivation layer 207 forms the 3rd via hole, and described 3rd via hole runs through described passivation layer 207 and described resin bed 205, and described 3rd via hole is corresponding with described drain electrode 204 to be arranged.Described passivation layer 207 forms pixel electrode 104, and described pixel electrode 104 is connected with described drain electrode 204 by described 3rd hole.
In the preparation method of the display base plate that the present embodiment provides, described display base plate comprises underlay substrate, described underlay substrate is provided with shading metal level and data wire, described shading metal level comprises the first grid line and light shield layer, the top correspondence position of described light shield layer is provided with the second grid line, and the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.The first grid line that the present embodiment provides is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
Embodiment five
The present embodiment provides a kind of preparation method of display base plate, comprise: on underlay substrate, form shading metal level, described shading metal level comprises the first grid line and light shield layer, above described light shield layer, correspondence position forms the second grid line, form data wire, pixel electrode and thin-film transistor, the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.The first grid line that the present embodiment provides is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.The forming process of described display base plate is illustrated below in conjunction with Fig. 3 and Fig. 4.
See Fig. 3, described underlay substrate 100 forms light shield layer 103, described light shield layer 103 is formed with resilient coating 105.Described resilient coating 105 is formed with active layer 208, and the constituent material of described active layer 208 comprises amorphous silicon.Certainly, the constituent material of described active layer 208 also can comprise metal oxide.Described active layer 208 is formed source electrode 203 and drain electrode 204, described source electrode 203 and described drain electrode 204 forms second gate insulating barrier 201, described second gate insulating barrier 201 is formed the second grid line 102, described second grid line 102 forms resin bed 205.Described resin bed 205 forms public electrode 206, described public electrode 206 forms passivation layer 207.Described passivation layer 207 forms the 4th via hole, and described 4th via hole runs through described passivation layer 207, described resin bed 205 and second gate insulating barrier 201, and described 4th via hole is corresponding with described drain electrode 204 to be arranged.Described passivation layer 207 forms pixel electrode 104, and described pixel electrode 104 is connected with described drain electrode 204 by described 4th hole.
See Fig. 4, described underlay substrate 100 forms the first grid line 101, described first grid line 101 forms first grid insulating barrier 106.Described first grid insulating barrier 106 is formed with active layer 208, described active layer 208 is formed source electrode 203 and drain electrode 204, described source electrode 203 and described drain electrode 204 form second gate insulating barrier 201, described second gate insulating barrier 201 forms resin bed 205.Described resin bed 205 forms public electrode 206, described public electrode 206 forms passivation layer 207.Described passivation layer 207 forms the 4th via hole, and described 4th via hole runs through described passivation layer 207, described resin bed 205 and second gate insulating barrier 201, and described 4th via hole is corresponding with described drain electrode 204 to be arranged.Described passivation layer 207 forms pixel electrode 104, and described pixel electrode 104 is connected with described drain electrode 204 by described 4th hole.
In the preparation method of the display base plate that the present embodiment provides, described display base plate comprises underlay substrate, described underlay substrate is provided with shading metal level and data wire, described shading metal level comprises the first grid line and light shield layer, the top correspondence position of described light shield layer is provided with the second grid line, and the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.The first grid line that the present embodiment provides is corresponding with the second grid line to be arranged, and is positioned at same position, thus can saves the area of a grid line, improve aperture opening ratio, reduce power consumption with the first grid line and the second grid line that make different layers.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (11)
1. a display base plate, it is characterized in that, comprise underlay substrate, described underlay substrate is provided with shading metal level and data wire, described shading metal level comprises the first grid line and light shield layer, the top correspondence position of described light shield layer is provided with the second grid line, and the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.
2. display base plate according to claim 1, is characterized in that, also comprises insulating barrier, and described insulating barrier comprises resilient coating and first grid insulating barrier, and described resilient coating is arranged on described light shield layer, and described first grid insulating barrier is arranged on described first grid line.
3. display base plate according to claim 2, is characterized in that, described thin-film transistor includes active layer, source electrode, drain electrode, first grid or second grid, and the constituent material of described active layer comprises polysilicon, amorphous silicon or metal oxide.
4. display base plate according to claim 3, it is characterized in that, described light shield layer is arranged on described underlay substrate, described active layer is arranged on described resilient coating, described active layer is provided with second gate insulating barrier, described second grid line and second grid are arranged on described second gate insulating barrier, described second grid line and second grid are provided with interlayer dielectric layer, described interlayer dielectric layer is provided with the first via hole and the second via hole, described source electrode is connected with described active layer by described first via hole, described drain electrode is connected with described active layer by described second via hole.
5. display base plate according to claim 3, it is characterized in that, described first grid line and first grid are arranged on described underlay substrate, described active layer is arranged on described first grid insulating barrier, described active layer is provided with second gate insulating barrier, described second gate insulating barrier is provided with interlayer dielectric layer, described interlayer dielectric layer is provided with the first via hole and the second via hole, described source electrode is connected with described active layer by described first via hole, and described drain electrode is connected with described active layer by described second via hole.
6. a display unit, is characterized in that, comprises the arbitrary described display base plate of claim 1 to 5.
7. a preparation method for display base plate, is characterized in that, comprising:
Underlay substrate is formed shading metal level, and described shading metal level comprises the first grid line and light shield layer;
Above described light shield layer, correspondence position forms the second grid line;
Form data wire, pixel electrode and thin-film transistor, the pixel cell that described first grid line, the second grid line and data wire limit comprises pixel electrode and thin-film transistor.
8. the preparation method of display base plate according to claim 7, is characterized in that, described on underlay substrate, form the step of shading metal level after comprise:
Described shading metal level forms insulating barrier, and described insulating barrier comprises resilient coating and first grid insulating barrier;
The described step forming insulating barrier on described shading metal level comprises:
Described light shield layer forms resilient coating, described first grid line forms first grid insulating barrier.
9. the preparation method of display base plate according to claim 8, it is characterized in that, described thin-film transistor includes active layer, source electrode, drain electrode, first grid or second grid, and the constituent material of described active layer comprises polysilicon, amorphous silicon or metal oxide.
10. the preparation method of display base plate according to claim 9, is characterized in that, described on described light shield layer, form the step of resilient coating after comprise:
Described resilient coating forms described active layer;
Described active layer is formed second gate insulating barrier;
The described step that correspondence position forms the second grid line above described light shield layer comprises:
While described second gate insulating barrier forms the second grid line, described second gate insulating barrier forms second grid;
Described on described second gate insulating barrier, form the second grid line while, comprise after described second gate insulating barrier forms the step of second grid:
Described second grid line and second grid form interlayer dielectric layer, described interlayer dielectric layer is formed with the first via hole and the second via hole;
Described interlayer dielectric layer is formed described source electrode and described drain electrode, and described source electrode is connected with described active layer by described first via hole, and described drain electrode is connected with described active layer by described second via hole.
The preparation method of 11. display base plates according to claim 9, is characterized in that, the described step forming shading metal level on underlay substrate comprises:
While described underlay substrate is formed the first grid line, described underlay substrate forms first grid;
Described on described first grid line, form the step of first grid insulating barrier after comprise:
Described first grid insulating barrier forms described active layer;
Described active layer is formed second gate insulating barrier;
Described second gate insulating barrier forms interlayer dielectric layer, described interlayer dielectric layer is formed with the first via hole and the second via hole;
Described interlayer dielectric layer is formed described source electrode and described drain electrode, and described source electrode is connected with described active layer by described first via hole, and described drain electrode is connected with described active layer by described second via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510252987.0A CN104952885A (en) | 2015-05-18 | 2015-05-18 | Display baseplate, manufacturing method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510252987.0A CN104952885A (en) | 2015-05-18 | 2015-05-18 | Display baseplate, manufacturing method thereof and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104952885A true CN104952885A (en) | 2015-09-30 |
Family
ID=54167429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510252987.0A Pending CN104952885A (en) | 2015-05-18 | 2015-05-18 | Display baseplate, manufacturing method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104952885A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105514126A (en) * | 2016-02-19 | 2016-04-20 | 京东方科技集团股份有限公司 | Array base plate and manufacturing method and display device thereof |
| CN106611775A (en) * | 2015-10-27 | 2017-05-03 | 三星显示有限公司 | Organic light-emitting diode display |
| CN107275334A (en) * | 2016-04-08 | 2017-10-20 | 群创光电股份有限公司 | Display device |
| CN108535925A (en) * | 2018-03-20 | 2018-09-14 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108538860A (en) * | 2018-04-27 | 2018-09-14 | 武汉华星光电技术有限公司 | The production method of top gate type amorphous-silicon TFT substrate |
| CN110444548A (en) * | 2019-01-08 | 2019-11-12 | 友达光电股份有限公司 | Dot structure |
| CN110867454A (en) * | 2018-08-28 | 2020-03-06 | 三星显示有限公司 | Organic light emitting display device |
| WO2020155107A1 (en) * | 2019-02-01 | 2020-08-06 | 深圳市柔宇科技有限公司 | Thin film transistor and manufacturing method therefor, driver circuit, and display screen |
| WO2022160421A1 (en) * | 2021-01-27 | 2022-08-04 | 武汉华星光电技术有限公司 | Display panel and liquid crystal display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1312590A (en) * | 2000-02-01 | 2001-09-12 | 株式会社半导体能源研究所 | Semiconductor device and producing method thereof |
| CN101706634A (en) * | 2009-03-13 | 2010-05-12 | 深超光电（深圳）有限公司 | Pixel design layout structure with high aperture |
| CN102736340A (en) * | 2011-04-01 | 2012-10-17 | 精工爱普生株式会社 | Electro-optic device, electronic device, and method of manufacturing electro-optic device |
| CN103499906A (en) * | 2013-10-15 | 2014-01-08 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
-
2015
- 2015-05-18 CN CN201510252987.0A patent/CN104952885A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1312590A (en) * | 2000-02-01 | 2001-09-12 | 株式会社半导体能源研究所 | Semiconductor device and producing method thereof |
| CN101706634A (en) * | 2009-03-13 | 2010-05-12 | 深超光电（深圳）有限公司 | Pixel design layout structure with high aperture |
| CN102736340A (en) * | 2011-04-01 | 2012-10-17 | 精工爱普生株式会社 | Electro-optic device, electronic device, and method of manufacturing electro-optic device |
| CN103499906A (en) * | 2013-10-15 | 2014-01-08 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106611775A (en) * | 2015-10-27 | 2017-05-03 | 三星显示有限公司 | Organic light-emitting diode display |
| CN106611775B (en) * | 2015-10-27 | 2022-02-22 | 三星显示有限公司 | Organic light emitting diode display |
| CN105514126A (en) * | 2016-02-19 | 2016-04-20 | 京东方科技集团股份有限公司 | Array base plate and manufacturing method and display device thereof |
| CN105514126B (en) * | 2016-02-19 | 2019-01-22 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN107275334A (en) * | 2016-04-08 | 2017-10-20 | 群创光电股份有限公司 | Display device |
| CN108535925A (en) * | 2018-03-20 | 2018-09-14 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108538860A (en) * | 2018-04-27 | 2018-09-14 | 武汉华星光电技术有限公司 | The production method of top gate type amorphous-silicon TFT substrate |
| CN110867454A (en) * | 2018-08-28 | 2020-03-06 | 三星显示有限公司 | Organic light emitting display device |
| CN110444548A (en) * | 2019-01-08 | 2019-11-12 | 友达光电股份有限公司 | Dot structure |
| WO2020155107A1 (en) * | 2019-02-01 | 2020-08-06 | 深圳市柔宇科技有限公司 | Thin film transistor and manufacturing method therefor, driver circuit, and display screen |
| CN113261103A (en) * | 2019-02-01 | 2021-08-13 | 深圳市柔宇科技股份有限公司 | Thin film transistor, manufacturing method thereof, driving circuit and display screen |
| WO2022160421A1 (en) * | 2021-01-27 | 2022-08-04 | 武汉华星光电技术有限公司 | Display panel and liquid crystal display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104952885A (en) | Display baseplate, manufacturing method thereof and display device | |
| CN108231795B (en) | Array substrate, manufacturing method, display panel and display device | |
| US9880439B2 (en) | Array substrate, method for manufacturing the same, and display device | |
| CN105489552B (en) | The production method of LTPS array substrates | |
| CN102636927B (en) | Array base palte and manufacture method thereof | |
| CN103268878B (en) | The manufacture method of tft array substrate, tft array substrate and display unit | |
| WO2017128557A1 (en) | Array substrate and liquid crystal display device | |
| CN105702623B (en) | The production method of tft array substrate | |
| US9530800B2 (en) | Array substrate, display panel and method for preparing array substrate | |
| CN202631914U (en) | Array substrate and display equipment | |
| CN102683353B (en) | Array substrate for display device and producing method of array substrate | |
| WO2016086531A1 (en) | Array substrate and manufacturing method therefor | |
| CN108695394A (en) | Thin film transistor (TFT), preparation method, array substrate and display device | |
| CN102929060B (en) | Array substrate, fabrication method of array substrate, and display device | |
| CN105470197A (en) | Production method of low temperature poly silicon array substrate | |
| CN105390551A (en) | Thin film transistor, manufacturing method thereof, array substrate, and display device | |
| CN104091831A (en) | Thin film transistor, array substrate and display device | |
| CN104681631A (en) | Thin film transistor and manufacturing method thereof as well as array substrate and display device | |
| CN105097829B (en) | Array base palte and preparation method thereof | |
| CN105529366A (en) | Metal oxide thin film transistor and manufacturing method thereof | |
| CN203870366U (en) | Array substrate and display device | |
| CN101840121A (en) | Array substrate and manufacturing method thereof | |
| CN104810375B (en) | A kind of array substrate and preparation method thereof and a kind of display device | |
| CN107112365A (en) | Semiconductor device | |
| CN203932068U (en) | A kind of thin-film transistor, array base palte and display unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150930 |
|
| RJ01 | Rejection of invention patent application after publication |