CN102656673B - 晶片结构的电耦合 - Google Patents
晶片结构的电耦合 Download PDFInfo
- Publication number
- CN102656673B CN102656673B CN201080056932.8A CN201080056932A CN102656673B CN 102656673 B CN102656673 B CN 102656673B CN 201080056932 A CN201080056932 A CN 201080056932A CN 102656673 B CN102656673 B CN 102656673B
- Authority
- CN
- China
- Prior art keywords
- wafer
- opening
- width
- lid
- tube core
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000008878 coupling Effects 0.000 title claims abstract description 26
- 238000010168 coupling process Methods 0.000 title claims abstract description 26
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 239000000428 dust Substances 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 124
- 239000004065 semiconductor Substances 0.000 description 16
- 239000004020 conductor Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005194 fractionation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 208000002925 dental caries Diseases 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/097—Interconnects arranged on the substrate or the lid, and covered by the package seal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
- H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/166—Material
- H01L2924/167—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/166—Material
- H01L2924/16786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/16788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Micromachines (AREA)
- Dicing (AREA)
Abstract
提供了一种用于使第一晶片(105)与第二晶片(103)电耦合的方法。该方法包括使用接合材料(121)来使第一晶片与第二晶片接合。该方法还包括在第一晶片中在第二晶片的划线区(141或143)内形成开口(201或203)以使第二晶片的导电结构(108或112)的表面露出。该方法还包括形成覆盖于第一晶片及第一晶片内的开口之上的导电层,使得导电层与第二晶片的导电结构(108或112)形成电接触,从而使第一晶片与第二晶片电耦合。
Description
技术领域
本发明总体上涉及半导体器件,并且特别地涉及两个晶片的结构的电耦合。
背景技术
某些半导体器件(例如,MEMS半导体器件)使用盖晶片(capwafer)来为MEMS器件在操作期间提供保护腔体。MEMS器件是在某些实施例中通常以半导体器件工艺来制造的微机电器件。MEMS器件的实例包括加速度计、传感器、微电机和开关。在某些实例中,MEMS器件包括在操作期间移动的部件(例如,检测质量块)。由于该移动,腔体被用来在允许部件移动的同时保护该部件。
腔体能够通过在盖晶片内形成开口并且将盖晶片接合至器件晶片来实现,其中开口覆盖于MEMS器件之上。然后,盖晶片和器件晶片被拆分以形成MEMS管芯。
在某些实例中,有关实现盖晶片的一个问题是需要与器件晶片间的良好接地耦合。在某些实例中,接地耦合通过从盖晶片到器件晶片的导线接合、穿过盖晶片到器件晶片的导电通路或者在盖晶片与器件晶片之间的导电接合材料来实现。
附图说明
通过参考附图,本发明可以更好地理解,并且本领域技术人员可以更清楚本发明众多的目的、特征及优点。
图1-6给出了根据本发明的实施例在制造具有盖晶片结构的半导体器件中的各个阶段的视图。
除非另有说明,在不同附图中使用相同的附图标记来指示相同的项目。附图并不一定按比例来绘制。例如,在附图中所示出的结构的宽高比可以偏移,以便更清晰地示出本发明的各方面。
具体实施方式
下面给出了关于本发明的实施方式的详细描述。该描述是用来说明本发明的,而不应当被认为是对本发明的限定。
如本文所述,在一种实施例中,从盖晶片结构到器件晶片结构的电耦合通过以下方式来实现:在划线区(scribe area)内在盖晶片中形成到器件晶片的导电结构的开口并且然后在盖晶片之上(包括在开口内以及在开口的侧壁上)形成导电层,其中导电层接触器件晶片的导电结构。然后,盖晶片和器件晶片在划线区内被拆分,使得在开口侧壁上的导电材料保留,以用于使盖晶片结构和器件晶片结构电耦合。
图1是所得晶片101的局部截面侧视图,该所得晶片101包括以接合材料121与盖晶片105接合的器件晶片102。在一种实施例中,接合材料121是不导电的玻璃粉。但是,在其他实施例中,可以使用诸如导电玻璃粉(例如,具有诸如铅之类的导电材料)或焊料之类的其他类型的接合材料。在一种实施例中,晶片在温度和压力下接合在一起达一段时间,以在两个晶片之间提供坚实的机械接合。在一种实施例中,接合是气密性接合。
器件晶片102包括位于基板103上的多个半导体器件(107、109、110),该多个半导体器件(107、109、110)在晶片102与晶片105接合之前形成。在一种实施例中,这些器件包括由半导体、导电的和/或电介质材料制成的结构,该结构由半导体制造工艺形成。器件107、109和110可以包括已经被处理成形成不同结构的多层不同的材料。在一种实施例中,器件107、109和110是多轴加速度计,而在其他实施例中,器件107、109和110可以是其他类型的MEMS器件,例如,其他类型的加速度计、传感器、电机或开关。此外,在其他实施例中,器件107、109和110可以是其他类型的半导体器件,例如,集成电路、独立器件或传感器。在一种实施例中,器件107、109和110通过在基板103上形成和处理不同的层来形成。
晶片102包括用于将器件107、109和110向外耦合至外部器件(例如,在集成电路管芯上)以将信号传送给那些外部器件的焊盘(113和115)。焊盘113和115由导电材料(例如,铜、铝、金)制成,所述导电材料在一种实施例中可导线接合。焊盘113和115分别位于多晶硅结构114和116上并且分别与它们电接触。在一种实施例中,基板103包括用于使半导体器件(107、109和110)的导电结构与焊盘支撑结构(114和116)电耦合的多个导电结构(没有示出)。例如,器件107与结构114电耦合,以及器件109与结构116电耦合。
在一种实施例中,基板103包括半导体材料(例如,硅),导电结构和电介质结构位于其中的层内。在某些实施例中,半导体材料的某些部分被选择性地掺杂以成为导电性的。但是,晶片102在其他实施例中可以具有其他配置。
器件晶片102包括包含位于划线区141和143内的部分的划线导电结构108和112。划线区是晶片中位于将在拆分期间分离的晶片的器件区之间的并且包括分离路径的区域。结构108和112由诸如多晶硅或金属之类的导电材料制成。每个划线结构(108和112)通过位于基板103内的导电结构(没有示出)与(器件107、109和110中的)两个器件电耦合。例如,导电结构112与器件109和器件110电耦合。
晶片102还包括位于器件与焊盘区之间的导电结构124和126,用于接合盖晶片以为器件107和109提供密封。
在一种实施例中,盖晶片105由半导体材料(例如,硅)制成,并且包括用于为器件晶片102的结构形成腔体的开131、133、135和137(例如,通过蚀刻形成的)。在一种实施例中,在晶片105贴附于晶片102之后,晶片105的顶面被磨削并被抛光以减小晶片105的厚度。在一种实施例中,晶片105被磨削至范围为100-400μm的减小的厚度。但是,在其他实施例中,盖可以被磨削至其他厚度或者可以一点也不磨削。在某些实施例中,盖晶片105可以包括器件,例如,MEMS器件或者形成于其上的其他半导体器件。在一种实施例中,晶片105不包括开口131、133、135和137。
图2是所得晶片101在开口(201和203)形成于晶片105内以使在晶片102的划线区内的导电结构(108和112)露出之后的局部截面侧视图。在一种实施例中,使开口达到确保晶片105和接合材料121从结构108和112之上的位置去除以使导电结构露出的深度。该切割可以包括去除结构108和112的顶部部分。在一种实施例中,开口用锯来形成。在所示出的实施例中,开口201和203具有80微米的宽度205和207,但是在其他实施例中可以是其他宽度。
在其他实施例中,接合材料121不会形成于开口201和203的区域内。在这些区域中,会存在位于盖晶片105和划线导电结构(108和112)之间的空隙。但是,在这些区域内形成接合材料可以提供开口的平齐侧壁,因为接合材料位于划线导电结构(108和112)与盖晶片105之间。平齐的侧壁使得导电层随后更好地形成于侧壁上。
在其他实施例中,开口201和203可以通过其他方法来形成,例如,通过复齿锯切割(double saw cut),通过激光或者通过蚀刻。
图3是所得晶片101在导电层301形成于晶片101上之后的局部截面侧视图。在一种实施例中,层301由金属(例如,铜、铝或金)制成。在一种实施例中,层具有2微米的厚度,但是在其他实施例中可以具有其他厚度。层301被形成为在开口201和203的侧壁上具有良好的台阶覆盖,以提供用于良好的电传导的通路。在一种实施例中,层301通过金属淀积工艺来形成,例如,化学气相淀积工艺、物理气相淀积工艺、电镀工艺或其他金属形成工艺。在一种实施例中,层301可以包括多层不同的材料。
图4是所得晶片101在开口(401)形成于焊盘(113和115)之上以使焊盘为了后续的测试而露出之后的局部截面侧视图。在一种实施例中,开口401以复齿锯切割来形成,但是在其他实施例中可以通过其他方法(例如,蚀刻)来形成。在形成了开口之后,晶片101经受清洁处理(例如,灰化)以去除不想要的有机材料。然后,器件(107、109和110)使用与所露出的焊盘(113和115)接触的测试探针来测试可操作性。
图5是所得晶片101被拆分成分离的管芯(529、521、523和527)之后的局部截面侧视图。在一种实施例中,拆分通过在划线区(141和143)内和在焊盘(例如,114和116)之间切割晶片101来完成。在一种实施例中,晶片用锯、激光或其他晶片切割工具来切割。在其他实施例中,拆分能够通过在划线区内蚀刻晶片101来执行。每个管芯(529、521、523和527)包括位于腔体(由开口131、135和137形成)内的半导体器件(107、109和110)。在一种实施例中,这些腔体在晶片102接合至晶片105时被气密性地密封。
在所示出的实施例中,锯切路径(501、503和515)具有大约为40-50微米宽的宽度(507、509和511),但是在其他实施例中能够是其他宽度的。这些锯切路径的宽度(507、509和511)小于先前形成的开口(201和203)的宽度(205和207)。因此,层301的某些部分保留于开口201和203的侧面上,以提供导电通路,所述导电通路用于使晶片105中用于每个管芯的部分与在拆分之后保留下来的其对应的导电划线结构(108和112)电耦合。
在所示出的实施例中,划线导电结构(112、108)的保留部分与诸如结构124和126之类的导电结构一起形成了密封环,以密封每个管芯的腔体。
图6是在拆分后的管芯523的顶视图。在所示出的实施例中,层301覆盖着管芯523除了由用于使焊盘115、605和607露出的开口401形成的那部分之外的整个顶部。在所示出的实施例中,层301覆盖着由开口(例如,201和203)形成于划线区之上的三个侧壁(541、603和601)。因此,对于所示出的实施例,存在着相对大量的将两个晶片部分耦合在一起的导电材料。在其他实施例中,层301的形状和覆盖率可以是不同的。例如,它可以仅覆盖盖晶片结构的侧壁的一部分或者覆盖盖晶片结构的全部四个侧面。此外,在层301的顶面内可以存在用于其他外部导体的开口。
所得管芯然后能够进一步单独地或者与其他集成电路管芯一起封装(例如在密封剂中)。层301可以与封装的接地端子电耦合。所得封装然后能够应用于各种电子***内。
在两个接合晶片之间提供电连接包括在划线区内形成开口以及然后形成覆盖(plate)开口的导电层,与其他常规的技术相比,这可以提供两个晶片之间更高效及更可靠的电耦合。因为这两个晶片的电耦合由导电层来实现,所以晶片接合材料121能够针对其接合性质来选择,而与其导电性质无关。
此外,通过此类实施例,对于两个晶片之间的接地耦合(groundcoupling),不需要导线接合。这还可以降低后续封装的总高度,因为盖晶片接地导线接合通常被制作于盖晶片的顶表面。
而且,在相对大的开口的侧壁上形成导电层在技术上比在盖晶片内形成穿过相对小的开口的导电通路更容易。此外,因为层301能够被配置用于覆盖划线区中包围着管芯的大部分(例如,图6所示的3个侧面),所以内部的器件区不需要导线接合或通路形成。而且,将需要多个导线接合和导电通路来获得数量与位于盖晶片结构的侧壁上的导电材料相同的导电材料,以使晶片电耦合。
在其他实施例中,初始划线开口(201和203)能够从器件晶片102的底部来制作,以使盖晶片105的导电表面露出。导电层301然后被形成于器件晶片102的底面上,并且在开口内扩展以接触盖晶片105的裸露导电表面。通过该实施例,器件晶片102的底部在晶片接合之后可以被向下磨削以减小厚度。
本发明的一种实施例包括一种用于使第一晶片与第二晶片电耦合的方法。该方法包括使第一晶片与第二晶片接合,在第一晶片中在第二晶片的划线区中形成开口以使第二晶片的导电结构的表面露出,以及形成覆盖于第一晶片及第一晶片内的开口之上的导电层,使得导电层与第二晶片的导电结构形成电接触,从而使第一晶片与第二晶片电耦合。
另一种实施例包括一种用于使盖晶片与器件晶片电耦合的方法。该方法包括使用接合材料来使盖晶片与器件晶片接合。器件晶片包括基板。该方法包括在盖晶片以及器件晶片的划线区内的接合材料中形成开口,以使器件晶片的导电结构的表面露出。形成穿过盖晶片和接合材料的开口包括锯切穿过盖晶片以及器件晶片的划线区内的接合材料。该方法包括形成覆盖于盖晶片及盖晶片内的开口之上的导电层,使得导电层与器件晶片的导电结构形成电接触,从而使盖晶片与器件晶片电耦合。
另一种实施例包括一种用于使第一晶片与第二晶片电耦合的方法。该方法包括使用接合材料来使第一晶片与第二晶片接合,在第一晶片以及第二晶片的划线区内的接合材料中形成开口以使第二晶片的导电结构的表面露出,以及形成覆盖于第一晶片及第一晶片内的开口之上的导电层,使得导电层与第二晶片的导电结构形成电接触,从而使第一晶片与第二晶片电耦合。该方法包括将所接合的晶片分离成多个管芯。该分离包括去除第二晶片的分离路径的材料,该分离路径具有第一宽度。开口具有第二宽度,以及第一宽度和第二宽度被选择成使得导电层的至少一部分保留于分离的管芯的至少一个侧壁上,并从而提供第一晶片与第二晶片之间的电耦合。
虽然已经示出并描述了本发明的特定实施例,但是本领域技术人员应当认识到,基于本文的教导,在不脱离本发明及其更宽泛的方面的情况下可以进行进一步的改变和修改,因而,所附的权利要求应当包含于属于本发明的真正精神和范围的所有改变和修改的范围之内。
Claims (19)
1.一种用于使第一晶片与第二晶片电耦合的方法,所述方法包括:
使所述第一晶片与所述第二晶片接合;
在所述第一晶片中在所述第二晶片的划线区内形成开口以使得所述第二晶片的导电结构的表面露出;以及
形成覆盖于所述第一晶片及所述第一晶片中的所述开口之上的导电层,使得所述导电层与所述第二晶片的导电结构形成电接触,从而使所述第一晶片与所述第二晶片电耦合;
所述方法还包括:将所接合的第一和第二晶片分离成多个管芯,其中所述分离包括去除所述第二晶片的分离路径的材料,所述分离路径具有第一宽度,其中所述开口具有第二宽度,以及其中所述第一宽度和所述第二宽度被选择成使得所述导电层的至少一部分保留在所分离的管芯的至少一个侧壁上,从而提供所述第一晶片与所述第二晶片之间的电耦合。
2.根据权利要求1所述的方法,其中所述第二晶片包括多个焊盘,以及所述方法还包括在所述第一晶片内形成所述开口之后在所述第一晶片内形成第二开口,以使所述多个焊盘露出。
3.根据权利要求1所述的方法,其中在所述第一晶片中形成所述开口包括在所述第二晶片的所述划线区内锯切穿过所述第一晶片。
4.根据权利要求1所述的方法,其中使所述第一晶片与所述第二晶片接合包括使用接合材料来使所述第一晶片与所述第二晶片接合,其中形成所述开口包括在所述接合材料中形成开口。
5.根据权利要求1所述的方法,其中所述第二晶片包含至少一个微机电***(MEMS)器件。
6.根据权利要求1所述的方法,还包括锯切穿过所述第二晶片以将所接合的第一和第二晶片分离成多个管芯,其中所述锯切包括在所述划线区内锯切穿过锯切路径。
7.根据权利要求1所述的方法,其中所述第二宽度比所述第一宽度宽。
8.一种用于使盖晶片与器件晶片电耦合的方法,所述方法包括:
使用接合材料来使所述盖晶片与所述器件晶片接合,其中所述器件晶片包括基板;
在所述盖晶片以及所述器件晶片的划线区内的所述接合材料中形成开口,以使所述器件晶片的导电结构的表面露出,其中在所述盖晶片和所述接合材料中形成所述开口包括锯切穿过所述盖晶片以及所述器件晶片的所述划线区内的接合材料;以及
形成覆盖于所述盖晶片及所述盖晶片内的所述开口之上的导电层,使得所述导电层与所述器件晶片的所述导电结构形成电接触,从而使所述盖晶片与所述器件晶片电耦合。
9.根据权利要求8所述的方法,其中所述器件晶片包括多个焊盘,以及所述方法还包括在所述盖晶片内形成所述开口之后在所述盖晶片内形成第二开口,以使所述多个焊盘露出。
10.根据权利要求8所述的方法,其中所述器件晶片包含至少一个微机电***(MEMS)器件。
11.根据权利要求8所述的方法,还包括锯切穿过所述器件晶片以将所接合的晶片分离成多个管芯,以及其中所述多个管芯中的每一个都包含至少一个微机电***(MEMS)器件。
12.根据权利要求8所述的方法,还包括将所接合的晶片分离成多个管芯,其中所述分离包括去除在所述划线区内的所述器件晶片的分离路径的材料,所述分离路径具有第一宽度,其中所述开口具有第二宽度,以及其中所述第一宽度和所述第二宽度被选择成使得所述导电层的至少一部分保留于所分离的管芯的至少一个侧壁上,由此继续提供所述盖晶片与所述器件晶片之间的电耦合。
13.根据权利要求8所述的方法,其中所述接合材料是非导电的。
14.根据权利要求13所述的方法,其中所述非导电的接合材料是玻璃粉。
15.一种用于使第一晶片与第二晶片电耦合的方法,所述方法包括:
使用接合材料来使所述第一晶片与所述第二晶片接合,以形成接合的晶片;
在所述第一晶片以及所述第二晶片的划线区内的接合材料中形成开口以使所述第二晶片的导电结构的表面露出;
形成覆盖于所述第一晶片及所述第一晶片内的所述开口之上的导电层,使得所述导电层与所述第二晶片的所述导电结构形成电接触,从而使所述第一晶片与所述第二晶片电耦合;以及
将接合的晶片分离成多个管芯,其中所述分离包括去除所述第二晶片的分离路径的材料,所述分离路径具有第一宽度,其中所述开口具有第二宽度,以及其中所述第一宽度和所述第二宽度被选择成使得所述导电层的至少一部分保留于所分离的管芯的至少一个侧壁上,从而提供所述第一晶片与所述第二晶片之间的电耦合。
16.根据权利要求15所述的方法,其中所述第二晶片包括多个焊盘,以及所述方法还包括在所述第一晶片内形成所述开口之后在所述第一晶片内形成第二开口,以使所述多个焊盘露出。
17.根据权利要求15所述的方法,其中所述多个管芯中的每一个都包括由所述第一晶片的结构的表面和所述第二晶片的结构的表面界定的腔体。
18.根据权利要求17所述的方法,其中所述第二晶片包含多个微机电***(MEMS)器件。
19.根据权利要求15所述的方法,其中所述接合材料是非导电的玻璃粉。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/638,424 US8138062B2 (en) | 2009-12-15 | 2009-12-15 | Electrical coupling of wafer structures |
US12/638,424 | 2009-12-15 | ||
PCT/US2010/057624 WO2011081741A2 (en) | 2009-12-15 | 2010-11-22 | Electrical coupling of wafer structures |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102656673A CN102656673A (zh) | 2012-09-05 |
CN102656673B true CN102656673B (zh) | 2015-05-20 |
Family
ID=44143393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201080056932.8A Expired - Fee Related CN102656673B (zh) | 2009-12-15 | 2010-11-22 | 晶片结构的电耦合 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8138062B2 (zh) |
JP (1) | JP5721742B2 (zh) |
CN (1) | CN102656673B (zh) |
TW (1) | TWI555069B (zh) |
WO (1) | WO2011081741A2 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8637981B2 (en) | 2011-03-30 | 2014-01-28 | International Rectifier Corporation | Dual compartment semiconductor package with temperature sensor |
US8633088B2 (en) | 2012-04-30 | 2014-01-21 | Freescale Semiconductor, Inc. | Glass frit wafer bond protective structure |
US9327965B2 (en) | 2013-03-15 | 2016-05-03 | Versana Micro Inc | Transportation device having a monolithically integrated multi-sensor device on a semiconductor substrate and method therefor |
CN103466541B (zh) * | 2013-09-12 | 2016-01-27 | 上海矽睿科技有限公司 | 晶圆级封装方法以及晶圆 |
US9630832B2 (en) * | 2013-12-19 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing |
US9826630B2 (en) | 2014-09-04 | 2017-11-21 | Nxp Usa, Inc. | Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof |
KR20180032985A (ko) * | 2016-09-23 | 2018-04-02 | 삼성전자주식회사 | 집적회로 패키지 및 그 제조 방법과 집적회로 패키지를 포함하는 웨어러블 디바이스 |
CN107827079B (zh) * | 2017-11-17 | 2019-09-20 | 烟台睿创微纳技术股份有限公司 | 一种mems芯片的制作方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1346949A2 (en) * | 2002-03-06 | 2003-09-24 | Robert Bosch Gmbh | Si wafer-cap wafer bonding method using local laser energy, device produced by the method, and system used in the method |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3613838B2 (ja) | 1995-05-18 | 2005-01-26 | 株式会社デンソー | 半導体装置の製造方法 |
SG111972A1 (en) | 2002-10-17 | 2005-06-29 | Agency Science Tech & Res | Wafer-level package for micro-electro-mechanical systems |
JP3905041B2 (ja) * | 2003-01-07 | 2007-04-18 | 株式会社日立製作所 | 電子デバイスおよびその製造方法 |
US20040166662A1 (en) | 2003-02-21 | 2004-08-26 | Aptos Corporation | MEMS wafer level chip scale package |
JP4551638B2 (ja) * | 2003-08-01 | 2010-09-29 | 富士フイルム株式会社 | 固体撮像装置の製造方法 |
DE10350460B4 (de) * | 2003-10-29 | 2006-07-13 | X-Fab Semiconductor Foundries Ag | Verfahren zur Herstellung von mikromechanische und/ oder mikroelektronische Strukturen aufweisenden Halbleiterbauelementen, die durch das feste Verbinden von mindestens zwei Halbleiterscheiben entstehen, und entsprechende Anordnung |
US7034393B2 (en) | 2003-12-15 | 2006-04-25 | Analog Devices, Inc. | Semiconductor assembly with conductive rim and method of producing the same |
TWI236111B (en) * | 2004-06-30 | 2005-07-11 | Ind Tech Res Inst | Apparatus and method for wafer level packaging |
US7495462B2 (en) | 2005-03-24 | 2009-02-24 | Memsic, Inc. | Method of wafer-level packaging using low-aspect ratio through-wafer holes |
TWI295081B (en) * | 2006-01-12 | 2008-03-21 | Touch Micro System Tech | Method for wafer level package and fabricating cap structures |
US20080131662A1 (en) * | 2006-12-05 | 2008-06-05 | Jordan Larry L | Alignment of a cap to a MEMS wafer |
US20080191334A1 (en) | 2007-02-12 | 2008-08-14 | Visera Technologies Company Limited | Glass dam structures for imaging devices chip scale package |
US20080290430A1 (en) * | 2007-05-25 | 2008-11-27 | Freescale Semiconductor, Inc. | Stress-Isolated MEMS Device and Method Therefor |
-
2009
- 2009-12-15 US US12/638,424 patent/US8138062B2/en not_active Expired - Fee Related
-
2010
- 2010-11-22 CN CN201080056932.8A patent/CN102656673B/zh not_active Expired - Fee Related
- 2010-11-22 WO PCT/US2010/057624 patent/WO2011081741A2/en active Application Filing
- 2010-11-22 JP JP2012544551A patent/JP5721742B2/ja not_active Expired - Fee Related
- 2010-12-06 TW TW099142440A patent/TWI555069B/zh not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1346949A2 (en) * | 2002-03-06 | 2003-09-24 | Robert Bosch Gmbh | Si wafer-cap wafer bonding method using local laser energy, device produced by the method, and system used in the method |
Also Published As
Publication number | Publication date |
---|---|
WO2011081741A2 (en) | 2011-07-07 |
CN102656673A (zh) | 2012-09-05 |
US20110143476A1 (en) | 2011-06-16 |
US8138062B2 (en) | 2012-03-20 |
TW201128691A (en) | 2011-08-16 |
JP2013513971A (ja) | 2013-04-22 |
WO2011081741A3 (en) | 2011-09-09 |
JP5721742B2 (ja) | 2015-05-20 |
TWI555069B (zh) | 2016-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102656673B (zh) | 晶片结构的电耦合 | |
CN102751266B (zh) | 芯片封装体及其形成方法 | |
CN102398888A (zh) | 晶圆级封装 | |
US9212050B2 (en) | Cap and substrate electrical connection at wafer level | |
CN104716050A (zh) | 具有模塑通孔的半导体器件 | |
US11078075B2 (en) | Packaging method and associated packaging structure | |
CN104900616A (zh) | 晶片封装体及其制造方法 | |
CN102832180B (zh) | 晶片封装体及其形成方法 | |
CN102543922A (zh) | 晶片封装体及其形成方法 | |
CN105023909A (zh) | 提供再分布层(rdl)和硅通孔(tsv)的结构和方法 | |
CN105271100A (zh) | 用于气密密封的薄膜结构 | |
US8502382B2 (en) | MEMS and protection structure thereof | |
US7911043B2 (en) | Wafer level device package with sealing line having electroconductive pattern and method of packaging the same | |
CN105776123A (zh) | 微机电***元件及其制造方法 | |
CN102779800A (zh) | 晶片封装体及其形成方法 | |
CN107697882B (zh) | 用于制造半导体器件的工艺以及相应半导体器件 | |
CN103489842B (zh) | 半导体封装结构 | |
CN103435000A (zh) | 集成mems器件的传感器的晶圆级封装结构及封装方法 | |
CN103723674B (zh) | Mems晶体管及其制造方法 | |
CN103489804B (zh) | 半导体封装结构的形成方法 | |
CN102779809B (zh) | 晶片封装体及其形成方法 | |
CN110034064A (zh) | 半导体结构及其形成方法 | |
US7696083B2 (en) | Multi-layer device | |
CN109802031B (zh) | 一种声表面波器件的封装方法及结构 | |
US12015001B2 (en) | Bonding structure and method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150520 Termination date: 20191122 |
|
CF01 | Termination of patent right due to non-payment of annual fee |