CN102655095A - 薄膜晶体管及阵列基板的制造方法 - Google Patents

薄膜晶体管及阵列基板的制造方法 Download PDF

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CN102655095A
CN102655095A CN2011101471342A CN201110147134A CN102655095A CN 102655095 A CN102655095 A CN 102655095A CN 2011101471342 A CN2011101471342 A CN 2011101471342A CN 201110147134 A CN201110147134 A CN 201110147134A CN 102655095 A CN102655095 A CN 102655095A
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film transistor
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exposure
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layer
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CN102655095B (zh
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周伟峰
薛建设
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BOE Technology Group Co Ltd
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Abstract

本发明公开了一种薄膜晶体管及阵列基板的制造方法，涉及薄膜晶体管液晶显示技术领域，解决了现有底栅顶接触结构薄膜晶体管制造工艺中所使用的掩膜版套数较多，导致该薄膜晶体管制造成本较高的问题。本发明实施例在制造薄膜晶体管时，由于用于制备源/漏电极和图案化有源层的掩膜版上具有对应沟道区域的宽度小于曝光机分辨率的缝隙，通过增大曝光量，可正常形成源/漏电极；再使用该掩膜版，通过减小曝光量，可形成所需形状的有源层。由于形成源/漏电极及图案化有源层时共用一套掩膜版，因此，降低了薄膜晶体管及阵列基板的制造成本。本发明实施例主要用于制备液晶显示器或电子纸显示器。

Description

薄膜晶体管及阵列基板的制造方法
技术领域
本发明涉及薄膜晶体管液晶显示技术领域，尤其涉及薄膜晶体管及阵列基板的制造方法。
背景技术
随着平板显示产品生产的不断扩大，各个生产厂商之间的竞争也日趋激烈。各厂家在不断提高产品性能的同时，也在不断努力降低产品的生产成本，从而提高市场的竞争力。
TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器)作为家喻户晓的平板显示产品，降低生产成本也是其技术革新的一个重要方面。
TFT(Thin Film Transistor，薄膜晶体管)是TFT-LCD阵列基板的重要组成部分，通常采用图1A所示的底栅顶接触结构。图1A所示的形成在基板上的TFT从下至上依次包括：栅电极、栅极绝缘层、有源层、源电极及漏电极。
在使用图1A所示的TFT时，发明人发现现有技术中至少存在如下问题：由于载流子的导通层在栅极绝缘层与有源层的界面处，因此，电子必须两次穿越有源层才能在源电极与漏电极之间传输，从而影响了TFT的导电性能。
如果采用如图1B所示的底栅底接触结构的TFT，电子从源电极传输到漏电极，需要移动的距离仅为一个沟道的长度，远小于底栅顶接触结构的TFT中电子需要移动的距离，因此，可避免TFT导电性能受到影响。
但制备底栅底接触结构的TFT时，无法使用现有的制备底栅顶接触结构的TFT时采用的四掩膜工艺(在形成源/漏电极和图案化有源层时，共用一套掩膜版)，需要多设计一套掩膜版，即形成源/漏电极和图案化有源层时，需使用不同的掩膜版。由于掩膜版的价格很高，多设计一套掩膜版会导致TFT的制造成本升高。
发明内容
本发明的实施例提供一种薄膜晶体管及阵列基板的制造方法，能降低底栅底接触结构的TFT的制造成本。
为达到上述目的，本发明的实施例采用如下技术方案：
一种薄膜晶体管的制造方法，包括：在制备薄膜晶体管的过程中，使用曝光机及掩膜版按大于正常曝光量的第一曝光量对引线层进行图案化，以形成源电极及漏电极；在所述图案化后的引线层上形成半导体层；使用所述曝光机及所述掩膜版按小于所述第一曝光量的第二曝光量对所述半导体层进行图案化，以形成有源层；所述掩膜版具有可掩膜出所述源电极的源极区域、可掩膜出所述漏电极的漏极区域及所述源极区域与所述漏极区域之间的缝隙，所述缝隙的宽度小于曝光机分辨率。
一种阵列基板的制造方法，包括：在用上述的方法制造的薄膜晶体管上形成钝化层；在覆盖有所述钝化层的所述薄膜晶体管中形成过孔，以暴露所述薄膜晶体管的所述漏电极；在所述钝化层上及所述过孔中形成像素电极。
本发明实施例提供的薄膜晶体管及阵列基板的制造方法中，制造TFT时，由于用于制备源/漏电极和图案化有源层的掩膜版上具有对应沟道区域的宽度小于曝光机分辨率的缝隙，通过增大曝光量，可在制备源/漏电极的光刻胶中正常形成源/漏电极图形。另外，通过减小曝光量，可在对半导体层进行图案化的光刻胶中形成对应沟道区域的半曝光区，该半曝光区可阻挡沟道区域的半导体层被刻蚀，从而形成了所需形状的有源层。由于使用上述方法制造底栅底接触结构TFT的源/漏电极及图案化有源层时共用了一套掩膜版，因此，降低了底栅底接触结构TFT的制造成本，进而降低了使用底栅底接触结构TFT的阵列基板的制造成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1A为现有技术中底栅顶接触结构TFT的剖面示意图；
图1B为现有技术中底栅底接触结构TFT的剖面示意图；
图2A～2E为本发明实施例1的TFT制造方法流程的剖面示意图；
图3A～3C为本发明实施例2的阵列基板制造方法流程的局部剖面示意图；
图4A为本发明实施例3提供的方法所制造的顶栅底接触结构TFT的剖面示意图；
图4B为本发明实施例4提供的方法所制造的阵列基板的局部剖面示意图。
具体实施方式
本发明实施例提供一种薄膜晶体管的制造方法，包括：在制备薄膜晶体管的过程中，使用曝光机及掩膜版按大于正常曝光量的第一曝光量对引线层进行图案化，以形成源电极及漏电极；在所述图案化后的引线层上形成半导体层；使用所述曝光机及所述掩膜版按小于所述第一曝光量的第二曝光量对所述半导体层进行图案化，以形成有源层；所述掩膜版具有可掩膜出所述源电极的源极区域、可掩膜出所述漏电极的漏极区域及所述源极区域与所述漏极区域之间的缝隙，所述缝隙的宽度小于曝光机分辨率。
本实施例还提供一种阵列基板的制造方法，包括：在用上述的方法制造的薄膜晶体管上形成钝化层；在覆盖有所述钝化层的所述薄膜晶体管中形成过孔，以暴露所述薄膜晶体管的所述漏电极；在所述钝化层上及所述过孔中形成像素电极。
本发明实施例提供的薄膜晶体管及阵列基板的制造方法中，制造TFT时，由于用于制备源/漏电极和图案化有源层的掩膜版上具有对应沟道区域的宽度小于曝光机分辨率的缝隙，通过增大曝光量，可在制备源/漏电极的光刻胶中正常形成源/漏电极图形。另外，通过减小曝光量，可在对半导体层进行图案化的光刻胶中形成对应沟道区域的半曝光区，该半曝光区可阻挡沟道区域的半导体层被刻蚀，从而形成了所需形状的有源层。由于使用上述方法制造底栅底接触结构TFT的源/漏电极及图案化有源层时共用了一套掩膜版，因此，降低了底栅底接触结构TFT的制造成本，进而降低了使用底栅底接触结构TFT的阵列基板的制造成本。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
本实施例提供一种TFT的制造方法，如图2A～2E所示，该方法包括如下步骤。
步骤1、如图2A所示，在基板201上依次形成栅电极202、栅极绝缘层203、引线层204及第一光刻胶层205。
步骤2、如图2B所示，使用曝光机及掩膜版206按大于正常曝光量的第一曝光量对所述第一光刻胶层205进行曝光。
该掩膜版206具有可掩膜出源电极的源极区域207A、可掩膜出漏电极的漏极区域207B及源极区域207A与漏极区域207B之间的缝隙209，该缝隙209的宽度L小于曝光机分辨率。其中，该缝隙对应薄膜晶体管的沟道区域208。
其中，正常曝光量指可以使掩膜版上正常尺寸的图案对应的光刻胶完全曝光的曝光量，正常尺寸的图案指该图案与其横截面的相交线中最短相交线的长度不小于曝光机的分辨率。
由于掩膜版206上的源极区域207A与漏极区域207B之间的对应薄膜晶体管沟道区域208的缝隙209的宽度L小于曝光机的分辨率，即该缝隙209属于不正常尺寸的图案。当属于正常曝光量的光线通过该缝隙209时会发生衍射现象，光线强度会减弱，因此，使用大于正常曝光量的曝光量对该第一光刻胶层205进行曝光，可使该第一光刻胶层205上对应该缝隙209的区域完全曝光，以在第一光刻胶层205中正常地形成源/漏电极图形。
步骤3、以曝光显影后的所述第一光刻胶层对所述引线层进行图案化，以形成如图2C所示的源电极210A及漏电极210B。然后，剥离掉第一光刻胶，暴露出图案化后的引线层。
步骤4、如图2D所示，在所述图案化后的所述引线层上依次形成半导体层211及第二光刻胶层212。然后，使用所述曝光机及所述掩膜版206按小于所述第一曝光量的第二曝光量对所述第二光刻胶层212进行曝光，以在所述第二光刻胶层212上对应掩膜版206上所述缝隙209的区域形成半曝光区213，所述第二光刻胶层212上除所述半曝光区213外其它的对应所述掩膜版206上图案的区域完全曝光。
通过减小曝光量，可使得通过掩膜版206上所述缝隙209的光线强度减弱，导致第二光刻胶层212上对应该缝隙209的区域不完全曝光，形成半曝光区。通过控制曝光量的减小量，使得第二光刻胶层212上除该半曝光区以外其它的对应掩膜版206上图案的区域能完全曝光。
步骤5、如图2E所示，以曝光显影后的所述第二光刻胶层对所述半导体层211进行图案化，以形成的覆盖所述沟道区208、所述源电极210A及所述漏电极210B的有源层214。
由于曝光显影后的第二光刻胶层上对应半曝光区的区域有部分光刻胶未被去除，在图案化半导体层211时，挡住了该半导体层211上对应沟道区的区域，使该区域不能被图案化，从而形成了所需形状的有源层214。
本实施例提供的方法为底栅底接触结构TFT的制造方法，该方法中，先通过增大曝光量，并使用具有宽度小于曝光机分辨率的缝隙的掩膜版，可正常形成源/漏电极；再使用该掩膜版，并减小曝光量，可在用于图案化半导体层的光刻胶中形成对应沟道区域的半曝光区，该光刻胶层显影后图案化半导体层时，对应该半曝光区的未被去除光刻胶可阻挡沟道区域的半导体层被刻蚀，从而形成了所需形状的有源层。上述方法中，由于形成源/漏电极及图案化有源层时共用一套掩膜版，因此，降低了底栅底接触结构TFT的制造成本。
需要说明的是：经实验表明，当曝光机的分辨率为4μm时，上述掩膜版上缝隙的宽度可为1.7μm～3.5μm。当然，上述掩膜版上缝隙的宽度并不限于该尺寸，可以根据曝光机的分辨率及所制造TFT的沟道长度适当调整。
另外，上述TFT的半导体层的材料可为非晶硅、有机半导体材料、氧化物半导体材料、低温多晶硅中的任意一种，可根据对TFT器件性能的需求，选用不同材料的半导体层。
实施例2
本实施例提供一种阵列基板的制造方法，该方法包括如下步骤。
步骤1、如图3A所示，用实施例1提供的方法在基板301上制造TFT，该TFT包括：栅电极302、栅极绝缘层303、源电极304A、漏电极304B及有源层305。然后，在有源层305上形成钝化层306。
步骤2、如图3B所示，在所述钝化层306及对应的有源层305上形成过孔307，以暴露所述TFT的漏电极304B。
步骤3、如图3C所示，在所述钝化层306上及所述过孔307中形成像素电极308。
本实施例提供的阵列基板的制造方法中使用了实施例1提供的方法来制造TFT，由于制造TFT的过程中，形成源/漏电极及图案化有源层时共用一套掩膜版，因此，在降低TFT制造成本的同时，也降低了使用该TFT的阵列基板的制造成本。
实施例3
本实施例提供一种顶栅底接触结构TFT的制备方法，如图4A所示，该方法包括如下步骤。
步骤1、在基板401上形成源电极402A及漏电极402B。
步骤2、在形成有源电极402A及漏电极402B的基板401上形成图案化的有源层403。
具体地，形成源/漏电极及图案化的有源层的方法使用实施例1中形成源/漏电极及图案化有源层的方法，该方法已在实施例1中进行了详细描述，在此不再赘述。
步骤3、在图案化的有源层403上依次形成栅极绝缘层404及栅电极405。
现有技术制造顶栅底接触结构TFT时，无法使用同一套掩膜版来制备源/漏电极及图案化的有源层，而上述顶栅底接触结构TFT的制造方法中，由于使用了实施例1提供的形成源/漏电极及图案化有源层的方法，因此，在形成源/漏电极及图案化有源层时共用了一套掩膜版，降低了该顶栅底接触结构TFT的制造成本。
实施例4
本实施例提供一种阵列基板的制造方法，如图4B所示，该方法包括如下步骤。
步骤1、用实施例3提供的方法在基板401上制造顶栅底接触结构TFT，该TFT在基板401上由下至上依次包括：源电极402A、漏电极402B、有源层403、栅极绝缘层404及栅电极405。然后，在该TFT上形成钝化层406。
步骤2、在钝化层406及对应的栅极绝缘层404、有源层403上形成过孔407，以暴露该TFT的漏电极402B。
步骤3、在钝化层406上及过孔407中形成像素电极408。
本实施例提供的阵列基板的制造方法中，由于使用了实施例3提供的方法来制造TFT，因此，在降低TFT制造成本的同时，也降低了使用该TFT的阵列基板的制造成本。
本发明实施例主要用于制备液晶显示器、有机电致发光显示器及电子纸显示器等。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (6)

1.一种薄膜晶体管的制造方法，其特征在于，包括：
在制备薄膜晶体管的过程中，使用曝光机及掩膜版按大于正常曝光量的第一曝光量对引线层进行图案化，以形成源电极及漏电极；
在所述图案化后的引线层上形成半导体层；
使用所述曝光机及所述掩膜版按小于所述第一曝光量的第二曝光量对所述半导体层进行图案化，以形成有源层；
所述掩膜版具有可掩膜出所述源电极的源极区域、可掩膜出所述漏电极的漏极区域及所述源极区域与所述漏极区域之间的缝隙，所述缝隙的宽度小于曝光机分辨率。
2.根据权利要求1所述的方法，其特征在于，在所述使用曝光机及掩膜版按大于正常曝光量的第一曝光量对引线层进行图案化，以形成源电极及漏电极之前，还包括：
在基板上形成栅电极；
在形成有栅电极的基板上形成栅极绝缘层。
3.根据权利要求1所述的方法，其特征在于，还包括：
在所述有源层上形成栅极绝缘层；
在所述栅极绝缘层上形成栅电极。
4.根据权利要求1～3任一项所述的方法，其特征在于，当所述曝光机的分辨率为4μm时，所述掩膜版上缝隙的宽度为1.7μm～3.5μm。
5.根据权利要求4所述的方法，其特征在于，所述半导体层的材料为非晶硅、有机半导体材料、氧化物半导体材料、低温多晶硅中的任意一种。
6.一种阵列基板的制造方法，其特征在于，包括：
在用权利要求1～5任一项所述的方法制造的薄膜晶体管上形成钝化层；
在覆盖有所述钝化层的所述薄膜晶体管中形成过孔，以暴露所述薄膜晶体管的所述漏电极；
在所述钝化层上及所述过孔中形成像素电极。
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US9159867B2 (en) 2012-09-10 2015-10-13 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof, and display device
CN102832254A (zh) * 2012-09-10 2012-12-19 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示面板
US9564536B2 (en) 2012-11-26 2017-02-07 Shenzhen Royole Technologies Co., Ltd. Self-aligned metal oxide thin-film transistor component and manufacturing method thereof
WO2014114018A1 (zh) * 2013-01-23 2014-07-31 深圳市华星光电技术有限公司 一种薄膜晶体管结构、液晶显示装置和一种制造方法
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US10644159B2 (en) 2015-11-09 2020-05-05 Shenzhen China Star Optoelectronics Technology Co., Ltd. Array substrate, method for manufacturing array substrate, and display device
CN105206626A (zh) * 2015-11-09 2015-12-30 深圳市华星光电技术有限公司 阵列基板及其制备方法、显示装置
WO2017080013A1 (zh) * 2015-11-09 2017-05-18 深圳市华星光电技术有限公司 阵列基板及其制备方法、显示装置
CN105206626B (zh) * 2015-11-09 2018-11-20 深圳市华星光电技术有限公司 阵列基板及其制备方法、显示装置
CN107170756A (zh) * 2017-05-24 2017-09-15 京东方科技集团股份有限公司 阵列基板、显示装置以及制备阵列基板的方法
CN107331619A (zh) * 2017-06-28 2017-11-07 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置、曝光装置
CN108933179A (zh) * 2018-07-05 2018-12-04 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管及其制作方法
CN108933179B (zh) * 2018-07-05 2020-06-16 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管及其制作方法
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CN109541829A (zh) * 2018-12-19 2019-03-29 惠科股份有限公司 掩膜版、液晶面板和液晶显示装置
CN109541829B (zh) * 2018-12-19 2021-08-24 惠科股份有限公司 掩膜版、液晶面板和液晶显示装置
CN110178226A (zh) * 2019-02-22 2019-08-27 京东方科技集团股份有限公司 薄膜晶体管、像素结构、显示装置和制造方法
WO2020168550A1 (zh) * 2019-02-22 2020-08-27 京东方科技集团股份有限公司 薄膜晶体管、像素结构、显示装置和制造方法
US11121257B2 (en) 2019-02-22 2021-09-14 Boe Technology Group Co., Ltd. Thin film transistor, pixel structure, display device and manufacturing method
CN110178226B (zh) * 2019-02-22 2022-07-26 京东方科技集团股份有限公司 薄膜晶体管、像素结构、显示装置和制造方法

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