CN102386223A - High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method - Google Patents
High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method Download PDFInfo
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Abstract
The invention discloses a high-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and a manufacturing method. The device comprises a substrate (1) and an epitaxial layer grown on the substrate (1), and is characterized in that: the epitaxial layer comprises a stress buffer layer (2), a GaN layer (3) and a heterostructure barrier layer (4) sequentially upwards from the bottom; the heterostructure barrier layer (4) is etched to the GaN layer (4) to form a groove in a gate region; a p-type GaN layer (6) is selectively grown on the groove; an insulated dielectric layer (7) is deposited on the surfaces of the p-type GaN layer (6) and the heterostructure barrier layer (4) and etched in source and drain regions on the surface of the heterostructure barrier layer (4); a gate metal (9) is evaporated in the gate region; and an ohmic contact metal (8) is evaporated on the source and drain regions. The device provided by the invention has a simple structure, is simple in manufacturing process and high in stability, and can effectively increase a forward threshold voltage and simultaneously repair crystal lattices damaged by plasma treatment.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to a kind of GaN high threshold voltage enhancement mode MOSHFET device and preparation method.
Background technology
Semiconductor power switch device is necessary function components and parts in electric energy transmitting and the control procedure.And with GaN the device for power switching that the third generation semi-conducting material of representative is processed; Because the material property with broad stopband, high breakdown field strength, high heat conductance, high saturated electron drift velocity, the high excellence of heterojunction boundary two-dimensional electron gas becomes present semiconductor power switch device research focus.Compare with traditional Si base power device, GaN base device for power switching has that switching speed is fast, loss is low, the heat resisting temperature advantages of higher, is the ideal substitute of energy-saving power device of future generation.
In the power electronic equipment that with the Semiconductor Converting Technology is the basis, the power switch transistor of control unsteady flow process all is normal (claiming enhancement mode again) of pass type, and this point is the basis that guarantees power electronics loop " fail safe ".The preparation that realizes enhancement mode GaN device for power switching is the present International Technology circle scientific and technological difficult point generally acknowledged with industrial circle.The mainstream technology scheme that realizes enhancement mode GaN base field-effect transistor device at present mainly contains following two kinds: traditional mos field effect transistor (MOSFET) reaches the HFET (HFET) based on the AlGaN/GaN heterojunction.
Traditional MOSFET is in the source drain region of p-GaN layer; Inject the perhaps method formation n+ access district of alloy through ion, add certain positive voltage at grid simultaneously, make the MOS arrangement works at anti-type state; Form n type conducting channel at the p-GaN laminar surface, realize break-over of device.Traditional MOSFET can effectively improve device threshold voltage, reduces leakage current, but injects comparatively difficulty because the GaN material is carried out ion, and it is of low quality that formed n+ inserts the district.Simultaneously, because p type GaN doping efficiency is lower, shortcoming such as device also exists conducting resistance bigger, and current density is lower.
And realize that based on the HFET (HFET) of AlGaN/GaN heterojunction enhancement device mainly contains two kinds of technical schemes, recessed gate technique and F ion implantation technique.Recessed gate technique is meant the area of grid on traditional AlGaN/GaN HFET device; Carve a groove through dry etching technology; In groove, make the conductivity gate electrode, help exhausting AlGaN/GaN 2DEG at the interface, realize enhancement device with this; Can keep simultaneously the AlGaN/GaN heterostructure that inserts the district, utilize access district high concentration 2DEG to reduce conducting resistance.The F ion implantation technique then is meant through electronegative ions such as the injection of AlGaN barrier layer under grid F ions, the 2DEG in the conducting channel is exhausted, thereby realize enhancement mode.
Recessed grid and F ion implantation technique increase aspects such as current density reducing break-over of device resistance, have very big advantage with traditional MOSFET compared with techniques, but it also have some comparatively significant disadvantages.One. the Cement Composite Treated by Plasma that recessed gate technique and F ion implantation technique are used can cause lattice damage, influences the stability and the reliability of device; Two. threshold voltage is lower; The threshold voltage of AlGaN/GaN enhancement mode HFET device is usually about 0～1V; Outside noise also has bigger gap from the 5V of actual needs with upper threshold voltage to the interference of system in the time of can't effectively avoiding OFF state, is difficult to satisfy the requirement of practical devices; Three. owing to adopt Schottky gate, when grid voltage reached the increase of threshold voltage continued, the grid forward current will increase rapidly made grid lose the control action to raceway groove, can't realize the device large current characteristic.
In order to solve the above-mentioned shortcoming that traditional schottky grid HFET device exists, there is scientist to adopt mixed structure MOS-HFET technical scheme in the recent period.This scheme combines recessed grid and MOS structure at area of grid, can effectively improve threshold voltage and reduce grid leakage current, utilizes simultaneously and inserts district high concentration 2DEG reduction device access district resistance, improves current density.The MOSHFET device has combined the two advantage of MOSFET and HFET, is more satisfactory technology path.But because MOS structural semiconductor layer all is the u-GaN layer of non-doping; Device is operated in accumulation area; Threshold voltage is usually about 0～1V; 5V with a certain distance from real work needs is in addition above, and plasma etch process can cause the material surface lattice damage, can reduce the reliability and the stability of device.
Summary of the invention
It is lower to the objective of the invention is to overcome common mixed type MOSHFET device threshold voltage, and plasma etching causes shortcomings such as lattice damage, and a kind of GaN base enhancement mode MOSHFET device and preparation method thereof is provided.The present invention has combined the MOSHFET high current density; The characteristic of low grid leakage current adopts and selects regional diauxic growth technology, utilizes the p-GaN layer as MOS structural semiconductor layer; The threshold voltage that further increases device is repaired the lattice damage that etching technics causes simultaneously, improves device performance.
For realizing above-mentioned purpose, technical scheme of the present invention is: a kind of GaN high threshold voltage enhancement mode MOSHFET device comprises substrate and grows in the epitaxial loayer on the substrate; Wherein, Epitaxial loayer comprises stress-buffer layer, GaN layer and heterostructure barrier layer from lower to upper successively, forms a groove at area of grid etching heterostructure barrier layer to GaN layer, and on groove, selects growing p-type GaN layer; P type GaN layer and heterostructure barrier layer surface deposition have insulating medium layer; At heterostructure barrier layer surface source electrode and drain region etching insulating medium layer, area of grid vapor deposition gate metal, vapor deposition metal ohmic contact on source, the drain region.
The heterostructure barrier layer is a kind of or any several kinds of combinations in AlGaN, AlInN, AlInGaN, the AlN material, and this heterostructure barrier layer is non-doped layer or n type doped layer; The GaN layer is the high resistant GaN layer.
The high resistant GaN layer is that resistivity is higher than 1 * 10
7The GaN layer of W * mm.
This insulating medium layer is SiO
2, SiNx, Al
2O
3, AlN, HfO
2, MgO, Sc
2O
3, Ga
2O
3, among the AlHfOx, HfSiON any.
The dielectric layer thickness is between 1～200nm.
Metal ohmic contact is Ti/Al/Ni/Au alloy or Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; Gate metal is one or more combination Pt, Ir, Ni, Au, Mo, Pd, Se or Be of following high-work-function metal.
Simultaneously, the present invention also provides a kind of GaN high threshold voltage enhancement mode MOSHFET preparation of devices method, and it may further comprise the steps:
A. utilize metal organic chemical vapor deposition or molecular beam epitaxy, growth stress resilient coating successively on substrate, GaN layer and heterostructure barrier layer;
B. on the heterostructure barrier layer, through plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD) or magnetic control sputtering plating, one deck dielectric layer of evenly growing is as selecting the growing mask layer;
C. utilize photoetching technique, selective etch mask layer and heterostructure barrier layer, and be etched to the GaN layer and form a groove, keep and insert district's mask layer and heterostructure barrier layer;
D. utilize metal organic chemical vapor deposition or molecular beam epitaxy, on groove, select growth p-GaN layer;
E. after dry etching is accomplished device isolation, utilize wet etching method etching to insert district's mask layer, show the contact interface of heterostructure barrier layer;
F. utilize plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD), megohmite insulant on the contact interface deposition is as gate insulator;
G. adopt photoetching technique, wet etching or dry etching source, the insulating barrier material in drain electrode ohmic contact zone, metal ohmic contact on the vapor deposition again;
H. adopt evaporation process, vapor deposition gate metal on gate insulator.
Among the step D, in the growth p-GaN layer, the u-GaN layer of also growing forms double-deck epitaxial structure on groove.
Compared with prior art, beneficial effect of the present invention is,
The present invention is technical mixed type MOS-HFET structure; Adopted the regional diauxic growth technology of selecting; Adopt the p-GaN layer as MOS structural semiconductor layer at grid; Make device be operated in anti-type state, the threshold voltage that can further increase device is repaired the lattice damage that etching technics causes simultaneously, improves device performance.Insert the district simultaneously and adopt the AlGaN/GaN heterostructure, can form the 2DEG of high concentration, high mobility, reduce the MOSHFET conducting resistance, increase current density.
Description of drawings
Fig. 1 is the structural representation of first kind of GaN high threshold voltage of the present invention enhancement mode MOSHFET device;
Fig. 2 is the structural representation of second kind of GaN high threshold voltage of the present invention enhancement mode MOSHFET device;
Fig. 3 A-Fig. 3 I is the process schematic representation of GaN high threshold voltage enhancement mode MOSHFET preparation of devices method of the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing the present invention is carried out detailed description.
Present embodiment such as Fig. 1 provide a kind of GaN high threshold voltage enhancement mode MOSHFET device; Comprise substrate 1 and grow in the epitaxial loayer on the substrate 1 that wherein, epitaxial loayer comprises stress-buffer layer 2, GaN layer 3 and heterostructure barrier layer 4 from lower to upper successively; Form a groove at area of grid etching heterostructure barrier layer 4 to GaN layers 3; And on groove, select growing p-type GaN layer 6, p type GaN layer 6 and heterostructure barrier layer 4 surface depositions have insulating medium layer 7, at heterostructure barrier layer 4 surperficial source electrodes and drain region etching insulating medium layer; Area of grid vapor deposition gate metal 9, vapor deposition metal ohmic contact 8 on source, the drain region.
This insulating medium layer 7 is SiO
2, SiNx, Al
2O
3, AlN, HfO
2, MgO, Sc
2O
3, Ga
2O
3, among the AlHfOx, HfSiON any.Insulating medium layer 7 thickness are between 1～200nm.
Fig. 3 A-Fig. 3 I is the process flow diagram of a kind of GaN high threshold voltage of the present invention enhancement mode MOSHFET preparation of devices method, and its technological process is following:
A. utilize metal organic chemical vapor deposition or molecular beam epitaxy, growth stress resilient coating, GaN layer and heterostructure barrier layer successively on substrate;
B. on the heterostructure barrier layer, through plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD) or magnetic control sputtering plating, one deck dielectric layer of evenly growing is as selecting the growing mask layer;
C. utilize photoetching technique, selective etch mask layer and potential barrier of heterogenous junction layer keep and insert district's mask layer and heterostructure barrier layer;
D. utilize metal organic chemical vapor deposition or molecular beam epitaxy, select growth p-GaN layer;
E. after dry etching is accomplished device isolation, utilize wet etching method etching to insert district's mask layer, show the contact interface of heterostructure barrier layer;
F. utilize plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD), megohmite insulant on the contact interface deposition is as gate insulator;
G. adopt photoetching technique, wet etching or dry etching source, the insulating barrier material in drain electrode ohmic contact zone, metal ohmic contact on the vapor deposition again;
H. adopt evaporation process, vapor deposition gate metal on gate insulator.
Select the thickness of growth p-GaN layer 6 need control to its surface and insert district 2DEG conducting channel plane,, improve device performance to reduce the charge carrier loss that scattering forms in raceway groove near level.
The control of the thickness of gate insulator dielectric layer 8 should be satisfied the conductive characteristic of gate metal 9 ability better controlled raceway grooves, also will keep good gate insulator property.
As shown in Figure 2, present embodiment has provided a kind of second kind of structure of GaN enhancement mode MOSHFET device, and the device architecture of itself and embodiment 1 is roughly the same.Difference is that it is u-GaN layer 10 that area of grid is selected growth structure, p-GaN layer 6 double-deck epitaxial structure.The u-GaN layer can improve p-GaN layer crystal physique amount, improves device performance.
Claims (7)
1. GaN high threshold voltage enhancement mode MOSHFET device; Comprise substrate (1) and grow in the epitaxial loayer on the substrate (1); It is characterized in that; Epitaxial loayer comprises stress-buffer layer (2), GaN layer (3) and heterostructure barrier layer (4) from lower to upper successively, forms a groove at area of grid etching heterostructure barrier layer (4) to GaN layer (3), and on groove, selects growing p-type GaN layer (6); P type GaN layer (6) and heterostructure barrier layer (4) surface deposition have insulating medium layer (7); At surperficial source electrode of heterostructure barrier layer (4) and drain region etching insulating medium layer, area of grid vapor deposition gate metal (9), vapor deposition metal ohmic contact (8) on source, the drain region.
2. GaN high threshold voltage enhancement mode MOSHFET device according to claim 1; It is characterized in that; Heterostructure barrier layer (4) is a kind of or any several kinds of combinations in AlGaN, AlInN, AlInGaN, the AlN material, and this heterostructure barrier layer is non-doped layer or n type doped layer; GaN layer (3) is the high resistant GaN layer.
3. GaN high threshold voltage enhancement mode MOSHFET device according to claim 1 is characterized in that this insulating medium layer (7) is SiO
2, SiNx, Al
2O
3, AlN, HfO
2, MgO, Sc
2O
3, Ga
2O
3, among the AlHfOx, HfSiON any.
4. GaN high threshold voltage enhancement mode MOSHFET device according to claim 1 is characterized in that insulating medium layer (7) thickness is between 1～200nm.
5. according to each described GaN high threshold voltage enhancement mode MOSHFET device of claim 1～4, it is characterized in that metal ohmic contact (8) is Ti/Al/Ni/Au alloy or Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; Gate metal (9) is one or more combination Pt, Ir, Ni, Au, Mo, Pd, Se or Be of following high-work-function metal.
6. GaN high threshold voltage enhancement mode MOSHFET preparation of devices method is characterized in that may further comprise the steps:
A. utilize metal organic chemical vapor deposition or molecular beam epitaxy, growth stress resilient coating successively on substrate, GaN layer and heterostructure barrier layer;
B. on the heterostructure barrier layer, through plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD) or magnetic control sputtering plating, one deck dielectric layer of evenly growing is as selecting the growing mask layer;
C. utilize photoetching technique, selective etch mask layer and heterostructure barrier layer, and be etched to the GaN layer and form a groove, keep and insert district's mask layer and heterostructure barrier layer;
D. utilize metal organic chemical vapor deposition or molecular beam epitaxy, on groove, select growth p-GaN layer;
E. after dry etching is accomplished device isolation, utilize wet etching method etching to insert district's mask layer, show the contact interface of heterostructure barrier layer;
F. utilize plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD), megohmite insulant on the contact interface deposition is as gate insulator;
G. adopt photoetching technique, wet etching or dry etching source, the insulating barrier material in drain electrode ohmic contact zone, metal ohmic contact on the vapor deposition again;
H. adopt evaporation process, vapor deposition gate metal on gate insulator.
7. GaN high threshold voltage enhancement mode MOSHFET preparation of devices method according to claim 6 is characterized in that, among the step D, in the growth p-GaN layer, the u-GaN layer of also growing forms double-deck epitaxial structure on groove.
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