CN102646667A - 功率半导体模块及制造功率半导体模块的方法 - Google Patents
功率半导体模块及制造功率半导体模块的方法 Download PDFInfo
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- CN102646667A CN102646667A CN2012100469208A CN201210046920A CN102646667A CN 102646667 A CN102646667 A CN 102646667A CN 2012100469208 A CN2012100469208 A CN 2012100469208A CN 201210046920 A CN201210046920 A CN 201210046920A CN 102646667 A CN102646667 A CN 102646667A
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Abstract
本发明名称为功率半导体模块及制造功率半导体模块的方法,涉及功率半导体模块,包括半导体器件(12),尤其是绝缘栅双极晶体管、反向导电绝缘栅双极晶体管或双模绝缘栅晶体管,具有发射电极和集电极,将导电上层(14)烧结到发射电极,上层(14)至少部分地能够与半导体器件(12)的半导体形成共晶体,且至少部分地具有如下热膨胀系数:与半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%,以及将导电基板(20)烧结到集电极。半导体模块(10)还包括与基板(20)电隔离且经由直接电连接(22)连接到上层(14)的导电区(24)。根据本发明的半导体模块易于制备,具有改进可靠性且呈现短路故障模式能力。
Description
技术领域
本发明涉及功率半导体模块以及制造功率半导体模块的方法。具体来说,本发明涉及具有短路故障模式能力的功率半导体模块以及制造具有短路故障模式能力的功率半导体模块的方法。
背景技术
在例如用于HVDC应用中的这类模块的串联连接叠层等的高功率半导体模块的情况下,已经发现缺陷导致短路。对于大芯片面积,这种短路在长时间保持稳定。如果例如冗余晶闸管设置在串联连接的晶闸管的叠层中,则其余完整无缺的晶闸管耐受关断阶段期间的电压,并且该叠层保持为可操作。随后能够在计划维修工作的过程中更换有缺陷的晶闸管。
在晶闸管模块中,例如,半导体(也就是说硅)与两个钼晶圆进行机械和电接触并且设置在两个钼晶圆之间。硅(Si)具有1420℃的熔点,其中钼(Mo)的熔点较高,并且硅和钼的金属间化合物具有甚至更高的熔点。因此,在存在缺陷的情况下,硅首先局部熔化,并且当电流流动时,它形成由半导体的整个厚度之上的熔化Si所组成的导电通道。这个缺陷区域能够扩散和/或移动,但是仅将影响芯片面积的小部分。在密封壳体中,熔化Si没有氧化,而是与钼起反应以形成一种类型的粉末。这个过程继续进行到已经消耗所有Si,并且可能会延续数年。
与晶闸管半导体组件形成对照,例如,绝缘栅双极晶体管芯片不是作为大面积单元制造的,因此通常多个小面积的单独芯片相互隔离并且并排设置在绝缘栅双极晶体管模块中。通常,小面积芯片的芯片尺寸是在0.25cm2至10cm2之间。当今的作为大面积单元的一个示例的晶闸管具有10cm2至300cm2的典型尺寸。
已经发现,例如对于绝缘栅双极晶体管模块,不能预计上述类型的长期稳定短路。这主要是由于各个芯片的已减小面积以及小的硅体积。在这种情况下,短路的伪稳态阶段仅持续几个小时至几天。此外,壳体往往有意没有密封,使得熔化硅能够与氧起反应,并且形成绝缘硅石(SiO2)。在有缺陷的芯片中没有任何稳定短路通路的情况下,能够发生的最坏情况的情形如下所述:如果模块中的其余芯片(包括激励)仍然完整无缺,则它们能够耐受关断阶段期间的电压。然后迫使电流通过有缺陷芯片,并且在完整无缺的芯片的高达击穿电压的电压下,能够导致形成具有极高功率密度的等离子体。这引起整个模块被破坏。
为了避免这个问题,从EP 0989611B1已知的是一种功率半导体模块,该模块由小面积的单独芯片来形成,并且其中单独芯片的短路没有导致模块的整体故障。按照这种现有技术,使由适当材料(例如银)构成的金属层与硅半导体的主电极中的一个或两个直接接触。这种金属层的材料必须与半导体的硅形成共晶混合物。在短路的情况下,加热整体夹合结构(sandwich structure),一旦达到共晶混合物的熔点,导电熔化开始在所述金属层与硅之间的接触表面上形成。这个区域则能够在半导体的整个厚度之上扩展,并且因而形成金属导电通道,其又称作热点。充分电接触由此通过电接触活塞来提供。
关于金属层的厚度,金属层必须提供足够的材料来形成通过半导体的整个厚度的导电通道。如果金属层的厚度是半导体厚度的至少50%,则情况通常是这样。在理想情况下,金属层的材料的摩尔量与硅的摩尔量之间的比率应当近似等于这些材料在相图中的其共晶点处的摩尔比率,使得金属导电通道由共晶材料形成。
但是,在引起半导体器件中的大温度摆动的高额定功率的正常操作条件下,引入与半导体接触的金属层在间歇工作负载(IOL)下产生热机疲劳的问题,并且能够因相接触的半导体芯片与金属层之间的热膨胀系数(CTE)的差而引起磨损。这可能潜在地引起半导体芯片的提早故障。
因此,从US 7538436B2已知的是一种包括使之与半导体芯片的主电极中的一个或两个直接接触的层的高功率压接封装半导体模块,使用在接触界面的平面中随机定向的、热膨胀系数能够调整成与硅的热膨胀系数接近或匹配的值的二维短石墨纤维、由金属基质合成物(MMC)材料来制成所述层。
使用对半导体器件施加压力的接触活塞的这些半导体模块的主要缺点之一是其老化行为。详细来说,存在渗透接触部之间的硅凝胶导致电流通路的欧姆电阻增加的风险。这个电阻还通过芯片的电极与模块的外部电接触部之间数个这样形成的干式接触部来增加。此外,其电流负载受到弹簧形状限制。此外,这种半导体模块的制造是复杂并且成本极高的。
发明内容
因此,本发明的一个目的是提供一种将消除本领域已知的至少一个缺点的改进功率半导体模块。
本发明的另一个目的是提供一种制造将消除本领域已知的至少一个缺点的功率半导体模块的改进方法。
尤其是,本发明的一个目的是提供一种功率半导体模块及其制造方法,其中制造方法易于执行,并且其中功率半导体模块具有良好短路故障模式能力和提高的可靠性。
该目的通过如权利要求1所述的功率半导体模块来实现。此外,此目的通过如权利要求16所述的制造功率半导体模块的方法来实现。在从属权利要求中定义了本发明的优选实施例。
本发明涉及一种功率半导体模块,包括半导体器件,尤其是绝缘栅双极晶体管(IGBT)、反向导电绝缘栅双极晶体管(RC IGBT)或者双模绝缘栅晶体管(BIGT),其具有发射电极和集电极,其中导电上层通过烧结接合连接到发射电极,上层的材料至少部分地能够与半导体器件的材料形成共晶体,并且至少部分地具有如下热膨胀系数:该热膨胀系数与半导体的热膨胀系数相差的范围是250%以下(≤250%)、尤其是50%以下(≤50%),以及其中导电基板通过另一个烧结接合连接到集电极,以及其中半导体模块还包括与基板电绝缘并且经由直接电连接连接到上层的导电区。
按照本发明,上层包括通过烧结过程使半导体器件或者其发射极相应地与其直接接触的适当材料。该层的所述材料必须与半导体、特别是与硅相应地形成共晶体或共晶混合物。在短路的情况下,加热整体夹合结构,一旦达到共晶混合物的熔点,导电熔化开始在所述层与半导体之间的接触表面上形成。这个区域则能够在半导体的整个厚度之上扩展,并且因而形成金属导电通道。因此,按照本发明的半导体模块提供短路故障模式(SCFM)能力。
因此,按照本发明的短路故障模式能力基于因故障所诱发的能量耗散而引起的材料熔化。硅芯片以及附连到其发射极接触部的诸如铝、金、铜或银之类的适当金属部分熔化并且产生高导电合金,即所谓的热点。
由于按照本发明的功率半导体模块的短路故障模式能力,这些模块可优选地是电压源转换器(VSC)的组件,因为它们允许所述转换器的长期可靠操作。在短路的情况下,它们不再能够进行切换。但是,它们仍然可携带负载电流。主要地,在***中存在冗余度,并且其它模块能够共享电压,因为出故障的模块仅具有电阻器的功能。转换器或半导体模块相应地则通常仅要求常规的计划维护来更换出故障模块。
另外,由于上层的热膨胀系数与半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%的事实,所以半导体模块内部、尤其是上层与半导体之间的应力可减小。这产生如下优点:功率模块内部的内部应力的风险没有超过上限,并且因而降低形成裂缝的风险。如果半导体器件是高功率半导体器件、特别是高功率绝缘栅双极晶体管,则这种效果特别重要。因此,按照本发明的功率半导体模块的可靠性得到提高。
由于将上层以及基板相应地烧结到半导体或者其电极的事实,因而不需要提供通过将压力施加到上层的接触活塞所形成的干式接触部。因此,发射电极或者上层可相应地通过适合于预期应用的任何连接来接触。作为一个示例,发射电极能够通过钎焊、烧结、超声焊接、瞬态接合等等,来连接到电流引线。适当地,这些连接和引线耐受短路故障模式中出现的电流负载。
另外,功率半导体模块包括与基板电隔离或绝缘并且经由直接电连接连接到上层的导电区。因此,发射电极或者上层相应地经由直接电连接、即从上层直接行进到导电区的一种桥接来接触,其中又可按照预期应用来接触导电区。
因此,可省略包括特别是在接触活塞与其连接的半导体模块的上壳体中的复杂电流连接或者模块功率连接的复杂布置。因此,可通过简单的方式制造按照本发明的功率半导体模块。可直接在功率半导体器件或上层之上相应地实现接合。
因此,导电区可用于提供互连,以便形成电路和/或冷却这些组件。这在高功率半导体模块领域中是特别有利的,因为它们可携带高电流。它们可优选地工作在大温度范围,特别是高达150或200℃或者甚至更高。
按照本发明的共晶体或者共晶混合物由此相应地是具有单一化学成分的元素、特别是金属或化学化合物的混合物。此外并且必要地,这种单一化学成分的熔点位于相应地低于形成它的金属或不同化学化合物的熔点或熔化区的温度。因此,共晶体是形成热点所必要的。在这方面,尤其是在短路的情况下,上层形成共晶体。
在本发明的一个优选实施例中,上层包括至少两个子层,其中下子层能够与半导体器件的半导体形成共晶体,并且其中上子层具有如下热膨胀系数:该热膨胀系数与半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%。在这种情况下,上层分为两个子层,以此为依据,上层的性质可按照简单方式来适合预期应用。详细来说,下子层可选择成在短路的情况下完全形成预期共晶体,而上子层可根据半导体器件的预期热膨胀系数来选择。因此,完全可适合所需应用的上层的大量可能的配置是可能的。例如,可使用具有适当热膨胀系数的价格更低的材料作为半导体芯片与发射极接合之间的缓冲。
即使上子层与半导体器件之间不存在直接接触,但是总之重要的是提供具有适合于半导体热膨胀系数的热膨胀系数的上子层。详细来说,上子层与下子层紧密接触。因此,在下子层经受热膨胀或者与此相反经受收缩的情况下,这种热行为受到上子层影响。详细来说,下子层的膨胀和/或收缩受到上子层影响,因而适合于上子层的行为并且因而适合半导体器件的行为。因此,由于提供具有适合于与半导体器件或半导体的热膨胀系数相应地匹配的热膨胀系数的上子层,所以降低了变为内部损坏、特别是裂缝的风险。因此,按照本发明的功率半导体模块在可靠性方面得到改进。
下子层和上子层可相互烧结在一起,由此允许在一个步骤将两个子层或者上层相应地烧结到半导体器件。备选地,两个子层可相互烧结在一起,由此形成预成型件,预成型件又烧结到半导体器件。
可优选的是,下子层包括铝,和/或上子层包括钼。这些化合物呈现预期性质。详细来说,铝与半导体形成适当共晶体,半导体一般包括硅。另外,钼的热膨胀系数的范围是硅的热膨胀系数的200%以下、尤其是硅的热膨胀系数的大约160%。
在本发明的另一个优选实施例中,上层包括合成物,尤其是铝-石墨合成物。按照这个实施例,按照本发明的半导体模块特别易于制备。子层主要包括可烧结到半导体器件的一种化合物。因此,不需要对两个子层进行预成型以形成上层或者在一个步骤烧结三层。具体来说,铝-石墨合成物关于共晶体的形成以及关于其热膨胀系数具有适当性质。
在这方面,热点的使用期限可得到改进,并且此外,通过在Al-石墨部分的表面上添加Al表层,来减少形成热点所需的时间。
在本发明的另一个优选实施例中,基板至少部分地具有如下热膨胀系数:该热膨胀系数与半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%。这使半导体模块内部、特别是基板与半导体之间的应力能够降低。因此,半导体模块内部的内部应力的风险没有超过上限,并且因而降低形成裂缝的风险。
进一步优选的是,基板包括钼、铜-钼或者铝-石墨。尤其是,钼的热膨胀系数的范围是硅的热膨胀系数的200%以下、尤其是硅的热膨胀系数的大约160%。因此,使功率半导体模块的内部结构中的裂缝或损坏的风险为最小。此外,导电使得按照本发明的半导体模块适合于各种应用。
在本发明的另一个优选实施例中,导电区形成为陶瓷衬底或金属衬底,例如直接接合铜(DBC)衬底或者活性金属铜(AMB)衬底。按照本发明的这种衬底尤其包括瓷砖、特别是氧化铝(Al2O3)、氮化铝(AlN)或者氧化铍(BeO),其中适当金属片、特别是铜片或铝片接合到一侧或两侧。按照本发明的这种衬底的使用由于其极好的导热性而是有利的。这种衬底的另一个主要优点是它的与半导体、特别是硅的热膨胀系数接近的低热膨胀系数,尤其是与纯金属相比。这确保良好的热循环性能。它们还具有优良的电绝缘和良好的散热特性。衬底的金属层的电流能力能够通过接合例如由钼、铝石墨或铜-钼所制成的具有与之匹配的热膨胀系数的附加高导电部分或层来得到提高。
在本发明的另一个优选实施例中,将至少两个半导体器件烧结到一个基板,其发射电极连接到一个导电区。这允许形成各种同等复杂(even complex)的内部结构,从而产生功率半导体模块的各种适当应用。
此外,优选的是,导电区和/或上层和/或基板通过接触活塞来接触。在这方面,接触活塞尤其提供导电区的外部接触部。即使不严格要求提供接触活塞,但是为外部接触部提供活塞会是有利的。这尤其允许外部接触部的电流的垂直通路,其中大量电流流经活塞。作为一个示例,例如,与例如线接合(wire bond)等接合相比,有可能引导高得多的电流通过活塞。由于不要求接触活塞来形成相应层之间的干式接触部的事实,所以不要求高压力。因此,没有降低可靠性。
在另一个优选实施例中,通过外部端子来接触导电区,并且通过外部端子来接触基板。这个实施例提供到外部接触装置的简单并且节省成本的电接触。例如,端子可由适当金属板形成。
在本发明的另一个优选实施例中,电连接通过钎焊或焊接来接合。这是特别简易并且可靠的连接,由此不要求接触活塞。
在本发明的另一个优选实施例中,基板是导电的,并且优选地在功率半导体(12)的相对侧上具有接触表面,该接触表面与烧结接合直接电接触。这个导电基板允许堆叠多个模块。通过堆叠这些模块,作为模块的发射极接触部的下模块的上接触部接触作为模块的集电极接触部的上模块的下接触部。
此外,本发明涉及一种制造功率半导体模块的方法,包括:提供半导体器件,尤其是绝缘栅双极晶体管、反向导电绝缘栅双极晶体管或者双模绝缘栅晶体管,其具有发射电极和集电极;将导电上层烧结到发射电极,上层至少部分地能够与半导体器件的半导体形成共晶体,并且至少部分地具有如下热膨胀系数:该热膨胀系数与所述半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%;将导电基板烧结到集电极,在基板上提供导电区,使得导电区与所述基板电绝缘,并且经由直接电连接来连接到上层。
按照以上所述,易于对按照本发明的功率半导体模块进行预成型,从而产生以上针对按照本发明的功率半导体模块所述的优点。
附图说明
在权利要求书部分、附图以及以下对相应附图和示例的描述中公开本发明的主题的附加特征、特性和优点,以示范方式示出按照本发明的半导体模块的一个实施例和示例。
附图中:
图1示出按照本发明的功率半导体模块的一个实施例的一部分的局部截面侧视图;
图2示出按照本发明的功率半导体模块的一个实施例的局部截面侧视图;
图3示出按照本发明的功率半导体模块的另一个实施例的局部截面侧视图。
参考标号列表
10 半导体模块
12 半导体器件
14 上层
16 下子层
18 上子层
20 基板
22 电连接
24 导电区
26 接触层
28 接触活塞
具体实施方式
图1中,示意示出按照本发明的功率半导体模块10的布置的一部分。详细来说,半导体模块10相应地包括功率半导体芯片或者功率半导体器件12。通过示范方式,半导体器件12可以是绝缘栅双极晶体管(IGBT)、反向导电绝缘栅双极晶体管(RC IGBT)、双模绝缘栅晶体管(BIGT)、二极管、金属氧化物半导体场效应晶体管(MOSFET)等等。按照本发明,半导体器件12设计用于相应地形成功率半导体模块或者高功率半导体模块,因而特别适合于其中使用大电流量的高功率应用。半导体器件12相应地包括其上侧的发射电极或阳极以及其下侧的集电极或阴极。更一般来说,发射电极形成半导体器件12的负载连接,并且集电极形成半导体器件12的另一个负载连接。此外,半导体器件12可包括用于控制半导体器件的栅电极等。
将上层14相应地烧结到半导体器件12或者发射电极(阳极)。因此,上层14通过烧结接合连接到发射电极。作为一个示例,上层14可通过低温接合、银纳米烧结过程等等,烧结到半导体器件12。
上层14至少部分地能够与半导体器件12的半导体形成共晶体。换言之,上层14包括能够与半导体器件12形成共晶体的材料。尤其是,相应半导体器件12包括硅。此外,上层14至少部分地具有如下热膨胀系数:该热膨胀系数与所述半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%。这可通过不同方式实现。
作为一个示例,上层14可包括至少两个子层。按照图1,上层14包括下子层16和上子层18。在这方面,特别优选的是,下子层16能够与半导体器件12的材料、特别是与硅形成共晶体。因此,下子层16可由铝、银、金或铜来形成。此外,所述金属的合金也会是可能的。由此,上子层18具有如下热膨胀系数:该热膨胀系数与所述半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%。这可通过形成钼的上子层18来实现。但是,下子层16以及上子层18可由适合的并且呈现所需性质的任何材料来形成。
为了能够形成通过半导体器件12的共晶体的导电通道,上层14必须提供足够的材料以形成这种通道。为此,相应地,上层14的厚度或者下子层18的厚度应当至少为半导体器件12的厚度的50%,和/或应当具有至少0.1mm的厚度、更优选地为至少0.5mm的厚度以及最优选地具有至少0.8mm的厚度。实际上,上层14或下子层18的厚度取决于半导体器件的厚度,半导体器件的厚度又取决于电气规范,即,取决于半导体器件12的闭塞电压。下子层16和上子层18可作为预成型件来提供。预成型件的厚度通常在0.2mm至5mm的范围之内。因此,例如,它们可通过烧结过程来连接。在用于制造按照本发明的功率半导体模块10的另一个步骤中,预成型件可烧结到半导体器件12或者相应地烧结到半导体器件12的发射极侧或发射电极。备选地,下子层16和上子层18可烧结在一起并且在一个步骤中烧结到半导体器件12。还有可能通过例如层压、铜焊或轧制包覆等的不同技术,来将下子层16连接到上子层18。
在一个备选实施例中,上层14可主要包括一个成分。在这种情况下,最优选的是,主成分包括合成材料。上层14可由例如铝-石墨合成物来形成。这个化合物关于共晶体的形成以及关于热膨胀系数具有预期性质。作为上层14的主成分的另一个示例包括铝-钼-铝(Al-Mo-Al)叠层。
另外,将基板20烧结到半导体器件12或者相应地到其集电极侧或集电极(阴极)。因此,形成基板20与半导体器件12之间的烧结接合。例如,可使用例如以上所述的烧结过程。基板20优选地具有如下热膨胀系数:该热膨胀系数与所述半导体器件的热膨胀系数相差的范围是≤250%、尤其是≤50%。例如,这可通过形成钼、铜-钼合金或者铝-石墨合成物的基板20来实现。此外,基板20是导电的。尤其是,与基板20的、半导体器件12通过烧结接合来连接在其上的表面相对的基板20的表面形成用于接触功率半导体模块10的接触表面。因此,基板20的该接触表面与烧结接合直接电接触。
基板20用作模块的底座或支承。
由上层14所形成的发射电极接触部则可通过适当技术、例如通过超声焊接、烧结、钎焊等等来接触。由此,应当形成能够耐受故障事件以及此后的所需电流负载的连接。
这种结构的示例如图2所示。按照图2,在一个非限制性示例中,上层14包括下子层16以及上子层18,以便关于热膨胀系数以及共晶体的形成得到所需性质。
详细来说,经由到导电区24的电连接22、优选地经由到导电区24的高电流连接来接触发射电极,导电区24与基板20电绝缘。例如,导电区24可优选地是直接接合铜衬底(DBC衬底)。电连接22可由例如铜、钼或者钼和铜的合金来形成,并且应当耐受至少50A和/或高达2000A或以上的电流和/或200℃或更高的温度。可由钼、铝-石墨、铜-钼、铜、金、银或者其合金来形成的接触层26、尤其是高导电层可设置为导电区24与电连接22之间的界面,以便提高衬底的金属层的电流能力。优选地,接触层26具有与衬底的金属层的热膨胀系数匹配的热膨胀系数。
此外,导电区24和/或接触层26设置在基板20的与半导体器件12相同的一侧上。
因此,按照本发明的功率半导体模块10具有适当短路故障模式能力,这可通过热点的热诱发形成来实现,因此按照本发明的半导体模块10极为可靠。
因此,一种制造功率半导体模块10的方法包括:提供半导体器件12,尤其是绝缘栅双极晶体管、反向导电绝缘栅双极晶体管或者双模绝缘栅晶体管,其具有发射电极和集电极;将导电上层14烧结到发射电极,上层14至少部分地能够与半导体器件12的半导体形成共晶体,并且至少部分地具有如下热膨胀系数:该热膨胀系数与所述半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%;将导电基板20烧结到集电极,基板20优选地至少部分地具有如下热膨胀系数:该热膨胀系数与所述半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%;在基板20上提供导电区24,使得导电区24与所述基板20电绝缘,并且经由直接电连接22来连接到上层14。
图3中,示出本发明的另一个实施例。按照图3,将两个半导体器件12烧结在一个基板20上,其发射电极连接到一个导电区24。这样形成的子模块允许为高功率应用提供复杂的内部结构。
优选地,通过接触活塞28来接触导电区24和/或上层或者相应地接触发射电极。因此,虽然因相应层的烧结连接而不需要半导体器件12的表面上的高压力用于形成按照本发明的干式接触,但是仍然有可能提供半导体模块10的一种压接封装设计。
一种可能的布置可在每个子模块的中心相应地提供少量接触活塞28或者弹簧,其中接触活塞28直接接合到电引线、导电区24或者接触层26。一种备选布置可在半导体模块10的每个角中包括一个接触活塞28,其中接触活塞28又直接接合到电引线、导电区24或者接触层26。
代替接触活塞28,有可能直接提供一个或多个常规外部端子,用于在外部相应地接触半导体器件12或者子模块或者导电区24和基板。
虽然在附图和以上描述中详细说明和描述了本发明,但是这种说明和描述被认为是说明性或示范性而不是限制性的;本发明并不局限于所公开的实施例。通过研究附图、本公开和所附权利要求书,对所公开的实施例的其它变更是本领域的技术人员可以理解并且在实施要求保护的本发明中能够实现。在权利要求书中,词语“包括”并不排除其它元件或步骤,以及不定冠词“一”、“一个”并不排除多个。在互不相同的从属权利要求中陈述某些量度的事实并不表示这些量度的组合不能用于形成有利因素。权利要求书中的任何参考标号不应当被理解为限制范围。
Claims (16)
1.一种功率半导体模块,包括半导体器件(12),尤其是绝缘栅双极晶体管、反向导电绝缘栅双极晶体管或者双模绝缘栅晶体管,其具有发射电极和集电极,其中导电上层(14)通过烧结接合连接到发射电极,所述上层(14)的材料至少部分地能够与所述半导体器件(12)的材料形成共晶体,并且所述上层(14)至少部分地具有如下热膨胀系数:该热膨胀系数与所述半导体器件的热膨胀系数相差的范围是≤250%、尤其是≤50%,以及其中导电基板(20)通过另一个烧结接合连接到所述集电极,以及其中所述功率半导体模块(10)还包括与所述基板(20)电绝缘并且经由直接电连接(22)连接到所述上层(14)的导电区(24)。
2.如权利要求1所述的功率半导体模块,其中,所述上层(14)包括至少两个子层,其中下子层(16)能够与所述半导体器件(12)的半导体形成共晶体,并且其中上子层(18)具有如下热膨胀系数:该热膨胀系数与所述半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%。
3.如权利要求2所述的功率半导体模块,其中,所述下子层(16)包括铝、银、金或铜,和/或其中所述上子层(18)包括钼,和/或其中所述下子层(18)的厚度至少为所述半导体组件(12)的厚度的50%。
4.如权利要求1所述的功率半导体模块,其中,所述上层(14)包括合成材料,尤其是铝-石墨合成物或者铝-钼-铝叠层。
5.如权利要求1至4中的任一项所述的功率半导体模块,其中,所述上层(14)的厚度至少为所述半导体器件(12)的厚度的50%,和/或具有至少0.05mm、更优选地为至少0.2mm以及最优选地为至少0.3mm的厚度。
6.如权利要求1至4中的任一项所述的功率半导体模块,其中,所述基板(20)至少部分地具有如下热膨胀系数:该热膨胀系数与所述半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%。
7.如权利要求5所述的功率半导体模块,其中,所述基板(20)包括铜、钼、铜-钼或者铝-石墨。
8.如权利要求1至6中的任一项所述的功率半导体模块,其中,所述导电区(24)形成为直接接合铜衬底或者活性金属铜衬底。
9.如权利要求1至7中的任一项所述的功率半导体模块,其中,将至少两个半导体器件(12)烧结到一个基板(20),其发射电极连接到一个导电区(24)。
10.如权利要求1至8中的任一项所述的功率半导体模块,其中,所述导电区(24)和/或所述上层(14)和/或所述基板通过接触活塞来接触。
11.如权利要求1至9中的任一项所述的功率半导体模块,其中,所述导电区(24)通过外部端子来接触,并且所述基板(20)通过外部端子来接触。
12.如权利要求1至10中的任一项所述的功率半导体模块,其中,所述电连接(22)通过钎焊或焊接或烧结来接合。
13.如权利要求1至11中的任一项所述的功率半导体模块,其中,所述基板(20)是导电的,并且优选地在所述功率半导体(12)的相对侧上具有接触表面,所述接触表面与所述烧结接合直接电接触。
14.如权利要求1至12中的任一项所述的功率半导体模块,其中,所述半导体器件(12)和所述导电区(24)设置在所述基板(20)的同一侧。
15.如权利要求1至13中的任一项所述的功率半导体模块,其中,所述半导体模块提供短路故障模式能力。
16.一种制造功率半导体模块(10)的方法,包括:
-提供半导体器件(12),尤其是绝缘栅双极晶体管、反向导电绝缘栅双极晶体管或者双模绝缘栅晶体管,其具有发射电极和集电极,
-将导电上层(14)烧结到所述发射电极,所述上层(14)至少部分地能够与所述半导体器件(12)的半导体形成共晶体,并且至少部分地具有如下热膨胀系数:该热膨胀系数与所述半导体的热膨胀系数相差的范围是≤250%、尤其是≤50%,
-将导电基板(20)烧结到所述集电极,
-在所述基板(20)上提供导电区(24),使得所述导电区(24)与所述基板(20)电绝缘,并且经由直接电连接(22)连接到所述上层(14)。
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US (1) | US20120211799A1 (zh) |
EP (1) | EP2503595A1 (zh) |
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Cited By (4)
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CN107851634A (zh) * | 2015-05-22 | 2018-03-27 | Abb瑞士股份有限公司 | 功率半导体模块 |
CN110364512A (zh) * | 2018-04-11 | 2019-10-22 | 半导体元件工业有限责任公司 | 用以防止短路事件的半导体功率模块 |
CN110676232A (zh) * | 2019-08-30 | 2020-01-10 | 华为技术有限公司 | 一种半导体器件封装结构及其制作方法、一种电子设备 |
CN112447614A (zh) * | 2019-08-30 | 2021-03-05 | 朋程科技股份有限公司 | 功率器件封装结构 |
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WO2014068936A1 (ja) * | 2012-11-05 | 2014-05-08 | 日本精工株式会社 | 半導体モジュール |
JP2014123638A (ja) * | 2012-12-21 | 2014-07-03 | Murata Mfg Co Ltd | 部品モジュール |
EP2827366A1 (en) * | 2013-07-18 | 2015-01-21 | ABB Technology AG | Power semiconductor module |
JP6860510B2 (ja) | 2015-06-22 | 2021-04-14 | アーベーベー・シュバイツ・アーゲーABB Schweiz AG | パワー半導体モジュール用のばね要素 |
EP3306663A1 (en) | 2016-10-05 | 2018-04-11 | ABB Schweiz AG | Sic-on-si-based semiconductor module with short circuit failure mode |
CN110268522B (zh) | 2017-02-01 | 2024-01-16 | 日立能源有限公司 | 具有主动短路故障模式的功率半导体装置 |
WO2018141867A1 (en) | 2017-02-01 | 2018-08-09 | Abb Schweiz Ag | Power semiconductor module with short circuit failure mode |
JP6860453B2 (ja) * | 2017-09-11 | 2021-04-14 | 株式会社東芝 | パワー半導体モジュール |
WO2020114660A1 (en) | 2018-12-07 | 2020-06-11 | Abb Schweiz Ag | Hybrid short circuit failure mode preform for power semiconductor devices |
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US5262336A (en) * | 1986-03-21 | 1993-11-16 | Advanced Power Technology, Inc. | IGBT process to produce platinum lifetime control |
DE59407080D1 (de) * | 1993-08-09 | 1998-11-19 | Siemens Ag | Leistungs-Halbleiterbauelement mit Druckkontakt |
DE19843309A1 (de) | 1998-09-22 | 2000-03-23 | Asea Brown Boveri | Kurzschlussfestes IGBT Modul |
EP1403923A1 (en) * | 2002-09-27 | 2004-03-31 | Abb Research Ltd. | Press pack power semiconductor module |
US8154114B2 (en) * | 2007-08-06 | 2012-04-10 | Infineon Technologies Ag | Power semiconductor module |
US7808100B2 (en) * | 2008-04-21 | 2010-10-05 | Infineon Technologies Ag | Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element |
-
2012
- 2012-02-02 EP EP12153710A patent/EP2503595A1/en not_active Withdrawn
- 2012-02-16 KR KR1020120016019A patent/KR20120095313A/ko not_active Application Discontinuation
- 2012-02-17 JP JP2012049759A patent/JP2012175113A/ja active Pending
- 2012-02-17 US US13/399,410 patent/US20120211799A1/en not_active Abandoned
- 2012-02-17 CN CN2012100469208A patent/CN102646667A/zh active Pending
Cited By (5)
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CN107851634A (zh) * | 2015-05-22 | 2018-03-27 | Abb瑞士股份有限公司 | 功率半导体模块 |
CN110364512A (zh) * | 2018-04-11 | 2019-10-22 | 半导体元件工业有限责任公司 | 用以防止短路事件的半导体功率模块 |
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CN112447614A (zh) * | 2019-08-30 | 2021-03-05 | 朋程科技股份有限公司 | 功率器件封装结构 |
CN110676232B (zh) * | 2019-08-30 | 2022-05-24 | 华为技术有限公司 | 一种半导体器件封装结构及其制作方法、一种电子设备 |
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KR20120095313A (ko) | 2012-08-28 |
JP2012175113A (ja) | 2012-09-10 |
EP2503595A1 (en) | 2012-09-26 |
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