CN102645806B - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN102645806B CN102645806B CN201210093643.6A CN201210093643A CN102645806B CN 102645806 B CN102645806 B CN 102645806B CN 201210093643 A CN201210093643 A CN 201210093643A CN 102645806 B CN102645806 B CN 102645806B
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- base palte
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- 239000000758 substrate Substances 0.000 title abstract description 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 238000002161 passivation Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 23
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052779 Neodymium Inorganic materials 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 description 11
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 9
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides an array substrate and a manufacturing method thereof. A resistor for providing a Gamma voltage is integrated in the array substrate to save the area originally reserved for the resistor in a printed circuit board (PCB); and because the array substrate only adopts the resistor to provide the Gamma voltage, compared with the an array substrate adopting a Power IC, the cost is reduced, and the power consumption of the array substrate provided by the invention is low. The array substrate provided by the invention comprises a resistor positioned between a gate insulation layer and a passivation layer, and at least one through hole formed on an area of the passivation layer covered by the resistor, wherein the resistor is not connected with an active layer and a source-drain electrode layer in the array substrate. The manufacturing method of the array substrate comprises the following steps of: forming the resistor on the gate insulation layer, wherein the resistor is separated from and not connected with the active layer and the source-drain electrode layer in the array substrate; and forming the passivation layer on the resistor, and forming at least one through hole on the area of the passivation layer covered by the resistor through etching.
Description
Technical field
The present invention relates to display device technical field, particularly relate to a kind of array base palte and manufacture method.
Background technology
In existing liquid crystal indicator, gamma (Gamma) voltage is actual is supplied to source electrode drive circuit voltage.In the driving circuit of liquid crystal panel, the generation of gamma (Gamma) voltage is mainly adopted in two ways: first, as shown in Figure 1, directly at PCB (Printed Circuit Board, printed circuit board (PCB)) on provide a voltage by power IC (Power IC), then share with Chip-R 11 series connection the form that this provides voltage, provide Gamma voltage to source electrode drive circuit 12.The second, directly provide Gamma voltage by programmable PowerIC.
Adopt first kind of way to provide gamma voltage, its circuit structure is simple, and power consumption can do very low.But, adopt first kind of way will inevitably be Chip-R slot milling because of needs, and increase the area of PCB.In today that panel demand is day by day lightening, reserving valuable pcb board area is very necessary to solve other problems.Further, use various encapsulation continually, the resistance of different resistance brings trouble to a certain degree also can to the management of manufacturer and supply.And pass through the second way, namely programmable Power IC directly provides Gamma voltage, this mode of voltage that provides is flexible, shortens the time of Gamma Voltage Cortrol (Gamma Tuning), also can solve the difficulty that first method is brought to a great extent.But, programmable Power IC itself costly, adopt programmable Power IC significantly can improve production cost undoubtedly, programmable Power IC is made up of multiple electronic component simultaneously, therefore gamma electric voltage is provided also can to improve the power consumption of product by programmable Power IC, the problem that this respect Ye Shi panel vendor needs emphasis to consider.
Summary of the invention
The invention provides a kind of array base palte and manufacture method thereof, be integrated into by resistance in array base palte, by providing voltage to the resistance in array base palte, and on the insulation course covered above by resistance, voltage is derived to provide voltage by equally distributed through hole.So both for pcb board has saved out more spaces, as long as and by providing voltage just exportable voltage to resistance, power consumption is also low.
Array base palte provided by the invention, described array base palte comprises: the resistance between gate insulator and passivation layer, and has at least one through hole on the region of passivation layer covering resistance;
Wherein, described resistance is separated setting with the active layer in array base palte, source-drain electrode layer.
Described resistance is strip.
Described through hole is uniformly distributed on the length direction of strip resistance.
The material of described resistance is amorphous silicon.
Metal level is had in described through hole.
Have N-type non-crystalline silicon layer in described through hole, described N-type non-crystalline silicon layer is between described metal level and resistance.
The material of described metal level is the alloy of a kind of metal in molybdenum, aluminium, neodymium, titanium, chromium, tantalum or copper or several formation.
Present invention also offers a kind of display device, this display device comprises above-mentioned array base palte.
Present invention also offers the method making above-mentioned array base palte, the method comprises:
Formation resistance on gate insulator, wherein, described resistance is separated setting with the active layer in array base palte, source-drain electrode layer;
Resistance forms passivation layer, and covers by being etched in passivation layer on the region of resistance, form at least one through hole.
Described on gate insulator, form resistance after, before resistance forms passivation layer, the method comprises further:
On described resistance, and the position forming through hole is needed to form metal level.
After gate insulator forms resistance, before resistance forms passivation layer, the method comprises further:
On described resistance, and need the position forming through hole to form metal level and N-type non-crystalline silicon layer, described N-type non-crystalline silicon layer is between described metal level and resistance.
Resistance is integrated in wherein by array base palte provided by the invention, reduces the pcb board area taken to set up resistance separately, and adopts the resistance be integrated in array base palte, and cost is not high and power dissipation ratio is lower.
Accompanying drawing explanation
Fig. 1 is for providing the structure of Gamma voltage by Chip-R in the existing mode of the present invention;
Fig. 2 is the sectional view of embodiment of the present invention array base palte resistance region;
Fig. 3 is the structural representation of array base palte embodiment of the present invention;
Fig. 4 is the resistance position schematic diagram of array base palte embodiment of the present invention;
Fig. 5 is through hole distribution schematic diagram in the embodiment of the present invention;
Fig. 6 is that embodiment of the present invention array base palte resistance region executes alive sectional view to grid layer;
Fig. 7 is the process flow diagram of the inventive method embodiment.
Embodiment
In order to save the area of pcb board, the large cost simultaneously avoiding adopting programmable Power IC to expend and high power consumption, the invention provides a kind of array base palte.Be described below in conjunction with the embodiment of accompanying drawing to this array base palte.
Array base palte in the present embodiment, as shown in Figure 2, be from bottom to top glass substrate 21, grid layer 22, gate insulator 23, resistance 24 between gate insulator 23 and passivation layer 25, and there is at least one through hole 26 in the region covering resistance 24 at passivation layer 25.When connecting voltage to resistance 24 two ends, by through hole 26, ohmically voltage is derived to provide dividing potential drop.
Through hole 26 described in the present embodiment is for being guided by the voltage be added on resistance 24.In fact, resistance end positions also by formed through hole, be added in needing to be added in ohmically voltage on resistance by the through hole at resistance two ends.But the through hole at resistance two ends and through hole 26 described in the present embodiment are different through holes, act on also different.Certainly, also just first before forming the passivation layer can form lead-in wire at resistance two ends, then, when needs apply voltage to resistance, can directly be connected on the lead-in wire of formation in advance.
The resistance be integrated in array base palte provided in the present embodiment, as shown in Figure 3, described resistance is arranged in array base palte, and can be used for provides Gamma voltage to source electrode drive circuit, but not only for the situation for providing Gamma voltage.Other need provide the situation of dividing potential drop with resistance, the resistance being integrated in array base palte that the present embodiment all can be adopted to provide provides.
Resistance 24 is separated setting with the active layer in array base palte, source-drain electrode layer, and namely resistance 24 is not connected with the active layer in array base palte, source-drain electrode layer.Resistance 24 is integrated in array base palte, and between gate insulator 23 and passivation layer 25, and active layer, source-drain electrode layer etc. included by thin film switch on array base palte and pixel electrode part are also between gate insulator 23 and passivation layer 25.In order to not affect the normal work of TFT switch and pixel electrode, as shown in Figure 4, array base palte 41 there are thin film switch and the pixel electrode area 42 of a resistance 24 and array base palte.Resistance quantity in array base palte 41 is one, and is long strip type, is separated setting with the thin film switch of array base palte with pixel electrode area 42.The voltage applied on resistance like this can not conducting to the thin film switch of array base palte and pixel electrode area, cause the normal work affecting thin film switch and pixel electrode.
Certainly, in practice, the resistance quantity on each array base palte is restriction not, can according to the quantity of actual conditions setting resistance voluntarily and position.Such as, for larger array base palte, then can set the resistance in multiple the present embodiment.Each resistance is integrated between the gate insulator of array base palte and passivation layer, by applying certain voltage at resistance two ends, just can from the through hole of resistance region overlying passivation layer extraction voltage.
Further, resistance is positioned to the position also not restriction of array base palte, the mode of placement resistance is as shown in Figure 4 a kind of embodiment.Actual any one position that can as required resistance be positioned in array base palte, only need to ensure that resistance is separated with thin film switch in array base palte and pixel electrode area not to be connected, making to be added in ohmically voltage can not impact thin film switch and pixel electrode.
The method be integrated into by resistance in array base palte shown in Fig. 3 of employing, relative to the mode adopting Chip-R in pcb board, the resistance be integrated in array base palte has saved the area of pcb board undoubtedly.Simultaneously, be integrated in the resistance of array base palte relative to adopting programmable integrated circuit source to provide the mode of Gamma voltage, the resistance be integrated in array base palte is only needed to provide gamma electric voltage, and do not need a large amount of electronic components to export required gamma electric voltage, therefore then power consumption is lower, and cost is lower.
When providing Gamma voltage for source electrode drive circuit, need for each dot structure provides the Gamma voltage of identical magnitude of voltage.So preferably mode is resistance is strip, and described through hole is uniformly distributed on the length direction of resistance, and specifically as shown in Figure 5, such is designed with 2 benefits:
One, because resistance is strip, when needing the voltage exporting specific a certain numerical value, the concrete resistance knowing resistance can not be needed, and just when applying the voltage of a known voltage value at resistance two ends, the magnitude of voltage of through hole and the resistance two ends of deriving voltage wherein one end, is multiplied by known voltage value by calculating the distance of through hole to aforementioned wherein one end again except the resistance total length for applying known voltage value part.Such as, in Fig. 5, the magnitude of voltage connected at A, B two ends of strip resistance is U, so the 4th through hole (through hole 4) and the voltage difference of through hole B, draw by L4/L*U.
Two, through hole is uniformly distributed on the length direction of resistance, as long as can meet easily, distance between through hole with through hole is identical just can export equal voltage.Such as, through hole 1 in Fig. 4 and the magnitude of voltage exported between through hole 2 just equal the magnitude of voltage that through hole 3 and through hole 4 export, because through hole 1 equals to the distance of through hole 2 distance that through hole 3 arrives through hole 4.Need to obtain this advantage, the shape of resistance itself is uniform.Like this, the resistance between through hole 1 with through hole 2 just meeting is identical with the resistance between through hole 3 and through hole 4.
Further, through hole is uniformly distributed on the length direction of resistance can multiple distribution mode, can arrange according to actual conditions to the position that through hole carries out.Such as, when needing the voltage that all extraction voltage value is equal from every two adjacent through holes, just can to set on resistance all through holes for drawing dividing potential drop all between any two apart from equal.If need to divide through hole, as shown in Figure 5, the dividing potential drop that needs are drawn between two two through hole from through hole 1 ~ 6 is equal, and the dividing potential drop that two two through hole finger tips are drawn from through hole 7 ~ 11 is equal, but and the dividing potential drop of drawing between two two through hole in through hole 1 ~ 6 is not above etc., distance then in through hole 1 ~ 6 between two two through hole is equal and be uniformly distributed, and the distance in through hole 7 ~ 11 between two two through hole is equal and be uniformly distributed, but distance between through hole 1,2 and the distance between through hole 7,8 are not etc.
It should be noted that, resistance be strip and through hole be uniformly distributed on the length direction of resistance these two design and non-required exist simultaneously.Only have one of them also can reach a corresponding effect, just have two effects better.
In the present embodiment, the material that resistance 24 can be used as resistance by difference is formed, and in the present embodiment, preferred a-Si (amorphous silicon, amorphous silicon) is as the material making resistance.Amorphous silicon is a kind of semiconductor film material, adopts amorphous silicon to prepare resistance, it not only can be made to reach the effect of resistance, also because the characteristic of amorphous silicon itself, make the technique making amorphous silicon resistance relatively simple, raw materials consumption is little, and price is more cheap.
Lead-in wire in array base palte can be made up of, as conducting metal etc. multiple different conductive material.In the present embodiment, preferred ITO (tin indium oxide) is as the material of lead-in wire.In the present embodiment, by with on the passivation layer of through hole, form ITO layer, by the contact of ITO layer and resistance, the ohmically component voltage of turn-on voltage is derived.
In order to make lead-in wire component voltage can better be derived, avoiding lead-in wire and resistance 24 surface of contact to occur to be oxidized and change, preferably, layer of metal layer 28 can be had in through-holes as buffering.And the ITO layer 29 being covered in metal level 28 contacts with metal level 28 and is derived by the voltage put on resistance 24.
Metal level 28 can be formed by possessing the good molybdenum of electric conductivity, aluminium, neodymium, titanium, chromium, tantalum or copper product, or also can be made up of several alloys formed in aforementioned various metals.Voltage better can be exported to ITO layer from resistance by such metal level, also can avoid the surface of contact as resistance and ITO layer that oxidation fusion occurs jointly.
Preferably, can also have N-type non-crystalline silicon layer 27 in through hole, wherein N-type non-crystalline silicon layer 27 to be between described metal level 28 and resistance 24 in through hole.
Because the electric conductivity of metal level is much stronger than semiconductor, be also easy to produce electric potential difference between metal level and resistive layer.So just need between metal level and resistance, add one deck N-type amorphous silicon 27 again, the electric conductivity of N-type non-crystalline silicon layer is better than amorphous silicon, slightly poorer than metal, is therefore positioned over the electric potential difference that can slow down metal level 28 and amorphous silicon 24 between amorphous silicon and metal level.
In order to increase the conductance of resistive layer, a voltage (as shown in Figure 6) equal with the magnitude of voltage applied at resistance two ends can be increased on the grid under gate insulator, because the voltage applied can make the electron-collection in resistance in the region contacted with gate insulator, and form hole in resistance inside.When applying the voltage equal with the magnitude of voltage applied at resistance two ends in grid, making the concentration of electronics be more than or equal to the concentration in hole, so just on the resistance of amorphous silicon formation, forming space charge region, being weak inversion layer.After weak inversion layer is formed, resistance conductive rate can be increased when applying voltage at resistance two ends.
Array base palte in the present embodiment, comprises the sheet resistance be integrated in wherein, and is covered in the through hole on ohmically passivation layer.By applying voltage on resistance, and from through hole, derive voltage to provide voltage.And because through hole is evenly distributed on the length direction of strip resistance, therefore still voltage between through hole can be drawn according to the distance between through hole and resistance two ends distance apart and the magnitude of voltage being applied to resistance two ends when not knowing resistance.Further, the voltage that each dot structure provides equivalent is also easily.
Display device provided by the invention, as shown in Figure 3, adopts the above-mentioned array base palte being integrated with resistance.Voltage is applied to provide the Gamma voltage of source electrode drive circuit by giving the resistance in array base palte.
Present invention also offers the method making above-mentioned array base palte.Below in conjunction with accompanying drawing, the method for preparing substrate in the present embodiment is described.
The method for making of array base palte as shown in Figure 7, comprising:
Step S501, forms grid layer on the glass substrate.The formation of grid layer has come by the step of deposition and etching.By deposition, carrying out etching formation thin-film electronic element after mask plate exposure is the common method that this area makes array base palte.
Step S502, the monolithic glass substrate forming grid layer forms gate insulator.
Step S503, the formation resistance on gate insulator.Resistance is formed by the method depositing and etch.Owing to also having N-type non-crystalline silicon layer and metal level in through hole, described metal level is arranged in through hole, and described N-type non-crystalline silicon layer is in through hole and is between described metal level and resistance.Metal level and N-type non-crystalline silicon layer are formed, can deposit respectively and etch respectively, also by the full exposure of a mask plate and half exposure technique after single exposure, then form resistance, N-type non-crystalline silicon layer and metal level through step etching.
Material due to resistance can be amorphous silicon, and the material of the active layer in the thin film switch and pixel electrode area of array base palte is also amorphous silicon.Therefore, when forming resistance, can be formed separately, also together can being formed with the amorphous silicon structures in dot structure.And the material of the thin film switch in array base palte and the source-drain layer in pixel electrode is also N-type non-crystalline silicon layer, so the N-type non-crystalline silicon layer in through hole can be formed with the source-drain layer in thin film switch and pixel electrode simultaneously, also formation can be separated separately.
The material of metal level is the alloy of a kind of metal in molybdenum, aluminium, neodymium, titanium, chromium, tantalum or copper or several formation.
Step S504, resistance forms passivation layer, and covers by being etched in passivation layer on the region of resistance, forms at least one through hole.The through hole that passivation layer needs is formed by a mask plate etching after deposit passivation layer.Originally the metal level covered by passivation layer after through hole is formed and N-type non-crystalline silicon layer are exposed.Described metal level is filled in through hole, and described N-type non-crystalline silicon layer to be filled in through hole and to be between described metal level and resistance.
Finally, square one-tenth goes between over the passivation layer.Go between by deposition and etching formation.The material of lead-in wire can be ITO.
In order to increase the usable range of the resistance in array base palte, the number of openings of passivation layer can be increased.And be all filled with N-type non-crystalline silicon layer and metal level in through-holes accordingly.Metal level in through-holes is also formed ITO layer as lead-in wire.When determining the through hole needing to use as required, lead-in wire is fused by heat shock light beam by unwanted through hole, the through hole needed for only connecting.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. an array base palte, is characterized in that, described array base palte comprises:
Resistance between gate insulator and passivation layer, and at least one through hole is had on the region of passivation layer covering resistance, to make when connecting voltage for described resistance two ends, described ohmically voltage is derived to provide dividing potential drop by described through hole;
Wherein, described resistance is separated setting with the active layer in array base palte, source-drain electrode layer.
2. array base palte according to claim 1, is characterized in that, described resistance is strip.
3. array base palte according to claim 1 and 2, is characterized in that, described through hole is uniformly distributed on the length direction of resistance.
4. array base palte according to claim 1, is characterized in that, the material of described resistance is amorphous silicon.
5. array base palte according to claim 1, is characterized in that, has metal level in described through hole.
6. array base palte according to claim 5, is characterized in that, also have N-type non-crystalline silicon layer in described through hole, described N-type non-crystalline silicon layer is between described metal level and resistance.
7. array base palte according to claim 5, is characterized in that, the material of described metal level is the alloy of a kind of metal in molybdenum, aluminium, neodymium, titanium, chromium, tantalum or copper or several formation.
8. a display device, is characterized in that, this display device comprises any one array base palte described in the claims 1 ~ 7.
9. a method for making for array base palte, is characterized in that, the method comprises:
Gate insulator forms resistance, and wherein, described resistance is separated setting with the active layer in array base palte, source-drain electrode layer;
Resistance forms passivation layer, and covers at passivation layer on the region of resistance, form at least one through hole, to make when connecting voltage for described resistance two ends, described ohmically voltage is derived to provide dividing potential drop by described through hole.
10. method for making according to claim 9, is characterized in that, described on gate insulator, form resistance after, the method comprises further:
On described resistance, and the position forming through hole is needed to form metal level.
11. method for makings according to claim 9, is characterized in that, described on gate insulator, form resistance after, the method comprises further:
On described resistance, and need the position forming through hole to form N-type non-crystalline silicon layer and metal level, described N-type non-crystalline silicon layer is between described metal level and resistance.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210093643.6A CN102645806B (en) | 2012-03-31 | 2012-03-31 | Array substrate and manufacturing method thereof |
| PCT/CN2012/085484 WO2013143312A1 (en) | 2012-03-31 | 2012-11-28 | Array substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210093643.6A CN102645806B (en) | 2012-03-31 | 2012-03-31 | Array substrate and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN102645806A CN102645806A (en) | 2012-08-22 |
| CN102645806B true CN102645806B (en) | 2015-02-18 |
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| CN201210093643.6A Expired - Fee Related CN102645806B (en) | 2012-03-31 | 2012-03-31 | Array substrate and manufacturing method thereof |
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| CN (1) | CN102645806B (en) |
| WO (1) | WO2013143312A1 (en) |
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| CN102645806B (en) * | 2012-03-31 | 2015-02-18 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
| CN105047152A (en) * | 2015-08-05 | 2015-11-11 | 昆山龙腾光电有限公司 | Display module |
| CN106057141A (en) * | 2016-05-04 | 2016-10-26 | 深圳市华星光电技术有限公司 | Gamma reference voltage generation circuit and display |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2677167B2 (en) * | 1993-07-08 | 1997-11-17 | 日本電気株式会社 | Method for manufacturing liquid crystal display device with built-in drive circuit |
| US6246460B1 (en) * | 1998-11-20 | 2001-06-12 | U.S. Philips Corporation | Active matrix liquid crystal display devices |
| US6639244B1 (en) * | 1999-01-11 | 2003-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| CN201876643U (en) * | 2010-11-22 | 2011-06-22 | 京东方科技集团股份有限公司 | Array substrate and LCD panel |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1103061C (en) * | 1995-08-07 | 2003-03-12 | 株式会社日立制作所 | Active matrix type liquid crystl display device resistant to static electricity |
| CN102645806B (en) * | 2012-03-31 | 2015-02-18 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
-
2012
- 2012-03-31 CN CN201210093643.6A patent/CN102645806B/en not_active Expired - Fee Related
- 2012-11-28 WO PCT/CN2012/085484 patent/WO2013143312A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2677167B2 (en) * | 1993-07-08 | 1997-11-17 | 日本電気株式会社 | Method for manufacturing liquid crystal display device with built-in drive circuit |
| US6246460B1 (en) * | 1998-11-20 | 2001-06-12 | U.S. Philips Corporation | Active matrix liquid crystal display devices |
| US6639244B1 (en) * | 1999-01-11 | 2003-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| CN201876643U (en) * | 2010-11-22 | 2011-06-22 | 京东方科技集团股份有限公司 | Array substrate and LCD panel |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013143312A1 (en) | 2013-10-03 |
| CN102645806A (en) | 2012-08-22 |
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