CN202435382U - Threshold-logic-based 7-3 counter with SET (single electron transistor)/MOS (metal oxide semiconductor) hybrid structure - Google Patents
Threshold-logic-based 7-3 counter with SET (single electron transistor)/MOS (metal oxide semiconductor) hybrid structure Download PDFInfo
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- CN202435382U CN202435382U CN2012200014867U CN201220001486U CN202435382U CN 202435382 U CN202435382 U CN 202435382U CN 2012200014867 U CN2012200014867 U CN 2012200014867U CN 201220001486 U CN201220001486 U CN 201220001486U CN 202435382 U CN202435382 U CN 202435382U
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Abstract
The utility model relates to the technical field of integrated circuit, in particular to a threshold-logic-based 7-3 counter with an SET (single electron transistor)/MOS (metal oxide semiconductor) hybrid structure. The 7-3 counter comprises a seven-input threshold logic gate, an eight-input threshold logic gate and a nine-input threshold logic gate. A circuit comprises three threshold logic gates and two phase inverters. Five PMOS (p-channel metal oxide semiconductor) transistors, five NMOS (n-channel metal oxide semiconductor) transistors and three SETs are needed. A Boolean-logic-based CMOS (complementary metal oxide semiconductor) 7-3 counter needs 194 transistors. Average power consumption of the whole circuit is 6.92nW. By the threshold-logic-based 7-3 counter compared with the prior art,, number of transistors needed is reduced greatly, power consumption of the circuit is lowered evidently, and structure of the circuit is further simplified. In addition, the threshold-logic-based 7-3 counter is possible to be applied to a multiplier, a multi-input adder and a digital signal processor.
Description
Technical field
The utility model relates to technical field of integrated circuits, particularly a kind of 7-3 counter of being made up of nano-device based on the SET/MOS mixed structure of voting logic.
Background technology
The 7-3 counter can calculate the number of high level in the input signal as basic digital circuit unit, is encoded to 3 binary number.The 7-3 counter is widely used in multiplier, many input summers and the digital signal processor.Existing 7-3 counter mainly is made up of traditional CMOS transistor.7-3 counter circuit structure based on cmos device is complicated, needs to consume more transistor, and circuit power consumption is bigger, and integrated level is not high.
Summary of the invention
The purpose of the utility model provides a kind of 7-3 counter of the SET/MOS mixed structure based on voting logic.
The utility model adopts following scheme to realize: a kind of 7-3 counter of the SET/MOS mixed structure based on voting logic comprises one seven input Threshold Logic Gate, eight input Threshold Logic Gate and one nine input Threshold Logic Gate; The output of said seven input Threshold Logic Gate is connected with the 8th input of said eight input Threshold Logic Gate, the 8th input of nine input Threshold Logic Gate through first inverter; The output of said eight input Threshold Logic Gate is connected through the 9th input of second inverter with said nine input Threshold Logic Gate; Said seven, eight, nine input Threshold Logic Gate are made up of the SET/MOS hybrid circuit.
In the utility model one embodiment, described SET/MOS hybrid circuit comprises: PMOS pipe, its source electrode connects power end
V DdOne NMOS pipe, its drain electrode is connected with the drain electrode of said PMOS pipe; And a SET pipe, it is connected with source electrode that said NMOS manages.
Coulomb blockade oscillation effect and multiple-grid input characteristics that the utility model utilizes single-electronic transistor and metal-oxide-semiconductor mixed structure to be had have realized the 7-3 counter based on the SET/MOS mixed structure of voting logic.Because the powerful logic function of voting logic, this circuit only is made up of 3 Threshold Logic Gate and 2 inverters, consumes 5 PMOS pipes altogether, 5 NMOS pipes and 3 SET.CMOS 7-3 counter based on Boolean logic then will consume 194 transistors.The simulation architecture of HSPICE shows that this circuit can realize the function of 7-3 counter, and the average power consumption of entire circuit is merely 19.7 nW.Comparatively speaking, the 7-3 counter number of tubes that the utility model proposes significantly reduces, and circuit power consumption significantly reduces, and circuit structure has obtained further simplification, is expected to be applied in the circuit such as multiplier, many input summers and digital signal processor.
Description of drawings
Fig. 1 is the Threshold Logic Gate sketch map.
Fig. 2 is a SET/MOS mixed structure 7-3 counter schematic diagram.
Fig. 3 is multiple-grid input SET/MOS hybrid circuit schematic diagram.
Fig. 4 is the input-output characteristic curve of SET/MOS hybrid circuit.
Fig. 5 a and Fig. 5 b are SET/MOS mixed structure 7-3 counter simulated properties curve.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is further specified.
As shown in Figure 2, the utility model provides a kind of 7-3 counter of the SETMOS mixed structure based on voting logic, comprises one seven input Threshold Logic Gate, eight input Threshold Logic Gate and one nine input Threshold Logic Gate; The output of said seven input Threshold Logic Gate is connected with the 8th input of said eight input Threshold Logic Gate, the 8th input of nine input Threshold Logic Gate through first inverter; The output of said eight input Threshold Logic Gate is connected through the 9th input of second inverter with said nine input Threshold Logic Gate; Said seven, eight, nine input Threshold Logic Gate are made up of the SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic is to calculate total input value according to the weighted value of importing; And total input value and said threshold value compared; More than or equal to said threshold value, then be output as 1, otherwise be output as 0.
Specifically, (Single electron transistor SET) carries out the design of 7-3 counter with the mode that metal-oxide-semiconductor mixes mutually to the utility model employing single-electronic transistor.Single-electronic transistor is a nano electron device of new generation, has unique coulomb blockade and coulomb oscillations effect.SET has extra small device size and ultralow circuit power consumption; Have remarkable advantages at aspects such as power consumption, operating rates with respect to traditional microelectronic component, be expected to become manufacturing low-power consumption of future generation, the desirable basic device of high density very lagre scale integrated circuit (VLSIC).Single-electronic transistor can be compatible mutually with the CMOS silicon technology simultaneously, helps making full use of the technological advantage of existing C MOS and carry out circuit design.This makes the SET/MOS mixed structure become a research direction of single-electronic transistor.The SET/MOS hybrid circuit possesses the superior function of SET and metal-oxide-semiconductor, shows extremely low power consumption, extra small device size, stronger driving force and bigger output voltage swing, in digital circuit, has obtained using widely.
In addition, the SET/MOS hybrid circuit can not followed traditional method for designing based on Boolean logic, and adopts voting logic to carry out the design of circuit.Because voting logic has the logical process more complicated than Boolean logic, can more effectively realize logic function.Therefore based on the circuit design of the SET/MOS mixed structure of voting logic, be expected to the function of intensifier circuit, improve the integrated level of circuit.
The cardinal principle of the voting logic of the utility model is that the weight calculation according to input goes out total input value, total input value and threshold value is compared draw output logic.If total input value then is output as 1, otherwise is 0 more than or equal to threshold value.The logical equation that voting logic will satisfy is suc as formula shown in (1), wherein
W iBe input
X iCorresponding weight,
nBe the number of input,
θBe threshold value.The sketch map of Threshold Logic Gate is as shown in Figure 1.To confirm at first that based on the circuit design of voting logic the voting logic expression formula of circuit, key are to confirm the weight of each input in the circuit and the threshold value of circuit.
The 7-3 counter of the utility model can calculate the number of logical one in the input signal, with the form output of 3 binary numbers.Please continue with reference to Fig. 2, this 7-3 counter is made up of 3 Threshold Logic Gate and two inverters, and 7 are input as
V 0-
V 6, be output as
V Out0-
V Out2The calculating of logical one number during this structure can realize importing, and export 3 bits.The voting logic expression formula of 3 outputs is suc as formula shown in (2), (3), (4);
,
,
are for exporting, and
,
are
, the output valve of
Jing Guo inverter.Each Threshold Logic Gate among Fig. 2 constitutes by the SET/MOS hybrid circuit of a multiple-grid input, and its schematic diagram is as shown in Figure 3.This circuit is managed by 1 PMOS, and the SET of 1 NMOS pipe and 1 multiple-grid input is in series.The PMOS pipe is that entire circuit provides bias current as constant-current source in the circuit.Because the electric current of SET operate as normal is all very little, is generally the nA order of magnitude, so the PMOS pipe should be operated in sub-threshold region.The grid bias of NMOS pipe
V NgFix, its value is slightly larger than the threshold voltage of NMOS pipe
V Th, the drain voltage of SET is fixed as
V Ng-
V ThGrid voltage
V 1,
V 2...,
V nBe capacitively coupled on the Coulomb island.Coupling capacitance has constituted the array of an electric capacity, is used to calculate total input value.According to the definition of voting logic, just can obtain corresponding output logic with circuit threshold value through more total input voltage.When total input voltage during, be output as high level (logical one) greater than threshold value; When total input voltage during, be output as low level (logical zero) less than threshold value.Through suitable circuit parameter is set, the input and output that the SET/MOS hybrid circuit is corresponding (
V In-
V Out) characteristic curve is as shown in Figure 4.Output voltage changes along with the variation of input voltage.When input voltage surpassed certain numerical value (being the threshold value of circuit, like the 400mV among Fig. 4), output realized the saltus step from the low level to the high level.Through the biasing SET back gate voltage (
V Ctrl), can obtain different threshold values.Therefore, the SET/MOS hybrid circuit can be realized the function of Threshold Logic Gate.
The utility model utilizes HSPICE that the 7-3 counter based on voting logic is carried out the function simulating checking.The model of SET is the macro model (Compact macromodel) widely-used at present, that precision is high.This model with the formal definition of electronic circuit in SPICE.The model of metal-oxide-semiconductor uses the Predicting Technique model (Predictive technology model) of 22 nm that generally acknowledge at present.In the circuit of 7-3 counter, except unit input coupling capacitance (
C 0,
C 1,
C 2) outside, 3 Threshold Logic Gate have identical simulation parameter, wherein
C 0,
C 1,
C 2Correspond respectively to and produce output
V Out0,
V Out1,
V Out2Threshold Logic Gate.In circuit, supply voltage
V DdBe set to 0.80V, the breadth length ratio of PMOS pipe and NMOS pipe (
W/
L) all being made as 1/7, main circuit simulation parameter is as shown in table 1.
Table 1
The characteristic curve that emulation obtains is shown in Fig. 5 a and Fig. 5 b.In Fig. 5 a, input signal all is made as square wave, and the high-low level of input is respectively 0.8 V and 0 V.The output waveform that emulation obtains can be calculated the number of logical one in the input, 3 to be the form output of binary number, shown in Fig. 5 b.Therefore the structure of the utility model proposition can realize the function of 7-3 counter effectively.
What be noted that the utility model requirement protection here is the connection features of hardware circuit, just is used to let those skilled in the art better understand the utility model as for other relevant design algorithmic descriptions.
The above is merely the preferred embodiment of the utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to the covering scope of the utility model.
Claims (2)
1. the 7-3 counter based on the SET/MOS mixed structure of voting logic comprises one seven input Threshold Logic Gate, eight input Threshold Logic Gate and one nine input Threshold Logic Gate; The output of said seven input Threshold Logic Gate is connected with the 8th input of said eight input Threshold Logic Gate, the 8th input of nine input Threshold Logic Gate through first inverter; The output of said eight input Threshold Logic Gate is connected through the 9th input of second inverter with said nine input Threshold Logic Gate; Said seven, eight, nine input Threshold Logic Gate are made up of the SET/MOS hybrid circuit.
2. the 7-3 counter of the SET/MOS mixed structure based on voting logic according to claim 1, it is characterized in that: described SET/MOS hybrid circuit comprises:
One PMOS pipe, its source electrode connects power end
V Dd
One NMOS pipe, its drain electrode is connected with the drain electrode of said PMOS pipe; And
One SET pipe, its source electrode with said NMOS pipe is connected.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571076A (en) * | 2012-01-05 | 2012-07-11 | 福州大学 | Threshold logic-based 7-3 counter with SET (single-electron transistors)/MOS (metal-oxide-semiconductor) mixed structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571076A (en) * | 2012-01-05 | 2012-07-11 | 福州大学 | Threshold logic-based 7-3 counter with SET (single-electron transistors)/MOS (metal-oxide-semiconductor) mixed structure |
| CN102571076B (en) * | 2012-01-05 | 2015-05-20 | 福州大学 | Threshold logic-based 7-3 counter with SET (single-electron transistors)/MOS (metal-oxide-semiconductor) mixed structure |
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| GR01 | Patent grant | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120912 Termination date: 20180105 |