CN102609023B - Built-in analog power supply circuit - Google Patents
Built-in analog power supply circuit Download PDFInfo
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- CN102609023B CN102609023B CN2012100638668A CN201210063866A CN102609023B CN 102609023 B CN102609023 B CN 102609023B CN 2012100638668 A CN2012100638668 A CN 2012100638668A CN 201210063866 A CN201210063866 A CN 201210063866A CN 102609023 B CN102609023 B CN 102609023B
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Abstract
The invention discloses a built-in analog power supply circuit comprising a band gap reference source, an operational amplifier, a first compensation capacitor, a second compensation capacitor, a first voltage stabilizing capacitor, a second voltage stabilizing capacitor, a high-voltage PMOS (P-channel Metal Oxide Semiconductor) power tube, a low-voltage NMOS (N-channel Metal Oxide Semiconductor) power tube, a first resistor, a second resistor and an external power voltage; an output end of the operational simplifier and an upper electrode plate of the first compensation capacitor are connected with the grid of the high-voltage PMOS power tube; and the drain of the high-voltage PMOS power tube, one end of the second resistor, a lower electrode plate of the second compensation capacitor, and the drain of the low-voltage NMOS tube are connected with the upper electrode plate of the first voltage stabilizing capacitor. With the adoption of the built-in analog power supply circuit, the capacitance value of the first voltage stabilizing capacitor is smaller and can be generated from the inside, and the increase of the system cost caused by providing capacitance from outside of the chip is avoided.
Description
Technical field
The present invention relates to circuit field, particularly relate to a kind of built-in analog power circuit.
Background technology
In the industrial electronic field, because the chip exterior supply voltage is higher, so built-in analog power circuit is widely used.This can guarantee the application of low-voltage device in large scale integrated circuit, and can reduce chip area, reduces power consumption.
Built-in analog power circuit of the prior art as shown in Figure 1, is comprised of generating circuit from reference voltage 101, operation amplifier circuit 102 and output stage 103.Generating circuit from reference voltage 101 is produced by resistance R 3 and the R4 series connection of same type, and the reference voltage Vref that produces is supplied with the negative input end of operational amplifier OPA; The output stage of operational amplifier OPA is connected with the grid of PMOS power tube P1; The drain electrode of P1, the top crown of C1 are connected with the upper end of resistance R 2, and this node is also the output node of internal simulation power supply VCC; The upper end of the lower end of resistance R 2, resistance R 1 is connected with the positive input terminal of operational amplifier OPA; Outer power voltage VDDA is connected with the upper end of R4, the power end of operational amplifier OPA, source electrode and the substrate of P1; Ground voltage is connected with the lower end of R3, the ground end of operational amplifier OPA, the lower end of resistance R 1 and the lower end of capacitor C 1.When system works, the internal simulation supply voltage is VCC=VDDA* (R3/ (R4+R3)) * ((R1+R2)/R1), as outer power voltage VDDA when floating in a big way, the VCC variation range also can be larger, so this circuit can not be applied to the larger situation of outer power voltage domain of walker.
In prior art, for the phase margin that guarantees that the system loop is enough, and avoid internal power source voltage startup overshoot to puncture the load low-voltage device, usually need dominant pole is located at the VCC output node, inferior dominant pole is arranged on operational amplifier OPA output terminal.This just need to the capacitance of C1 establish very large, generally need external capacitor to realize, but external capacitor can increase system cost.
Summary of the invention
The purpose of this invention is to provide a kind of built-in analog power circuit, at inside circuit, just can provide needed electric capacity, do not need external capacitor, and then can reduce the cost of built-in analog power circuit.
For achieving the above object, the invention provides following scheme:
A kind of built-in analog power circuit comprises: band gap reference, operational amplifier, the first building-out capacitor, the second building-out capacitor, the first electric capacity of voltage regulation, the second electric capacity of voltage regulation, high voltage PMOS power tube, low pressure NMOS pipe, the first resistance, the second resistance and outer power voltage;
The reference voltage output end of described band gap reference is connected with the negative input end of described operational amplifier; The reference voltage output end of described band gap reference is by described the second electric capacity of voltage regulation ground connection;
The top crown of the output terminal of described operational amplifier, described the first building-out capacitor is connected with the grid of described high voltage PMOS power tube; The drain electrode of one end of the drain electrode of described high voltage PMOS power tube, described the second resistance, the bottom crown of described the second building-out capacitor, described low pressure NMOS pipe is connected with the top crown of described the first electric capacity of voltage regulation, and this node is also the output node of internal simulation power supply VCC; The grid of one end of the other end of described the second resistance, described the first resistance, the top crown of described the second building-out capacitor, described low pressure NMOS pipe is connected with the positive input terminal of described operational amplifier; Described outer power voltage is connected with the bottom crown of the power end of the power end of described band gap reference, described operational amplifier, described the first building-out capacitor, source electrode and the substrate of described high-voltage power pipe; The bottom crown of the source electrode of the ground end of the ground end of described band gap reference, described operational amplifier, the other end of described the first resistance, described low pressure NMOS pipe and substrate, described the first electric capacity of voltage regulation is connected with ground voltage.
Optionally, described band gap reference, described operational amplifier, described the first building-out capacitor and described high voltage PMOS power tube are high pressure resistant device.
Optionally, described the first electric capacity of voltage regulation, described the second building-out capacitor, described the second electric capacity of voltage regulation, described the first resistance, described the second resistance and described low pressure NMOS pipe are low-voltage device.
Optionally, the dominant pole of described built-in analog power circuit is arranged on the output terminal of described operational amplifier, the inferior limit of described built-in analog power circuit is arranged on the internal simulation power output end of described built-in analog power circuit, and described internal simulation power output end is connected with the drain electrode of described high voltage PMOS power tube.
, according to specific embodiment provided by the invention, the invention discloses following technique effect:
In the present invention, dominant pole is arranged on the amplifier output terminal, and the internal simulation power output end is time dominant pole, and therefore the capacitance of the first electric capacity of voltage regulation is less, can be produced by inside, has avoided being provided and the elevator system cost by chip exterior;
In addition, internal simulation supply voltage of the present invention does not change with outer power voltage, therefore is applicable to the larger situation of outer power voltage variation range, when particularly externally supply voltage value is low, still can work;
The present invention's the first building-out capacitor upper and lower side is connected in respectively the grid of outer power voltage and high voltage PMOS power tube, when externally the high frequency burr appears in supply voltage, the grid of high voltage PMOS power tube can change with the variation of outer power voltage, so the internal simulation supply voltage is better to the high frequency electric source voltage rejection ratio of outer power voltage;
When the present invention had successfully solved outer power voltage and starts fast, the overshoot of internal simulation supply voltage punctured the problem of low-voltage device, under toggle speed arbitrarily, the phenomenon that overshoot punctures can not occur.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment be briefly described, apparent, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is built-in analog power circuit structure diagram of the prior art;
Fig. 2 is built-in analog power circuit structure diagram of the present invention;
When Fig. 3 is outer power voltage VDDA fast powering-up of the present invention, the oscillogram of internal power source voltage VCC.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete description, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment that obtains, belong to the scope of protection of the invention.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 2 is built-in analog power circuit structure diagram of the present invention.As shown in Figure 2, this built-in analog power circuit comprises: band gap reference Bandgap, operational amplifier OPA, the first building-out capacitor C3, the second building-out capacitor C2, the first electric capacity of voltage regulation C1, the second electric capacity of voltage regulation C4, high voltage PMOS power tube P1, low pressure NMOS pipe N1, the first resistance R 1, the second resistance R 2 and outer power voltage VDDA;
The reference voltage output end Vref of described band gap reference Bandgap is connected with the negative input end of described operational amplifier OPA; The reference voltage output end Vref of described band gap reference Bandgap is by described the second electric capacity of voltage regulation C4 ground connection;
The top crown of the output terminal of described operational amplifier OPA, described the first building-out capacitor C3 is connected with the grid of described high voltage PMOS power tube P1; The drain electrode of one end of the drain electrode of described high voltage PMOS power tube P1, described the second resistance R 2, the bottom crown of described the second building-out capacitor C2, described low pressure NMOS pipe N1 is connected with the top crown of described the first electric capacity of voltage regulation C1, and this node is also the output node of internal simulation power supply VCC; The grid of one end of the other end of described the second resistance R 2, described the first resistance R 1, the top crown of described the second building-out capacitor C2, described low pressure NMOS pipe N1 is connected with the positive input terminal of described operational amplifier OPA; Described outer power voltage VDDA is connected with the bottom crown of the power end of the power end of described band gap reference Bandgap, described operational amplifier OPA, described the first building-out capacitor C3, source electrode and the substrate of described high voltage PMOS power tube P1; The bottom crown of the source electrode of the ground end of described band gap reference Bandgap, the ground end of described operational amplifier OPA, the other end of described the first resistance R 1, described low pressure NMOS pipe N1 and substrate, described the first electric capacity of voltage regulation C1 is connected with ground voltage.
In practical application, band gap reference Bandgap, operational amplifier OPA can adopt high pressure resistant device.The first building-out capacitor C3 and high voltage PMOS power tube P1 can adopt high pressure resistant device.The first electric capacity of voltage regulation C1, the second building-out capacitor C2, the second electric capacity of voltage regulation C4, the first resistance R 1, the second resistance R 2, low pressure NMOS pipe N1 can adopt low-voltage device.The first resistance R 1, the second resistance R 2 are same type resistance.
Below the principle of work of built-in analog power circuit of the present invention is elaborated.
In order to make system stability, the dominant pole of Fig. 2 cyclic system is located at operational amplifier OPA output node place, and inferior dominant pole is located at VCC output node place.C2, C3 are the building-out capacitor of increase system loop phase nargin, and C3 is less before dominant pole frequency is compensated, and also have the quick start-up performance of VDDA.Make the P1 grid voltage follow the effect of VDDA voltage before OPA not yet works, to avoid the too early conducting of power tube P1, make VCC the phenomenon of overshoot occur starting; C2 can make VCC and N1 grid set up a quick path when overshoot occurs VCC, in overshoot moment, make up voltage on the N1 grid be approximately equal to up voltage on VCC, rushes down the positive charge at VCC place with the electric current that increases by N1, the generation of Avoids or reduces overshoot voltage; The quick path of C2, R1, R2 and N1 composition, also have the effect of output impedance while reducing high frequency simultaneously, strengthens the driving force of VCC, increases the output stage dot frequency, plays the effect of phase compensation; C1 exists as the electric capacity of voltage regulation of VCC, alleviates simultaneously the overshoot phenomenon of VCC while starting.
Concrete start-up course is as follows: before externally power vd DA powers on, the upper bottom crown supply voltage of C3 electric capacity is zero, when the VDDA fast powering-up, the mirror current source that bandgap provides not yet makes before the OPA startup, the P1 grid voltage can be because the effect of C1 raises along with the quick rising of VDDA voltage, P1 can conducting, so this stage does not have electric current and by the P1 power tube, VCC voltage raise.After OPA starts, the output current of OPA can fill negative charge to the C3 lower end, so that the reduction of P1 grid voltage, the conducting gradually of P1 power tube, V1 voltage raises, simultaneously, in the start-up course of bandgap, because the C4 capacitance is larger, the Vref that connects the OPA negative input end rises slower, the OPA output terminal can drop to normal working voltage under the reciprocation of positive-negative input end voltage V1, Vref, therefore the amplifier output voltage also can descend slower, reduces VCC the possibility of overshoot occurs.When overshoot occurred VCC, because C2 electric capacity is larger, the grid of N1 was followed together fast rise of VCC in addition, and the large electric current that flows through N1 can make VCC fall after rise fast, avoids puncturing the possibility of load low-voltage device.
After the system normal operation, operational amplifier OPA and output stage form low pressure drop (LDO) linear voltage regulator, VCC=Vref* ((R1+R2)/R1) is therefore arranged, and the reference voltage that Vref provides for bandgap voltage reference bandgap, the variation with outer power voltage VDDA does not change, and therefore built-in analog power VCC does not change with the variation of outer power voltage yet; And the bias current of OPA is produced by bandgap reference current mirror image, and the variation with VDDA does not change, so this system is applicable to the larger situation of outer power voltage variation range.
Because power tube of the present invention adopts PMOS(P1), the output voltage of OPA can drop to (VCC-Vth (P1)) (Vth (P1) is the threshold voltage of P1 pipe), P1 still is operated in saturation region, compared to the circuit structure of NMOS as power tube, the present invention can work under lower outer power voltage VDDA, so its outer power voltage work lower limit can be lower.
When Fig. 3 is outer power voltage VDDA fast powering-up of the present invention, the oscillogram of internal power source voltage VCC.As seen from Figure 3, after adopting built-in analog power circuit of the present invention, when outer power voltage VDDA fast powering-up, internal power source voltage VCC can stablize rising, does not occur " burr " in the waveform of VCC, and expression overshoot phenomenon can not occur.
Applied specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously,, for one of ordinary skill in the art,, according to thought of the present invention, all will change in specific embodiments and applications.In sum, this description should not be construed as limitation of the present invention.
Claims (4)
1. built-in analog power circuit, it is characterized in that, comprising: band gap reference, operational amplifier, the first building-out capacitor, the second building-out capacitor, the first electric capacity of voltage regulation, the second electric capacity of voltage regulation, high voltage PMOS power tube, low pressure NMOS pipe, the first resistance, the second resistance and outer power voltage;
The reference voltage output end of described band gap reference is connected with the negative input end of described operational amplifier; The reference voltage output end of described band gap reference is by described the second electric capacity of voltage regulation ground connection;
The top crown of the output terminal of described operational amplifier, described the first building-out capacitor is connected with the grid of described high voltage PMOS power tube; The drain electrode of one end of the drain electrode of described high voltage PMOS power tube, described the second resistance, the bottom crown of described the second building-out capacitor, described low pressure NMOS pipe is connected with the top crown of described the first electric capacity of voltage regulation, the junction configuration node of the drain electrode of one end of the drain electrode of described high voltage PMOS power tube, described the second resistance, the bottom crown of described the second building-out capacitor, described low pressure NMOS pipe and the top crown of described the first electric capacity of voltage regulation, described node is also the output node of internal simulation power supply VCC; The grid of one end of the other end of described the second resistance, described the first resistance, the top crown of described the second building-out capacitor, described low pressure NMOS pipe is connected with the positive input terminal of described operational amplifier; Described outer power voltage is connected with the bottom crown of the power end of the power end of described band gap reference, described operational amplifier, described the first building-out capacitor, source electrode and the substrate of described high-voltage power pipe; The bottom crown of the source electrode of the ground end of the ground end of described band gap reference, described operational amplifier, the other end of described the first resistance, described low pressure NMOS pipe and substrate, described the first electric capacity of voltage regulation is connected with ground voltage.
2. built-in analog power circuit according to claim 1, is characterized in that, described band gap reference, described operational amplifier, and described the first building-out capacitor and described high voltage PMOS power tube are high pressure resistant device.
3. built-in analog power circuit according to claim 1, is characterized in that, described the first electric capacity of voltage regulation, described the second building-out capacitor, described the second electric capacity of voltage regulation, described the first resistance, described the second resistance and described low pressure NMOS pipe are low-voltage device.
4. built-in analog power circuit according to claim 1, it is characterized in that, the dominant pole of described built-in analog power circuit is arranged on the output terminal of described operational amplifier, the inferior limit of described built-in analog power circuit is arranged on the internal simulation power output end of described built-in analog power circuit, and described internal simulation power output end is connected with the drain electrode of described high voltage PMOS power tube.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11095216B2 (en) | 2014-05-30 | 2021-08-17 | Qualcomm Incorporated | On-chip dual-supply multi-mode CMOS regulators |
| CN105373178B (en) | 2014-08-15 | 2018-02-02 | 深圳市中兴微电子技术有限公司 | Circuit start method, control circuit and voltage reference circuit |
| CN105700610B (en) * | 2016-01-29 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Ldo circuit |
| CN107749710B (en) * | 2017-11-15 | 2020-05-01 | 上海华虹宏力半导体制造有限公司 | LDO overshoot protection circuit and implementation method thereof |
| JP7079158B2 (en) * | 2018-06-27 | 2022-06-01 | エイブリック株式会社 | Voltage regulator |
| CN109002074A (en) * | 2018-09-12 | 2018-12-14 | 杰华特微电子（杭州）有限公司 | Linear voltage-stabilizing circuit, method for stabilizing voltage and the electric power management circuit using it |
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| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| CN102364407A (en) * | 2011-09-20 | 2012-02-29 | 苏州磐启微电子有限公司 | Novel low-dropout linear voltage regulator |
| CN202486647U (en) * | 2012-03-12 | 2012-10-10 | 北京经纬恒润科技有限公司 | Built-in analog power circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7088082B2 (en) * | 2003-12-16 | 2006-08-08 | Quick Logic Corporation | Regulator with variable capacitor for stability compensation |
| EP2354881A1 (en) * | 2010-02-05 | 2011-08-10 | Dialog Semiconductor GmbH | Domino voltage regulator (DVR) |
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Patent Citations (3)
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|---|---|---|---|---|
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| CN102364407A (en) * | 2011-09-20 | 2012-02-29 | 苏州磐启微电子有限公司 | Novel low-dropout linear voltage regulator |
| CN202486647U (en) * | 2012-03-12 | 2012-10-10 | 北京经纬恒润科技有限公司 | Built-in analog power circuit |
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