CN102594543B - Four frequency shift keying (4FSK) code element synchronizer applied to digital private mobile radio (dPMR) standard - Google Patents
Four frequency shift keying (4FSK) code element synchronizer applied to digital private mobile radio (dPMR) standard Download PDFInfo
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- 238000012937 correction Methods 0.000 claims description 4
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Abstract
The invention discloses a four frequency shift keying (4FSK) code element synchronizer applied to a digital private mobile radio (dPMR) standard. The 4FSK code element synchronizer comprises a sampling and quantification module, a phase discrimination module and a digital frequency synthesis module, wherein the sampling and quantification module samples a base-band signal by using an M-fold local reference lock, and divides each symbol period into M phases, and M is a positive integer; the phase discrimination module is used for performing hard decision on a sampled value, and calculating phase errors of corresponding phases; and the digital frequency synthesis module is used for finding a minimum error phase, comparing the found minimum error phase with a minimum error phase locked the last time to obtain a phase jitter value sigma, and correcting a symbol synchronization clock by using the phase jitter value sigma. The code element synchronizer is suitable for the synchronization of a continuously phase-modulated base-band signal; and moreover, when communication data is long, the accuracy of a synchronization clock also can be ensured.
Description
Technical field
The invention belongs to wireless communication field, relate to the demodulation in communication, a kind of 4FSK symbol synchronization device that is applied to dPMR standard particularly, can be applicable to the 4FSK modulation /demodulation of dPMR digital radio system.
Background technology
DPMR is the digital handset standard that ETSI (european telecommunication alliance) proposes for 2008, channel spacing 6.25KHz, and simplex pattern, adopts 4FSK modulation, provides two kinds of business: speech business and data service.DPMR modulator, through 2-4 level translation, makes each symbol carry 2 bit informations, and character rate is 2400sym/s, and information rate is 4.8Kb/s.
DPMR is 4 level, and each symbol carries 2bit information, and 4FSK modulation, so at the optimum sampling point of each symbol, be 4 kinds of discrete level.The corresponding relation of 4FSK symbol and bit is as shown in table 1:
Table 1
4FSK Deviation
| Di-bit | Symbol | Deviation |
| 01 | +3 | +1050Hz |
| 00 | +1 | +350Hz |
| 10 | -1 | -350Hz |
| 11 | -3 | -1050Hz |
Symbol synchronization device is the nucleus module of demodulation.Baseband signal after intermediate frequency demodulation, the matched filter through the same with modulated terminal, send in symbol synchronization device.Symbol synchronization device recovers the 4FSK symbol in baseband signal.
The 4FSK sign synchronization scheme of the conventional dPMR standard that is applied to has:
1, lead code synchronization scenario
According to the explanation in dPMR standard, when each data communication occurs, a string 72bit lead code is broadcasted at the head of data in capital: 5F 5F 5F 5F 5F 5F 5F 5F 5F is for sign synchronization, receiver is when receiving each communication data, capital first recovers an initial synchronisation clock according to lead code, as overall synchronised clock.This scheme is simply easy to realize, but higher to local clock required precision, and when communication data is longer, the error of accumulation can cause the synchronised clock at end very incorrect;
2, zero passage detection method synchronization scenario
4FSK modulation scheme for noncontinuous phase, each symbol period of baseband signal is the sine wave of discrete frequency, can carry out determination frequency f by detecting the number of times of zero crossing, and then obtain synchronised clock, synchronous but this scheme is not suitable for the baseband signal of Continuous Phase Modulation.
According to the modulation principle of dPMR standard, can obtain the 4FSK baseband waveform of Continuous Phase Modulation as shown in Figure 1, as can be seen from Figure 1, the optimum sampling point of dPMR pattern is not on crest or trough, waveform does not have any regularity yet, and this brings very large difficulty to demodulation.
Summary of the invention
The 4FSK symbol synchronization device that the object of this invention is to provide a kind of dPMR of being applied to standard.
The 4FSK symbol synchronization device that the present invention is applied to dPMR standard comprises:
Sample quantization module, this module with M doubly local reference clock baseband signal is sampled, each symbol period is divided into M phase place, M is positive integer;
Phase demodulation module, for sampled value is done to hard decision, calculates the phase error of corresponding phase; And
Numerical frequency synthesis module, for finding out minimal error phase place, the minimal error phase bit comparison with last time locking, obtains phase jitter value σ, with this phase jitter value σ correction symbol synchronised clock.
Preferably, described phase demodulation module comprises:
Sub module stored, for storing the sampled value in a continuous L symbol period; And
Calculating sub module, passes through formula
Calculate phase error, wherein, i represents i phase place in a symbol period, x
i+Mkthe sampled value that represents k i phase place in symbol period, hard (ι) represents hard decision.
Preferably, this symbol synchronization device also comprises digital filtering module, for the phase error that described phase demodulation module is calculated, does smothing filtering.
Preferably, described numerical frequency synthesis module comprises:
State judgement submodule, for the minimal error locking according to the last time
judge the current state of symbol synchronization device; And
Scope is determined submodule, for determining phase search scope according to the minimal error phase place of the current state of symbol synchronization device and last locking.
Preferably, the state of described symbol synchronization device comprises synchronous state and step-out state, searches for whole phase places under step-out state, and under synchronous state, search section is divided phase place.
Preferably, described state judgement submodule is by the minimal error of last time locking
with set point ERR
syncrelatively, when described minimal error
be greater than described set point ERR
synctime judge that symbol synchronization device is current in step-out state, otherwise judge that symbol synchronization device is current in synchronous state.
Preferably, this symbol synchronization device also comprises 4-2 level switch module, for being bit information by the 4FSK symbol transition of recovery, and output symbol synchronised clock.
The baseband signal that symbol synchronization device of the present invention can be applicable to Continuous Phase Modulation is synchronous, and when communication data is longer, also can guarantee that synchronised clock is correct.
Accompanying drawing explanation
Fig. 1 is the oscillogram of dPMR baseband signal.
Fig. 2 is the theory diagram of symbol synchronization device of the present invention.
Fig. 3 is that the error of phase demodulation module output of some embodiments of the invention symbol synchronization device is with the error curve of phase place.
Fig. 4 is some embodiments of the invention symbol synchronization device condition judgement schematic diagram.
Fig. 5 is some embodiments of the invention symbol synchronization device in once actual locking process, output error and phase-modulation temporal evolution curve.
Embodiment
The present invention is according to the discreteness of 4FSK symbol, a symbol period of baseband signal is divided into M phase place, calculate the error in each phase place, the positional information that is comprising 4FSK symbol in the error of phase place, then design the phase place that a set of efficient convergence algorithm finds error minimum in M phase place, carry out correction symbol synchronised clock.Below in conjunction with drawings and Examples, the four level baseband signallings of take in dPMR system are synchronously as example is described further technical solution of the present invention.
According to dPMR principles of modulation and demodulation, can obtain dPMR baseband waveform as shown in Figure 1.DPMR character rate is 2400sym/s, symbol period
Should comprise for the 4FSK symbol synchronization device of dPMR standard: sample quantization module 1, phase demodulation module 2, digital filtering module 3, numerical frequency synthesis module 4 (being DCO module) and 4-2 level switch module (not shown).
Sample quantization module 1 use M doubly local reference clock samples to baseband signal, and each symbol period is divided into M phase place, and M is positive integer.In the present embodiment, M value 16, sample frequency
t
srepresent symbol period, T '
sbe local reference clock cycle, σ represents the error of local reference clock cycle and symbol period, and this error amount is determined by the Crystal Oscillator Errors of transmitter and receiver, can be also negative for positive number.In each symbol period, there are like this 16 sampled points, i.e. 16 phase places.
In each symbol period, have M phase place, the corresponding phase error of each phase place, is comprising the positional information of optimum sampling point (4FSK symbol) in phase error.Phase demodulation module 2 can be done hard decision to sampled value, calculates the phase error of corresponding phase.
In some embodiment, phase demodulation module 2 comprises sub module stored and calculating sub module, and sub module stored is for storing the sampled value in a continuous L symbol period, and L is positive integer; Calculating sub module is calculated phase error by formula 1,
………………………………………1
Wherein, i represents i phase place in a symbol period, x
i+Mkthe sampled value that represents k i phase place in symbol period, hard (ι) represents hard decision.Hard (x
k) by formula 2, calculate,
………………………………………2。
In the present embodiment, L gets 4, M and gets 16,16 points of sampling in each symbol, and the sampled data of storing continuous 4 symbols, as calculating phase error, corresponding computing formula is suc as formula being:
That is: by each the corresponding phase place at 4 symbols, get sampled value, do hard decision, then ask the quadratic sum of the error of 4 same phases, obtain the phase error of this phase place.By calculating curve that error changes with phase place as shown in Figure 3, as seen from the figure, phase place is in center (phase place is correct), error equals 0, leading or hysteresis along with phase place, it is large that error can become, randomness due to code shape, at some phase point, also there will be local minimum, this is the problem that phase demodulation module must overcome, in order to proofread and correct by accelerating phase, and avoid the phase place of phase-locked loop to converge on Local Extremum, and to take into account the complexity of realization, 2 output phase error err of phase demodulation module (i), wherein
In order to strengthen the stability of numerical frequency synthesis module 4 inputs, be provided with digital filtering module 3, the error in each phase place is done to smothing filtering, specifically can realize by formula 3,
………………………………………3
Wherein N is positive integer.Its essence is the N continuous of a same phase place phase error is done on average.In the present embodiment, N gets 4, M and gets 16.
Numerical frequency synthesis module 4, by finding out minimal error phase place, is judged to be optimum sampling point position, and the minimal error phase bit comparison with last time locking, obtains phase jitter value σ, with this phase jitter value σ correction symbol synchronised clock.
In order to find efficiently minimal error phase place, in some embodiment, numerical frequency synthesis module 4 comprises that state judgement submodule and scope determine submodule, and state judgement submodule is for according to the minimal error of last time locking
judge the current state of symbol synchronization device; Scope determines that submodule is for determining phase search scope according to the minimal error phase place of the current state of symbol synchronization device and last locking.
More particularly, the state of symbol synchronization device is divided into synchronous state and step-out state.As shown in Figure 4, state judgement submodule is by the minimal error that the last time is locked
with set point ERR
syncrelatively, judge the current state of symbol synchronization device, when described minimal error
be greater than described set point ERR
synctime judge that symbol synchronization device is current in step-out state, otherwise judge that symbol synchronization device is current in synchronous state.By scope, determine that submodule makes under step-out state, to search for whole phase places, under synchronous state, a search section is divided phase place.If (i.e. last locking) minimal error phase place of locking is p in a upper symbol period.If current symbol synchronization device in synchronous state, determines that phase search scope is:
wherein, 0}b
1, b
2m,
if current symbol synchronization device in step-out state, determines that phase search scope is:
wherein, 0}c
1, c
2m,
for example, in the present embodiment, set ERR
sync=3, when the minimal error of last time locking
time, judge that current symbol synchronization device is in step-out state, when the minimal error of last time locking
time, judge that current symbol synchronization device is in synchronous state; At 2 output phase error err of above-mentioned phase demodulation module (i), wherein
time, can set hunting zone under synchronous state and be:
under step-out state, hunting zone is:
The sign synchronization clock of numerical frequency synthesis module 4 outputs, by sample frequency
through M frequency division, generate, this sign synchronization clock has M adjustable phase.Numerical frequency synthesis module 4 from
in find minimum error
obtain a phase jitter value σ, and then control character synchronised clock is done the phase place adjustment of σ.
4-2 level switch module 5, according to the mapping relations of dPMR symbol and bit (in Table 1), is bit information by the 4FSK symbol transition of recovery, and passes through output symbol synchronised clock after sign synchronization clock 2 frequencys multiplication.
Fig. 5 shows the present embodiment symbol synchronization device in once actual locking process, output error and phase-modulation temporal evolution curve.
Claims (6)
1. a 4FSK symbol synchronization device that is applied to dPMR standard, is characterized in that: comprise
Sample quantization module, this module with M doubly local reference clock baseband signal is sampled, each symbol period is divided into M phase place, M is positive integer;
Phase demodulation module, for sampled value is done to hard decision, calculates the phase error of corresponding phase; And
Numerical frequency synthesis module, for finding out minimal error phase place, the minimal error phase bit comparison with last time locking, obtains phase jitter value σ, with this phase jitter value σ correction symbol synchronised clock;
Described phase demodulation module comprises
Sub module stored, for storing the sampled value in a continuous L symbol period; And
Calculating sub module, passes through formula
Calculate phase error, wherein, x
i+Mkthe sampled value that represents k i phase place in symbol period, hard () represents hard decision.
2. symbol synchronization device according to claim 1, is characterized in that: this symbol synchronization device also comprises digital filtering module, and for the phase error that described phase demodulation module is calculated, do smothing filtering, this digital filtering module passes through formula
Realize, wherein, N is positive integer.
3. symbol synchronization device according to claim 2, is characterized in that: described numerical frequency synthesis module comprises
State judgement submodule, for the minimal error locking according to the last time
judge the current state of symbol synchronization device; And
Scope is determined submodule, for determining phase search scope according to the minimal error phase place of the current state of symbol synchronization device and last locking;
Described M=16, a described phase demodulation module output phase error err (i), i={ ± 6 wherein, ± 3, ± 1}.
4. symbol synchronization device according to claim 3, is characterized in that: the state of described symbol synchronization device comprises synchronous state and step-out state, and under step-out state, search for whole phase places, under synchronous state, search section is divided phase place.
5. symbol synchronization device according to claim 3, is characterized in that: described state judgement submodule is by the minimal error of last time locking
with set point ERR
syncrelatively, when described minimal error
be greater than described set point ERR
synctime judge that symbol synchronization device is current in step-out state, otherwise judge that symbol synchronization device is current in synchronous state.
6. symbol synchronization device according to claim 1, is characterized in that: this symbol synchronization device also comprises 4-2 level switch module, for being bit information by the 4FSK symbol transition of recovery, and output symbol synchronised clock.
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| CN102932305B (en) * | 2012-08-08 | 2015-07-01 | 清华大学深圳研究生院 | Code element synchronizer and code element synchronization method |
| CN106788955B (en) * | 2016-12-26 | 2020-06-19 | 中核控制***工程有限公司 | Four-phase high-speed code element detection method |
| CN107426812B (en) * | 2017-09-04 | 2020-01-14 | 中国电子科技集团公司第四十一研究所 | Universal code element recovery method applied to dPMR communication |
| CN114095071B (en) * | 2021-11-11 | 2024-04-19 | 成都中科微信息技术研究院有限公司 | Symbol synchronization method, readable medium and computing device of DVB-RCS2 system |
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| CN101568967A (en) * | 2007-11-26 | 2009-10-28 | 松下电器产业株式会社 | Phase comparator, PLL circuit, information regeneration processing apparatus, optical disc regenerating apparatus, and magnetic disc regenerating apparatus |
| CN102332972A (en) * | 2010-05-31 | 2012-01-25 | 索尼公司 | Phase synchronization equipment, phase synchronization method and phase synchronizing program |
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| CN101568967A (en) * | 2007-11-26 | 2009-10-28 | 松下电器产业株式会社 | Phase comparator, PLL circuit, information regeneration processing apparatus, optical disc regenerating apparatus, and magnetic disc regenerating apparatus |
| CN102332972A (en) * | 2010-05-31 | 2012-01-25 | 索尼公司 | Phase synchronization equipment, phase synchronization method and phase synchronizing program |
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