CN102593177A - Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof - Google Patents
Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof Download PDFInfo
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Abstract
The invention provides a tunneling transistor with a horizontal quasi coaxial cable structure and a forming method thereof. The tunneling transistor comprises a semiconductor substrate, a channel region, a drain region or a source region and a gate structure, wherein the semiconductor substrate has a first doping type; the semiconductor substrate is a source region or a drain region; the channel region is formed on the semiconductor substrate; an insulating layer is formed in the region on the semiconductor substrate, in which the channel region is not formed; the drain region or the source region is formed on the channel region and the insulating layer and has a second doping type; a first part of the channel region is coated by a first part of the drain region or the source region; the gate structure is formed on the first part of the drain region or the source region; and the first part of the drain region or the source region is coated by the gate structure. According to the tunneling transistor provided by the embodiment of the invention, the driving capacity of a TFET (Tunneling Field Effect Transistor) device can be improved.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of tunneling transistor and forming method thereof with the accurate coaxial cable structure of level.
Background technology
For a long time, in order to obtain higher chip density, operating rate and lower power consumption faster.It is constantly scaled that the characteristic size of metal-oxide semiconductor fieldeffect transistor (MOSFET) is being followed so-called Moore's Law (Moore ' s law) always, and its operating rate is more and more faster.The current scope that has entered into nanoscale.Yet; Serious challenge of the thing followed is short-channel effect to have occurred; For example subthreshold voltage drop (Vt roll-off), drain electrode cause that potential barrier reduces (DIBL), break-through phenomenons such as (punch through) is leaked in the source; Make the off-state leakage current of device enlarge markedly, thereby cause performance to worsen.
Current, in order to reduce the negative effect that short-channel effect brings, people have proposed various corrective measures, and wherein particularly outstanding is tunneling field-effect transistor (tunneling field effect transistor, TFET).Because when the MOSFET device was in the subthreshold value state, device was weak transoid, this moment, thermionic emission was main conductive mechanism, and therefore, at room temperature the sub-threshold slope of MOSFET is subject to 60mV/dec.For traditional MOSFET, on the one hand, because the active area of tunneling field-effect transistor device is essentially tunnel junctions, therefore, tunneling field-effect transistor has more weak even does not have short-channel effect; Simultaneously; The main current machine of tunneling field-effect transistor is made as band-band tunnelling (band-to-band tunneling); Be exponential relationship in sub-threshold region and saturation region drain current with the gate source voltage that adds; Therefore tunneling field-effect transistor has lower sub-threshold slope, and electric current receives Influence of Temperature hardly.
The preparation technology of tunneling field-effect transistor is compatible mutually with traditional complementary type metal-oxide semiconductor fieldeffect transistor (CMOSFET) technology.The transistorized structure of TFET is based on the p-i-n diode of Metal-oxide-semicondutor grid-control, and is as shown in Figure 1, is typical n type raceway groove TFET in the prior art.Particularly; N type raceway groove TFET comprises source region 1000 ' and N type impure drain region 2000 ' that a P type mixes; Kept apart by a channel region 3000 ' between source region and the drain region, grid pile up 4000 ' and comprise a gate dielectric layer and a gate electrode that is positioned at the channel region top.
Closed condition at the TFET device; When promptly not applying grid voltage; What form between source region 1000 ' and the drain region 2000 ' becomes back-biased diode; And the potential barrier that the potential barrier of being set up by reversed biased diodes is set up greater than complementary type MOSFET usually, therefore, even the sub-threshold leakage current and the direct Tunneling electric current of this TFET device when just having caused channel length very short reduce greatly.When the grid to TFET applies voltage; The channel region 3000 ' of device produces the passage of an electronics under the effect of field effect; In case the electron concentration generation degeneracy in the raceway groove; Between source region 1000 ' and channel region 3000 ', will form a tunnel junctions so, the tunnelling current that tunnelling produces is through this tunnel junctions.From the angle that can be with, this tunneling field-effect transistor based on grid-control P-I-N diode structure is a length of tunnel of regulating formed PN junction between source region 1000 ' and the channel region 3000 ' through the control gate pole tension.
The shortcoming of the TFET device of existing horizontal tunnelling is: because the sectional area of horizontal tunnelling is less, cause drive current too small, influence the driveability of TFET device.
Summary of the invention
The object of the invention is intended to solve at least one of above-mentioned technological deficiency, particularly solves or avoid to occur the above-mentioned shortcoming of TFET device.
For achieving the above object, one aspect of the present invention proposes a kind of tunneling transistor with the accurate coaxial cable structure of level, and comprising: have the Semiconductor substrate of first doping type, said Semiconductor substrate is source region or drain region; Be formed on the channel region on the said Semiconductor substrate, wherein, the zone that does not form said channel region on the said Semiconductor substrate is formed with insulating barrier; Be formed on drain region with second doping type or source region on said channel region and the insulating barrier, the first in said drain region or source region coats the first of said channel region; Be formed on the grid structure in the first in said drain region or source region, said grid structure coats the first in said drain region or source region.
In one embodiment of the invention, said channel region is semiconductor nanowires or the nano belt that is formed on the said Semiconductor substrate.The channel region that forms through grow nanowire or nano belt can further form double grid or ring grid (gate-all-around) structure above that, helps increasing the control ability of grid to channel region, improves effective electric field, increases the tunnelling probability.
In one embodiment of the invention, the material in said drain region or source region comprises: a kind of in Ge, SiGe, strain Si or the III-V family material.These semi-conducting materials not only can form heterojunction, and energy gap is little, help increasing the tunnelling probability of TFET.
In one embodiment of the invention, said drain region or source region are that extension forms on the first surface of said channel region and said insulating barrier, thereby the thickness that can make said drain region or source region is less than 10nm, to reduce the tunnelling path of TFET effectively.
In one embodiment of the invention, said drain region or source region are the heavy doping of P type, and said channel region is P type weak doping, N type weak doping or intrinsic, and said Semiconductor substrate is the heavy doping of N type; Perhaps said drain region or source region are the heavy doping of N type, and said channel region is N type weak doping, P type weak doping or intrinsic, and said Semiconductor substrate is the heavy doping of P type.Wherein, when the source region is the heavy doping of P type, channel region is P type weak doping, N type weak doping or intrinsic, when the drain region is the heavy doping of N type, constitutes N type tunneling field-effect transistor; When the source region is the heavy doping of N type, channel region is P type weak doping, N type weak doping or intrinsic, when the drain region is the heavy doping of P type, constitutes P type tunneling field-effect transistor.
In one embodiment of the invention, said channel region comprises second portion, and the second portion of said channel region is not coated by the first in said drain region or source region, is formed with first electrode on the second portion of said channel region; Said drain region or source region comprise second portion, and the second portion in said drain region or source region covers on the said insulating barrier, are formed with second electrode on the second portion in said drain region or source region.Wherein, because channel region contacts with Semiconductor substrate (being source region or drain region), so first electrode is source electrode or drain electrode, second electrode is drain electrode or source electrode accordingly.
The present invention also proposes a kind of formation method with tunneling transistor of the accurate coaxial cable structure of level on the other hand, may further comprise the steps: Semiconductor substrate is provided, said Semiconductor substrate is carried out the first kind mix to form source region or drain region; On said Semiconductor substrate, form channel region; The zone that on said Semiconductor substrate, does not form said channel region forms insulating barrier; On said channel region and insulating barrier, form drain region or source region; The doping of second type is carried out in said drain region or source region; The first in said drain region or source region coats the first of said channel region; The second portion in said drain region or source region covers on the said insulating barrier, and the second portion of said channel region exposes; In the first in said drain region or source region, form the grid structure, said grid structure coats the first in said drain region or source region.
In one embodiment of the invention, form said channel region and comprise: growing semiconductor nano wire or nano belt on said Semiconductor substrate, to form said channel region.The channel region that forms through grow nanowire or nano belt can further form double grid or ring grid (gate-all-around) structure above that, helps increasing the control ability of grid to channel region, improves effective electric field, increases the tunnelling probability.
In one embodiment of the invention, the material in said drain region or source region comprises: Ge, SiGe, strain Si or III-V family material.These semi-conducting materials not only can form heterojunction, and energy gap is little, help increasing the tunnelling probability of TFET.
In one embodiment of the invention, forming said drain region or source region comprises: epitaxial growth drain region or source region material layer on said channel region and insulating barrier; According to said drain region of predetermined pattern etching or source region material layer, to form said drain region or source region; The doping of second type is carried out in said drain region or source region.10nm can be less than through the drain region of epitaxial growth formation or the thickness in source region, thereby the tunnelling path of TFET can be reduced effectively.
In one embodiment of the invention, forming said grid structure comprises: in the first in said drain region or source region, form dielectric layer of high dielectric constant; According to the said dielectric layer of high dielectric constant of predetermined pattern etching, to form gate dielectric layer, said gate dielectric layer coats the first in said drain region or source region.The high-k gate dielectric layer that forms through deposit can reach equivalent oxide thickness EOT less than 1nm.
In one embodiment of the invention; Also comprise after forming said gate dielectric layer: on said gate dielectric layer, form gate electrode; On the second portion of said channel region, form first electrode, and on the second portion in said drain region or source region, form second electrode.Wherein, because channel region contacts with Semiconductor substrate (being source region or drain region), so first electrode is source electrode or drain electrode, second electrode is drain electrode or source electrode accordingly.
In one embodiment of the invention; Forming said source region, drain region and channel region comprises: said Semiconductor substrate is carried out the heavy doping of N type to form said source region or drain region; The heavy doping of P type is carried out in said drain region or source region, and said channel region is carried out P type weak doping, N type weak doping or intrinsic; Perhaps, said Semiconductor substrate is carried out the heavy doping of P type to form said source region or drain region, the heavy doping of N type is carried out in said drain region or source region, and said channel region is carried out P type weak doping, N type weak doping or intrinsic.
The present invention provides a kind of tunneling transistor with the accurate coaxial cable structure of level and forming method thereof; Through channel region, source region, drain region being arranged in structure with horizontal direction coaxial cable; Ring-type tunnelling cross section from the source region to the channel region is with respect to common planar tunnelling cross section; The tunnelling sectional area increases greatly, and grid significantly strengthen the control ability of channel region, thereby improves the driving force of TFET device.In addition, owing to the tunneling transistor according to the embodiment of the invention is the horizontal structure that is formed on the substrate,, and help the integrated of semiconductor device so its manufacturing approach can be compatible with the semiconductor fabrication of existing horizontal structure.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is typical n type tunneling field-effect transistor structure chart in the prior art;
Fig. 2 is the vertical view of the TFET structure with the accurate coaxial cable structure of level of the embodiment of the invention;
Fig. 3-5 is respectively along the profile of the line AA ' in the vertical view of the TFET structure with the accurate coaxial cable structure of level shown in Figure 2, BB ', CC ';
Fig. 6-15 is the section of structure of each step of formation method of the TFET structure with the accurate coaxial cable structure of level of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
Fig. 2 is the structure vertical view of the TFET with the accurate coaxial cable structure of level of the embodiment of the invention, and Fig. 3-5 is respectively along the profile of the line AA ' among Fig. 2, BB ', CC '.Shown in Fig. 2-5, comprise according to the TFET with the accurate coaxial cable structure of level of the embodiment of the invention: have the Semiconductor substrate 100 of first doping type, Semiconductor substrate 100 is source region or drain region (for for simplicity, source region or drain region also are 100); Be formed on the channel region 200 on the Semiconductor substrate 100, wherein, the zone that does not form channel region 200 on the Semiconductor substrate 100 is formed with insulating barrier 300; Be formed on drain region with second doping type or source region 400 on channel region 200 and the insulating barrier 300, the first 401 in drain region or source region coats the first 201 of channel regions; Be formed on the grid structure 500 in the first in drain region or source region 400, the first 401 in grid structure 500 coating drain regions or source region.
What need explanation is, in various embodiments of the present invention, as drain region 100, is formed on structure on channel region 200 and the insulating barrier 300 as source region 400 with Semiconductor substrate 100.More than limit and be merely example, for source-drain area is exchanged the tunneling transistor arrangement with the accurate coaxial cable structure of level that obtains, it does not break away from principle of the present invention and spirit, then is included within protection scope of the present invention equally.
According to the TFET of the embodiment of the invention, can know from profile (Fig. 4) along BB ' vertical view Fig. 1, internal layer channel region 200, source region, intermediate layer 400 and and the drain region 100 that is positioned at the two bottom constitute three layers of accurate coaxial cable structure of level.Wherein, Source region 400 is coated on the surface of channel region 200; Thereby make this TFET structure 500 tunnelling cross section is ring-type or type ring-type tunnelling cross section to the source region from channel region 200, with respect to the tunnelling cross section, plane of general T FET, the tunnelling sectional area increases greatly; Grid significantly strengthen the control ability of channel region, thereby improve the driving force of TFET device.
The material of Semiconductor substrate 100 can comprise semi-conducting materials such as silicon, germanium, diamond, carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes strengthening its performance, and also can comprise silicon-on-insulator (SOI) structure.In the present embodiment, the material of substrate is a silicon.
In the preferred embodiment of the invention, channel region 200 is for being formed on semiconductor nanowires or the nano belt on the Semiconductor substrate 100.The channel region that forms through grow nanowire or nano belt can further form double grid or ring grid (gate-all-around) structure above that, helps increasing the control ability of grid to channel region, improves effective electric field, increases the tunnelling probability.The material of channel region 200 can be the material that is suitable as channel region known in those skilled in the art, for example silicon.
In embodiments of the present invention, the material in source region 400 can comprise a kind of in Ge, SiGe, strain Si or the III-V family material, and these semi-conducting materials not only can form heterojunction, and energy gap is little, help increasing the tunnelling probability of TFET.Source region 400 can be for forming in the first 201 of channel region and the surperficial extension of insulating barrier 300, and the thickness in source region 400 can be less than 10nm, and less source region thickness can reduce the tunnelling path of TFET effectively.
In embodiments of the present invention, grid structure 500 comprises gate dielectric layer 502 and gate electrode 504, like Fig. 2 and shown in Figure 4.The material of gate dielectric layer 502 can be oxide, for example SiO
2Or the high K medium material, comprise for example hafnium sill, like hafnium oxide (HfO2); Hafnium silicon oxide (HfSiO), nitrogen hafnium silicon oxide (HfSiON), hafnium oxide tantalum (HfTaO); Hafnium oxide titanium (HfTiO), hafnium oxide zirconium (HfZrO), its combination and/or other suitable material.The material of gate electrode 504 can be polysilicon or metal.
In embodiments of the present invention, source region 400 is the heavy doping of P type, and channel region 200 is P type weak doping, N type weak doping or intrinsic, and drain region 100 is the heavy doping of N type, to constitute N type TFET; Source region 400 is the heavy doping of N type, and channel region 200 is N type weak doping, P type weak doping or intrinsic, and drain region 100 is the heavy doping of P type, to constitute P type TFET.
In embodiments of the present invention; Channel region 200 comprises second portion 202; The second portion 202 of channel region is not coated by the first 401 in source region, is formed with first electrode 204 on the second portion 202 of channel region, like Fig. 2 and shown in Figure 5; Because channel region 200 contacts with Semiconductor substrate 100, so first electrode 204 is drain electrode; Source region 400 comprises second portion 402, and the second portion 402 in source region covers on the insulating barrier 300, is formed with second electrode, 404, the second electrodes 404 on the second portion 402 in source region and is the source electrode, as shown in Figures 2 and 3.
Fig. 6-15 is the structure vertical view and the corresponding profile thereof of each step of formation method of the TFET structure with the accurate coaxial cable structure of level of the embodiment of the invention.What need explanation is, the embodiment of the invention is that example describes should the formation method to form N type TFET, and the formation method of P type TFET can repeat no more at this with reference to following step.Formation method according to the embodiment of the invention may further comprise the steps.
Step S101: Semiconductor substrate 100 is provided, Semiconductor substrate 100 is carried out the first kind mix to form source region or drain region.The material of Semiconductor substrate 100 can comprise semi-conducting materials such as silicon, germanium, diamond, carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes strengthening its performance, and also can comprise silicon-on-insulator (SOI) structure.In the present embodiment, the material of substrate is a silicon, and silicon substrate 100 is carried out the heavy doping of N type to form drain region 100.
Step S102: on Semiconductor substrate 100, form channel region 200, like Fig. 6 and shown in Figure 7, wherein, Fig. 6 is the structure vertical view of this step, and Fig. 7 is the profile along BB ' among Fig. 6.In embodiments of the present invention, can carry out P type weak doping, N type weak doping or intrinsic to channel region 200.The material of channel region 200 can be the material that is suitable as channel region known in those skilled in the art, for example silicon.Channel region 200 can form through photoetching process, in the preferred embodiment of the invention, can Semiconductor substrate 100 on growing semiconductor nano wire or nano belt (for example Si nano wire or nano belt) to form channel region 200.The channel region that forms through grow nanowire or nano belt can further form double grid or ring grid (gate-all-around) structure above that, helps increasing the control ability of grid to channel region, improves effective electric field, increases the tunnelling probability.
Step S103: the zone that on Semiconductor substrate 100, does not form channel region 200 forms insulating barrier 300.In embodiments of the present invention, can be on Semiconductor substrate 100 deposition insulating layer (SiO for example
2), perhaps surface of silicon substrate is carried out oxidation to form SiO
2Insulating barrier is implemented photoetching, etching then, removes the SiO on the channel region 200
2The insulating barrier part, like Fig. 8 and shown in Figure 9, wherein, Fig. 8 is the structure vertical view of this step, Fig. 9 is the profile along BB ' among Fig. 8.
Step S104: on channel region 200 and insulating barrier 300, form source region 400; Second type is carried out in source region 400 mixes; The first 401 in source region coats the first 201 of channel region, and the second portion 402 in source region covers on the insulating barrier 300, and the second portion 202 of channel region exposes.Forming source region 400 specifically can may further comprise the steps:
(4-1) epitaxial growth source region material layer 403 on channel region 200 and insulating barrier 300, like Figure 10 and shown in Figure 11, wherein, Figure 10 is the structure vertical view of this step, Figure 11 is the profile along BB ' among Figure 10.The material of source region material layer 403 can comprise a kind of in Ge, SiGe or the III-V family material, and these semi-conducting materials not only can form heterojunction, and energy gap is little, help increasing the tunnelling probability of TFET.In embodiments of the present invention, the material of source region material layer 403 is SiGe.
(4-2) according to predetermined pattern etching source region material layer 403 to form source region 400, make the first 401 in source region coat the first 201 of channel regions, the second portion 402 in source region is positioned on the insulating barrier 300, the second portion 202 of channel region exposes.Like Figure 12 and shown in Figure 13, wherein, Figure 12 is this step structure vertical view, and Figure 13 is the profile along DD ' among Figure 12.The thickness in the source region that forms through epitaxial growth can be less than 10nm, thereby can reduce the tunnelling path of TFET effectively.
(4-3) second type being carried out in source region 400 mixes.In embodiments of the present invention, the heavy doping of P type is carried out in the source region.
Step S105: in the first 401 in source region, form grid structure 500, the first 401 in grid structure 500 coating source regions.In embodiments of the present invention, forming grid structure 700 can may further comprise the steps:
(5-1) in the first 401 in source region, form the high K medium layer.In embodiments of the present invention, can for example comprise the hafnium sill through deposit high K medium material; Like hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), nitrogen hafnium silicon oxide (HfSiON); Hafnium oxide tantalum (HfTaO); Hafnium oxide titanium (HfTiO), hafnium oxide zirconium (HfZrO), its combination and/or other suitable material are to form the high K medium layer.The deposit of high K medium material can be adopted conventional depositing technics, for example chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or additive method.
(5-2) according to this high K medium layer of predetermined pattern etching, to form gate dielectric layer 702, the first 401 in gate dielectric layer 702 coating source regions.Like Figure 14 and shown in Figure 15, wherein, Figure 14 is the structure vertical view of this step, and Figure 15 is the profile along BB ' among Figure 14.The gate dielectric layer that mode through deposit high K medium material forms can reach equivalent oxide thickness EOT less than 1nm.
In embodiments of the present invention; After step S105; Also be included in and form gate electrode 504 on the gate dielectric layer 502; Go up formation first electrode 204 at the second portion 202 (part that is not covered) of channel region 200, owing to channel region 200 contacts with Semiconductor substrate 100, so first electrode 204 is drain electrode by the first 401 in source region; And formation second electrode 404, the second electrodes 404 are the source electrode on the second portion 402 in source region, shown in Fig. 2-5.
The present invention provides a kind of tunneling transistor with the accurate coaxial cable structure of level and forming method thereof; Through channel region, source region, drain region being arranged in structure with horizontal direction coaxial cable; Ring-type tunnelling cross section from the source region to the channel region is with respect to common planar tunnelling cross section; The tunnelling sectional area increases greatly, and grid significantly strengthen the control ability of channel region, thereby improves the driving force of TFET device.In addition, owing to the tunneling transistor according to the embodiment of the invention is the horizontal structure that is formed on the substrate,, and help the integrated of semiconductor device so its manufacturing approach can be compatible with the semiconductor fabrication of existing horizontal structure.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means the concrete characteristic, structure, material or the characteristics that combine this embodiment or example to describe and is contained at least one embodiment of the present invention or the example.In this manual, the schematic statement to above-mentioned term not necessarily refers to identical embodiment or example.And concrete characteristic, structure, material or the characteristics of description can combine with suitable manner in any one or more embodiment or example.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (13)
1. the tunneling transistor with the accurate coaxial cable structure of level is characterized in that, comprising:
Semiconductor substrate with first doping type, said Semiconductor substrate are source region or drain region;
Be formed on the channel region on the said Semiconductor substrate, wherein, the zone that does not form said channel region on the said Semiconductor substrate is formed with insulating barrier;
Be formed on drain region with second doping type or source region on said channel region and the insulating barrier, the first in said drain region or source region coats the first of said channel region;
Be formed on the grid structure in the first in said drain region or source region, said grid structure coats the first in said drain region or source region.
2. the tunneling transistor with the accurate coaxial cable structure of level as claimed in claim 1 is characterized in that, said channel region is semiconductor nanowires or the nano belt that is formed on the said Semiconductor substrate.
3. the tunneling transistor with the accurate coaxial cable structure of level as claimed in claim 1 is characterized in that, the material in said drain region or source region comprises: Ge, SiGe, strain Si or III-V family material.
4. the tunneling transistor with the accurate coaxial cable structure of level as claimed in claim 1; It is characterized in that; Said drain region or source region are that extension forms on the first surface of said channel region and said insulating barrier, and the thickness in said drain region or source region is less than 10nm.
5. the tunneling transistor with the accurate coaxial cable structure of level as claimed in claim 1 is characterized in that:
Said drain region or source region are the heavy doping of P type, and said channel region is P type weak doping, N type weak doping or intrinsic, and said Semiconductor substrate is the heavy doping of N type; Perhaps
Said drain region or source region are the heavy doping of N type, and said channel region is N type weak doping, P type weak doping or intrinsic, and said Semiconductor substrate is the heavy doping of P type.
6. the tunneling transistor with the accurate coaxial cable structure of level as claimed in claim 1 is characterized in that:
Said channel region comprises second portion, and the second portion of said channel region is not coated by the first in said drain region or source region, is formed with first electrode on the second portion of said channel region;
Said drain region or source region comprise second portion, and the second portion in said drain region or source region covers on the said insulating barrier, are formed with second electrode on the second portion in said drain region or source region.
7. the formation method with tunneling transistor of the accurate coaxial cable structure of level is characterized in that, may further comprise the steps:
Semiconductor substrate is provided, said Semiconductor substrate is carried out the first kind mix to form source region or drain region;
On said Semiconductor substrate, form channel region;
The zone that on said Semiconductor substrate, does not form said channel region forms insulating barrier;
On said channel region and insulating barrier, form drain region or source region; The doping of second type is carried out in said drain region or source region; The first in said drain region or source region coats the first of said channel region; The second portion in said drain region or source region covers on the said insulating barrier, and the second portion of said channel region exposes;
In the first in said drain region or source region, form the grid structure, said grid structure coats the first in said drain region or source region.
8. the formation method with tunneling transistor of the accurate coaxial cable structure of level as claimed in claim 7 is characterized in that, forms said channel region and comprises: growing semiconductor nano wire or nano belt on said Semiconductor substrate, and to form said channel region.
9. the formation method with tunneling transistor of the accurate coaxial cable structure of level as claimed in claim 7 is characterized in that the material in said drain region or source region comprises: Ge, SiGe, strain Si or III-V family material.
10. the formation method with tunneling transistor of the accurate coaxial cable structure of level as claimed in claim 7 is characterized in that, forms said drain region or source region and comprises:
Epitaxial growth drain region or source region material layer on said channel region and insulating barrier;
According to said drain region of predetermined pattern etching or source region material layer, to form said drain region or source region;
The doping of second type is carried out in said drain region or source region.
11. the formation method with tunneling transistor of the accurate coaxial cable structure of level as claimed in claim 7 is characterized in that, forms said grid structure and comprises:
In the first in said drain region or source region, form dielectric layer of high dielectric constant;
According to the said dielectric layer of high dielectric constant of predetermined pattern etching, to form gate dielectric layer, said gate dielectric layer coats the first in said drain region or source region.
12. the formation method with tunneling transistor of the accurate coaxial cable structure of level as claimed in claim 11; It is characterized in that; Also comprise after forming said gate dielectric layer: on said gate dielectric layer, form gate electrode; On the second portion of said channel region, form first electrode, and on the second portion in said drain region or source region, form second electrode.
13. the formation method with tunneling transistor of accurate coaxial cable structure as claimed in claim 7 is characterized in that, forms said source region, drain region and channel region and comprises:
Said Semiconductor substrate is carried out the heavy doping of N type to form said source region or drain region, the heavy doping of P type is carried out in said drain region or source region, and said channel region is carried out P type weak doping, N type weak doping or intrinsic; Perhaps
Said Semiconductor substrate is carried out the heavy doping of P type to form said source region or drain region, the heavy doping of N type is carried out in said drain region or source region, and said channel region is carried out P type weak doping, N type weak doping or intrinsic.
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| CN201210035782.3A CN102593177B (en) | 2012-02-16 | 2012-02-16 | Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof |
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| US20080303083A1 (en) * | 2007-06-06 | 2008-12-11 | Elpida Memory, Inc. | Semiconductor apparatus and production method of the same |
| CN101483192A (en) * | 2009-02-11 | 2009-07-15 | 西安交通大学 | Vertical fense MOSFET device and manufacturing method thereof |
| CN102214586A (en) * | 2011-06-13 | 2011-10-12 | 西安交通大学 | Preparation method of silicon nano-wire field-effect transistor |
| CN102254948A (en) * | 2011-07-29 | 2011-11-23 | 北京大学 | Tunneling field effect transistor with double-gate structure and preparing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080303083A1 (en) * | 2007-06-06 | 2008-12-11 | Elpida Memory, Inc. | Semiconductor apparatus and production method of the same |
| CN101483192A (en) * | 2009-02-11 | 2009-07-15 | 西安交通大学 | Vertical fense MOSFET device and manufacturing method thereof |
| CN102214586A (en) * | 2011-06-13 | 2011-10-12 | 西安交通大学 | Preparation method of silicon nano-wire field-effect transistor |
| CN102254948A (en) * | 2011-07-29 | 2011-11-23 | 北京大学 | Tunneling field effect transistor with double-gate structure and preparing method thereof |
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