CN102569217A - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- CN102569217A CN102569217A CN201110458334XA CN201110458334A CN102569217A CN 102569217 A CN102569217 A CN 102569217A CN 201110458334X A CN201110458334X A CN 201110458334XA CN 201110458334 A CN201110458334 A CN 201110458334A CN 102569217 A CN102569217 A CN 102569217A
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- groove
- crooked
- substrate
- package part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
A semiconductor package is provided in the invention. The substrate has an upper side and a lower side facing with the upper side. The substrate comprises a recess formed in the upper side, a bond finger which is exposed by the recess, and a Borland. A semiconductor chip has a one side and the other side facing with the one side. The semiconductor chip comprises a bonding pad arranged on the one side, and a bump formed on the bonding pad. The semiconductor chip is mounted on the upper side of the substrate with a face-down type in order to be opposite to the upper side of the substrate.
Description
Technical field
The present invention relates in general to a kind of semiconductor package part, particularly a kind of semiconductor package part that utilizes the bending realization of semiconductor chip.
Background technology
Usually, the semiconductor chip in the semiconductor package part adheres to the upper surface of substrate, and substrate is electrically connected to semiconductor chip through lead-in wire, and the upper surface of substrate is sealed to cover semiconductor chip and lead-in wire.
In order to satisfy the ever-increasing big capacity requirement of modern semiconductor products, having more jumbo semiconductor chip need be installed in the semiconductor package part.Yet, have the restriction that increases semiconductor chip self capacity.In order to reach the big capacity of expectation, the semiconductor package part of stacked comprises two or the semiconductor chip that piles up that is encapsulated in wherein.
The semiconductor chip attenuate can be realized the high integration of semiconductor package part; Yet semiconductor chip made thin bends to the shape (smile-shape) of similar smile easily, and for example, in the supine structure that faces up of active face, the marginal portion of semiconductor chip is bent upwards.
When the form that is bent upwards with the marginal portion when semiconductor chip is crooked; The whole surface that bending has hindered semiconductor chip attaches on the substrate; And when chip surface does not attach on the substrate securely, it will cause difficulty in wire bonds technology subsequently.Because crooked semiconductor chip, possibly make not only can not stacked semiconductor chips, and can not carry out wire bonds technology.
Summary of the invention
Embodiments of the invention provide a kind of semiconductor package part, and it can avoid the bad installation of semiconductor chip.
In addition, embodiments of the invention provide a kind of semiconductor package part of stacked, and it can avoid bad installation, and can realize the high-density installation of semiconductor chip.
In an embodiment of the present invention, semiconductor package part can comprise: substrate has upper surface and back to the lower surface of upper surface, and comprises the groove that is limited on the upper surface; And semiconductor chip, be mounted to the upper surface of substrate, have towards surface of upper surface and back to another surface on this surface, and bend to the shape of smile, make the curved edge of semiconductor chip partly be inserted in the groove.
Groove can be limited to two positions that the marginal portion is corresponding with semiconductor chip, and semiconductor chip can be installed as and makes two marginal portions of semiconductor chip be inserted in the corresponding groove respectively.
Groove can be limited to a position that the marginal portion is corresponding with semiconductor chip, and semiconductor chip can be installed as and makes semiconductor chip have only a marginal portion to be inserted in the groove.
Semiconductor package part may further include adhering part, and this bonding portion is inserted between the surface of upper surface and semiconductor chip of substrate.
Substrate can comprise that joint refers to that it is arranged on the surface of exposing via groove, and insert in the groove marginal portion of semiconductor chip.
Semiconductor chip can comprise bond pad, and bond pad is formed on the marginal portion of inserting in the lip-deep groove, is arranged to refer to towards joint, and refers to be electrically connected with engaging.
Semiconductor chip may further include the projection that is formed on the bond pad.
Semiconductor chip can comprise the bond pad of the mid portion that is formed on a surface; And being formed on a lip-deep redistribution lines, it has an end that connects bond pad and the other end that extends from an end, be arranged to refer to towards joint, and the electrical connection joint refers to.
Semiconductor chip may further include the projection on the other end that is formed on redistribution lines.
Substrate can comprise one or more further groove, and it limits with respect to this groove at regular intervals; And additional the joint refer to, is arranged on the surface of exposing via further groove.
Semiconductor package part may further include one or more additional semiconductor chips; It is installed on the upper surface of substrate; Isolate with semiconductor chip, and bend to the shape of smile, make the curved edge of additional semiconductor chip partly be inserted in the further groove.
Each additional semiconductor chip can comprise additional bond pad, and this bond pad is formed on the marginal portion on a surface, to be inserted in the further groove, is arranged to refer to towards additional the joint, and is electrically connected to additional the joint and refers to.
Each additional semiconductor chip may further include the additional bump that is formed on the additional bond pad.
Semiconductor package part may further include additional adhering part, between the additional semiconductor chip of additional adhering part insertion semiconductor chip and adjacency and between the additional semiconductor chip.
Semiconductor package part may further include the enclose components of the upper surface that covers semiconductor chip and substrate; And attach to the outside installation component on the upper surface of substrate.
In an embodiment of the present invention, semiconductor package part comprises: substrate has upper surface and back to the lower surface of upper surface, and comprises the groove that is limited on the upper surface; Semiconductor chip is mounted to the upper surface of substrate, has towards surface of upper surface and back to another surface on this surface, and comprises flat structures; And one or more additional semiconductor chips, be stacked on the semiconductor chip, bend to the shape of smile, make the curved edge of additional semiconductor chip partly be inserted in the further groove of substrate.
Substrate can comprise: joint refers to, is arranged on the upper surface with semiconductor chip and setting additional semiconductor chip above that, and is electrically connected semiconductor chip; And refer to via the additional joint that further groove is exposed, and each additional semiconductor chip can comprise additional bond pad, additional bond pad is arranged on the marginal portion and refers to be inserted in the further groove and to be electrically connected additional the joint.
Semiconductor package part may further include the additional bump that is formed on the additional bond pad.
Semiconductor package part may further include the enclose components of the upper surface that covers semiconductor chip, additional semiconductor chip and substrate; And the outside installing component that attaches to the lower surface of substrate.
Description of drawings
Fig. 1 is the sectional view that illustrates according to the semiconductor package part of the embodiment of the invention.
Fig. 2 is the plane graph that substrate shown in Figure 1 is shown.
Fig. 3 illustrates the sectional view of semiconductor package part in accordance with another embodiment of the present invention.
Fig. 4 is the sectional view that semiconductor chip shown in Figure 3 is shown.
Fig. 5 illustrates the sectional view of stacked type semiconductor package part in accordance with another embodiment of the present invention.
Fig. 6 illustrates the sectional view of stacked type semiconductor package part in accordance with another embodiment of the present invention.
Fig. 7 illustrates the sectional view of stacked type semiconductor package part in accordance with another embodiment of the present invention.
Fig. 8 illustrates the sectional view of stacked type semiconductor package part in accordance with another embodiment of the present invention.
Embodiment
To combine accompanying drawing that specific embodiment of the present invention is explained in detail below.
It is understandable that here accompanying drawing is not necessarily proportionally drawn, and possibly amplify ratio in some cases with clearer description characteristics more of the present invention.
Fig. 1 is the sectional view that illustrates according to the semiconductor package part of the embodiment of the invention, and Fig. 2 is the plane graph that substrate shown in Figure 1 is shown.
With reference to figure 1 and Fig. 2, comprise substrate 110 and be installed in the semiconductor chip 120 on the substrate 110 according to the semiconductor package part 100 of the embodiment of the invention.In addition, the semiconductor package part 100 according to the embodiment of the invention also comprises adhering part 140, enclose components 150 and outside installing component 160.
Substrate 110 can be the shape of rectangular hexahedron for example, and have each other back to upper surface 111a and lower surface 111b.Substrate 110 comprises groove 112, engage and to refer to 116 and ball pad 118; Groove 112 is limited on the upper surface 111a; Joint refers to that 116 are arranged on that upper surface 111a goes up and expose via groove 112, and ball pad 118 is arranged on lower surface 111b and goes up and be electrically connected to each joint and refer to 116.As shown in Figure 1, joint refers to that 116 can be arranged on the basal surface of groove 112.Alternately, although do not show in the accompanying drawings, joint refers to that 116 can be arranged on the sidewall surfaces of groove 112.
The application's accompanying drawing shows the groove (for example, 112 among Fig. 1) of rectangular cross-sectional shape, and the end (or sidewall) the lip-deep joint that the groove (for example, 112 among Fig. 1) that is arranged on rectangular cross-sectional shape is shown refers to (for example, 116 among Fig. 1).Yet according to example of the present invention, the engagement arrangement mode of the shape of cross section of other geometry and various ways also is feasible.For example, groove 112 as shown in Figure 1 can have the opening trapezoidal cross sectional shape that has inclined surface, refers to that 116 can be arranged on the inclined surface of groove 112 and engage.
Semiconductor chip 120 has a surperficial 121a towards the upper surface 111a of substrate 110, and back to another surperficial 121b of surperficial 121a.In addition, semiconductor chip 120 comprises the bond pad 122 that is arranged on the surperficial 121a and is formed on the projection 124 on the bond pad 122.Projection 124 can comprise multiple electric conducting material, for example solder projection or principal column projection.Because semiconductor chip 120 makes thinly, so semiconductor chip 120 has the structure that the marginal portion of semiconductor chip 120 is bent upwards, just, and with the structure of the curved shape of smiling.Curved surface 121a and outside sweep surface 121b in the surperficial 121a of semiconductor chip 120,121b also can be referred to as.Crooked semiconductor chip 120 is installed to the upper surface 111a of substrate 110 with prone mode, so that interior curved surface 121a is towards the upper surface 111a of substrate 110.
Then, the curved edge of semiconductor chip 120 partly is inserted in the groove 112 of substrate 110, and the joint that the bond pad 122 of semiconductor chip 120 is electrically connected in the corresponding groove 112 refers to 116.Bond pad 122 for example is arranged on the curved edge part of semiconductor chip 120, and it is inserted in the groove 112 of substrate 110.As shown in Figure 1, the joint of bond pad of semiconductor chip 120 122 and substrate 110 refers to that 116 are electrically connected to each other through the projection 124 that is formed on the bond pad 122.
Refer to that 116 realize being connected through projection 124 although Fig. 1 illustrates bond pad 122 and joint, bond pad 122 refers to that with engaging 116 can be electrically connected to each other through a lot of different modes.For example, although accompanying drawing does not illustrate, the bond pad 122 of semiconductor chip 120 refers to that with the joint of substrate 110 116 can realize being electrically connected to each other through directly contacting each other, and need not use independent link.
Equally, although accompanying drawing does not illustrate, the joint of bond pad of semiconductor chip 120 122 and substrate 110 refers to that 116 can be through projection but be electrically connected to each other through the conductive paste that is filled in the groove 112.Just; The curved edge part that is provided with the semiconductor chip 120 of bond pad 122 above that can be inserted in the groove 112 of substrate 110; And wherein do not have projection to be formed on the bond pad 122, and the joint of the bond pad 122 of semiconductor chip 120 and substrate 110 refers to that 116 can be electrically connected to each other through the conductive paste in the groove 112.
According to embodiments of the invention; Groove 112 is limited on the part of upper surface 111a of the substrate 110 corresponding with two marginal portions of semiconductor chip 120; And same, its curved edge part that is provided with the semiconductor chip 120 of bond pad 122 can be inserted in the corresponding groove 112.
Adhering part 140 is applied between the interior curved surface 121a of upper surface 111a and semiconductor chip 120 of substrate 110.Adhering part 140 is used for making semiconductor chip 120 attach to substrate top surface 111a securely through providing solid-state physics to attach.Adhering part 140 also is used to avoid the semiconductor chip 120 of bending further crooked.
Enclose components 150 forms the upper surface 110a that covers semiconductor chip 120 and substrate 110.Enclose components 150 can comprise for example epoxy molding plastic (EMC).
Outside installing component 160 is attached on the ball pad 118 that is arranged on the substrate lower surface 111b.Outside installing component 160 can comprise for example soldered ball.
Usually, have the semiconductor chip that reduces thickness, 120 among Fig. 1 for example is with arc-shaped cross-section profile (shape of for example smiling) bending.As stated; Towards substrate top surface 111a the semiconductor chip 120 of bending is mounted to substrate top surface 111a through curved surface 121a in making; And partly be inserted in the groove 112 that is limited on the substrate top surface 111a through the curved edge with semiconductor chip 120, overcome with chip and attached to a difficult problem relevant on the substrate securely bending.
In other words; In an embodiment of the present invention; The interior curved surface 121a of crooked semiconductor chip 120 attaches on the substrate 110 through the media of adhering part 140, and the curved edge of semiconductor chip 120 part (bond pad 122 is formed on the interior curved surface 121a) is inserted in the groove 112 that is formed on the substrate top surface 111a.Therefore, be fixed in the groove 112 on the substrate top surface 111a, can cause not substrate 110 bendings dorsad of marginal portion of semiconductor chip 120, thereby the installation reliability of semiconductor package part 100 be improved through making the marginal portion.
Fig. 3 illustrates the sectional view of semiconductor package part 300 in accordance with another embodiment of the present invention, and Fig. 4 is the sectional view that semiconductor chip shown in Figure 3 320 is shown.About Fig. 3 and Fig. 4, it has and characteristic like the feature class shown in Fig. 1-2 mentioned above, and therefore similarly characteristic no longer is repeated in this description.
According to embodiments of the invention as shown in Figure 3, groove 312 is formed on the part of upper surface 311a of substrate 310 in the semiconductor package part 300.Groove 312 forms the wherein marginal portion of holding semiconductor chip 320.In the embodiment shown in Fig. 1-2, two marginal portions of crooked semiconductor chip 120 are contained in the row of two on the substrate top surface 111a that is formed on substrate 110 groove 112.Yet in the embodiments of the invention shown in Fig. 3-4, semiconductor chip 320 has only a marginal portion to be formed with the bond pad 322 on the interior curved surface 321a of semiconductor chip 320, and this marginal portion is inserted in the groove 312.
According to the embodiments of the invention shown in Fig. 3-4, semiconductor chip 320 is formed with bond pad 322, and bond pad 322 is formed on the mid portion of interior curved surface 321a of semiconductor chip 320.As shown in Figure 4, in redistribution lines 326 is formed on the curved surface 321a, and each redistribution lines 326 is connected to projection 324 with a bond pad 322, and projection 324 is formed on the inner surface 321a of edge part office of crooked semiconductor chip 320.Dielectric layer 328 forms the redistribution lines 326 on the covering surfaces 321a, and exposes projection 324 in the edge part office of semiconductor chip 320.
Marginal portion (end of redistribution lines 326 is set) through with the semiconductor chip 320 of bending is inserted in the groove 312, so semiconductor chip 320 is electrically connected to substrate 310.Therefore the end of the redistribution lines 326 of the edge part office of semiconductor chip 320 also is inserted in the groove 312, and with the bottom surface that is formed on groove 312 on engage and refer to that 316 are coupled.
Yet; In Fig. 3-4; Bond pad is formed on the edge part office and the pars intermedia office of semiconductor chip 320, and semiconductor chip 320 can be " a monolateral chip ", and wherein 322 of bond pads are formed on an edge part office and on the inner surface 321a of semiconductor chip 320.
In addition, according to embodiments of the invention, redistribution lines 326 also can extend to any other marginal portion except shown in Fig. 3-4.For example, feasible and within scope of the present invention, redistribution lines 326 can extend to another marginal portion of the semiconductor chip 320 on the opposite side that is positioned at marginal portion shown in Fig. 3.In this case, 320 of semiconductor chips can be installed in such a way, and promptly groove is limited at the position of the opposite side of present groove 312 shown in Figure 3 in the substrate 310.The end that extends to the redistribution lines 326 of the marginal portion on the opposite side of marginal portion as shown in Figure 3 from the mid portion of semiconductor chip 320 can be inserted into the respective slot on the opposite side that is formed on present groove as shown in Figure 3 312.
The bond pad 322 of semiconductor chip 320 and the joint of substrate 310 refer to that 312 can be electrically connected to each other through the projection 324 that is formed on the edge part office on the redistribution lines 326.In Fig. 3-4, according to embodiments of the invention, bond pad 322 is illustrated in the mid portion of semiconductor chip 320; Yet scope of the present invention is not limited thereto.Bond pad 322 can form other position except the mid portion shown in Fig. 3-4, and it possibly be more suitable for the layout of redistribution lines 326.
Further, according to embodiments of the invention, can be so that the joint of the bond pad 322 of semiconductor chip 320 and substrate 320 refer to that 316 can be electrically connected to each other through directly contacting, and the link in the middle of not needing.In addition,, also can use the conductive paste that is filled in the groove 312 to replace projection 324, refer to 316 with the bond pad 322 of electrical connection semiconductor chip 320 and the joint of substrate 310 according to embodiments of the invention.
According to embodiments of the invention; Crooked semiconductor chip 320 is mounted to the substrate 310 with groove 312; And interior curved surface 321a is towards the upper surface 311a of substrate 310; Make the marginal portion according to the semiconductor chip that wherein is formed with projection 324 320 of the embodiment of the invention be inserted in the groove 312 on the upper surface 311a that is formed on substrate 310, thereby improved the installation reliability of semiconductor package part 300.
Fig. 5-the 6th illustrates the sectional view according to the different modification of the semiconductor package part of the embodiment of the invention.
With reference to figure 5, comprise on the substrate 510 one or more multiple semiconductor chip 520 and one or more multiple semiconductor chip 530 according to the stacked type semiconductor package part 500 of the embodiment of the invention.Semiconductor package part 500 comprises adhering part 540 and 542, enclose components 550 and outside installing component 560.
Joint refers to for example 516 and 517 can be arranged on the surface of groove 512 and 513, and is for example on the bottom surface, as shown in Figure 5.Therefore, for example, according to embodiments of the invention, joint refers to that 516 and 517 also can be formed on the sidewall surfaces of groove 512 and 513.
Although groove shown in Figure 5 512 and 513 has rectangular cross-sectional shape, scope of the present invention is not limited thereto, and other shape also is feasible.For example, as shown in Figure 6, groove 612 and 613 can form has trapezoidal cross sectional shape.Have the groove 612 of trapezoidal cross sectional shape and the surface that 613 side surface has inclination; Refer to that 616 and 617 can be formed on any surface with the surperficial groove 612 of sloped sidewall and 613 and engage; As shown in Figure 6, so that it exposes via groove 612 and 613.
Refer back to Fig. 5 again, semiconductor chip 520 has towards the interior curved surface 521a of the upper surface 511a of substrate 510 and the outside sweep surface 521b of opposite side that is positioned at the curved surface 521a of semiconductor chip 520.Semiconductor chip 520 comprises the bond pad 522 on two marginal portions that are formed on interior curved surface 521a, and is formed on the projection 524 on the bond pad 522.Projection 524 can be for example solder projection or principal column projection.When semiconductor chip 520 was made thinly, semiconductor chip 520 maybe be with the curved shape of similar smile, and was as shown in Figure 5.
Two marginal portions of semiconductor chip 520 all are inserted in two row's grooves 512 of substrate 510, and the joint of the bond pad 522 of semiconductor chip 520 and substrate 510 refers to that 516 projections 524 through formation on the bond pad in groove 512 522 are electrically connected to each other.
Therefore; Groove 512 (for example; Fig. 5 illustrates two row's grooves 512; Insert in two row's grooves 512 two marginal portions of chip 520) form two marginal portions that correspond respectively to semiconductor chip 520, and semiconductor chip 520 is mounted to and makes its two marginal portions be inserted into respectively in the groove 512.
Fig. 5 illustrates the semiconductor chip 520 that is installed on the substrate 510, and two marginal portions of semiconductor chip 520 are inserted in the groove 512 of substrate 510.Yet, according to embodiments of the invention, should be understood that easily that semiconductor chip 520 can be monolateral pad type chip, make semiconductor chip 520 have only a marginal portion to be inserted in the groove 512 of substrate 510, to be installed on the substrate 510.In this case, the semiconductor chip 520 of a monolateral pad type for example marginal portion is provided with bond pad, or has the center bonding pads cake core of redistribution lines.
One (with semiconductor chip 520) of the semiconductor chip 530 that Fig. 6 also illustrates has towards the interior curved surface 531a of the outside sweep surface 521b of semiconductor chip 520.Each semiconductor chip 530 has back to the outside sweep surface 531b of interior curved surface 531a.A semiconductor chip 530 is installed on the outside sweep surface 521b of semiconductor chip 520.As shown in Figure 5, additional semiconductor chip 530 forms and makes each chip 530 be formed on the outside sweep surface 531 of another semiconductor chip 530.As shown in Figure 5, because semiconductor chip 520 and 530 is made thin, so they bend to the shape of similar smile.Bond pad 532 only is formed on the semiconductor chip 530 along a marginal portion of each semiconductor chip 530 with additional projection 534.Each semiconductor chip 530 is mounted to and makes to have only a marginal portion that is formed with bond pad 532 and additional bump 534 on it to insert in the groove 513, and groove 513 is limited on the upper surface 511a of substrate 510.
Each semiconductor chip 530 can be monolateral pad type chip, and wherein 532 of bond pads are formed on the marginal portion, perhaps can be the center bonding pads cake core with redistribution lines.
Adhering part 540 is inserted between the outside sweep surface 521a of upper surface 511a and semiconductor chip 520 of substrate 510.Adhering part 540 is used for the upper surface 511a of semiconductor chip 520 physical fixation that are inserted into two row's grooves 512 to substrate 510, thereby has overcome the physical characteristic of crooked semiconductor chip 520.Adhering part 540 also prevents semiconductor chip 520 further flexural deformation owing to bending.
Adhering part 542 is inserted in semiconductor chip 520 and between the semiconductor chip 530 near the outside sweep surface 521b of semiconductor chip 520, and between the interior curved surface 531a of the outside sweep surface 531b of a semiconductor chip 530 and another semiconductor chip 530.Additional adhering part 542 is physically fixed to one another with semiconductor chip 520 and nethermost semiconductor chip 530, and other semiconductor chip 530 that will be inserted in the groove 513 is fixed to one another.
Enclose components 550 forms the upper surface 511a of encapsulation of semiconductor chip 520,530 and substrate 510.Enclose components 550 can comprise for example epoxy molding plastic (EMC).
Outside installing component 560 attaches to the ball pad 518 on the lower surface 511b that is arranged on substrate 510.Outside installing component 560 can comprise for example soldered ball.
In the stacked type semiconductor package part of embodiment according to the present invention as described hereinbefore; (just, the interior curved surface shown in Fig. 1-6 is 121a for example, 321a with prone mode for crooked semiconductor chip; 521a; 531a is installed as each upper surface towards corresponding substrate) be installed on the substrate, to avoid semiconductor chip each substrate crooked (for example, the upper surface 111a from substrate 110 like Fig. 1 is bent upwards) dorsad.Just; According to embodiments of the invention; Thin but crooked semiconductor chip is installed in prone mode on the substrate with groove, and it can make the small semiconductor packaging part realize the installation reliability of high integration and raising as stated and shown in Fig. 1-6.
Fig. 7 is the sectional view that illustrates according to another modification of the semiconductor package part of the embodiment of the invention.About Fig. 7, with shown in Fig. 1-6 and with reference to the no longer repetition hereinafter of the described similar characteristics of figure 1-6.
With reference to figure 7, stacked type semiconductor package part 700 comprises substrate 710 and is installed to a semiconductor chip 720 and or the more additional semiconductor chips 730 on the substrate 710.In addition, stacked type semiconductor package part 700 further comprises adhering part 742, enclose components 750 and outside installing component 760.
Particularly, in the semiconductor package part 700 according to the embodiment of the invention as shown in Figure 7, comprise semiconductor chip 720, it does not have bending, unlike Fig. 1,3 and 5-6 shown in semiconductor chip.Semiconductor chip 720 comprise be formed on two on the marginal portion bond pad 722 and be formed on the projection 724 on the bond pad 722.
Therefore; The bond pad 722 of semiconductor chip 720 and the joint of substrate 710 refer to that 716 are electrically connected to each other through projection 724, and the joint in the groove 713 of the bond pad 732 of crooked semiconductor chip 730 and substrate 710 refers to that 717 are electrically connected to each other through the projection 734 that is formed on the bond pad 732.According to embodiment as shown in Figure 7, joint refers to that 717 are formed on the basal surface of groove 713, but should be understood that easily to engage refers to be formed on other surface, for example on the sidewall surfaces of groove 713.
The bond pad 722 of semiconductor chip 720 and the joint of substrate 710 refer to that 716 are electrically connected to each other through the projection 724 that is formed on the bond pad 722, and the joint of the bond pad 732 of crooked semiconductor chip 730 and substrate 710 refers to that 717 are electrically connected to each other through the projection 734 that is formed on the bond pad 732.The bond pad 722 of semiconductor chip 720 refers to that with the joint of substrate 710 716 can not need independent link to be electrically connected to each other through directly contacting, and the additional bond pad 732 of crooked semiconductor chip 730 and the joint of substrate 710 refer to that 717 can not need independent link to be electrically connected to each other through directly contacting.In addition, the joint of the bond pad 732 of crooked semiconductor chip 730 and substrate 710 refers to that 717 can be electrically connected to each other through the conductive paste that is filled in the further groove 717.
With reference now to Fig. 8,, it should be noted that also all semiconductor chips 830 can be monolateral pad type chips, so that semiconductor chip 830 has only a marginal portion to be inserted in the groove 813 of substrate 810 to be installed on the substrate 810.In this case, monolateral pad type semiconductor chip 830 can for example have the bond pad that only on a marginal portion, is provided with, or has the center bonding pads cake core of redistribution lines.
The chip that should be understood that different length easily can encapsulate according to embodiments of the invention.
Although described a plurality of embodiment of the present invention for purposes of illustration; But those skilled in the art can be understood that; Under the situation that does not deviate from disclosed scope of the present invention of accompanying claims and spirit, be feasible to multiple modification of the present invention, additional and replacement.
The cross reference of related application
The application requires the priority of korean patent application No.10-2010-0100740 that submitted on October 15th, 2010 and the korean patent application No.10-2011-0096144 that submitted to September 23, quotes it in full in this combination.
Claims (23)
1. semiconductor package part comprises:
Substrate comprises first groove on the upper surface that is formed on this substrate; And
The first crooked semiconductor chip comprises first marginal portion, and this first marginal portion is inserted in this first groove on this upper surface that is formed on this substrate.
2. semiconductor package part as claimed in claim 1,
Wherein this first crooked semiconductor chip comprises second marginal portion, and this second marginal portion is inserted in second groove on this upper surface that is formed on this substrate; And
Wherein this first crooked semiconductor chip is installed as and makes this first marginal portion of this first crooked semiconductor chip and this second marginal portion be inserted into respectively in this first groove and this second groove.
3. semiconductor package part as claimed in claim 2 further comprises:
Adhering part is between this upper surface and this first crooked semiconductor chip of this substrate.
4. semiconductor package part as claimed in claim 2,
Wherein this substrate comprises that being formed on each lip-deep joint of this first groove and this second groove refers to.
5. semiconductor package part as claimed in claim 4,
Wherein this first crooked semiconductor chip comprises bond pad, and this bond pad is formed on each of this first marginal portion and this second marginal portion, is formed on each lip-deep joint of this first groove and this second groove with electrical connection and refers to.
6. semiconductor package part as claimed in claim 5, wherein this first crooked semiconductor chip further comprises the projection on each that is formed on this bond pad.
7. semiconductor package part as claimed in claim 4, one of them or more groove shaped become rectangular cross-sectional shape, and this joint in each groove refers to be formed on the basal surface or side surface of this groove.
8. semiconductor package part as claimed in claim 4, one of them or more groove shaped become trapezoidal cross sectional shape, and this joint in each groove refers to be formed on the basal surface or side surface of this groove.
9. semiconductor package part as claimed in claim 2 further comprises the second crooked semiconductor chip, and this second crooked semiconductor chip comprises the 3rd marginal portion, and the 3rd marginal portion is inserted in the 3rd groove on this upper surface that is formed on this substrate.
10. semiconductor package part as claimed in claim 9 further comprises:
Adhering part is between this first crooked semiconductor chip and this second crooked semiconductor chip.
11. semiconductor package part as claimed in claim 10, wherein this second crooked semiconductor chip comprises the engaged at end pad that is formed on the 3rd marginal portion.
12. semiconductor package part as claimed in claim 11, wherein this second crooked semiconductor chip comprises:
Intermediate bond pad is formed on the mid portion on surface of this second crooked semiconductor chip; And
Redistribution lines is formed on this surface of this second crooked semiconductor chip, to be electrically connected this intermediate bond pad and this engaged at end pad.
13. semiconductor package part as claimed in claim 12, wherein this substrate comprises that the lip-deep joint that is formed on the 3rd groove refers to, is formed on the engaged at end pad on the 3rd marginal portion of this second crooked semiconductor chip with electrical connection.
14. semiconductor package part as claimed in claim 13, wherein this second semiconductor chip further comprises the projection that is formed on this engaged at end pad.
15. semiconductor package part as claimed in claim 13, wherein the 3rd groove shaped becomes rectangular cross-sectional shape, and this joint in the 3rd groove refers to be formed on the basal surface or side surface of the 3rd groove.
16. semiconductor package part as claimed in claim 13, wherein the 3rd groove shaped becomes trapezoidal cross sectional shape, and the joint in the 3rd groove refers to be formed on the basal surface or side surface of the 3rd groove.
17. semiconductor package part as claimed in claim 12, wherein this second crooked semiconductor chip also comprises:
Projection is formed on the end of this redistribution lines corresponding with the 3rd marginal portion of this second crooked semiconductor chip.
18. semiconductor package part as claimed in claim 17, wherein this redistribution lines is covered by protective material, but exposes this projection.
19. semiconductor package part as claimed in claim 1 further comprises:
Enclose components covers this upper surface of this first crooked semiconductor chip and this substrate; And
Outside installing component attaches to the lower surface of this substrate.
20. semiconductor package part as claimed in claim 19, wherein this first crooked semiconductor chip comprises:
Intermediate bond pad is formed on the mid portion on surface of this first crooked semiconductor chip;
Redistribution lines is formed on this surface of this first crooked semiconductor chip, with this intermediate bond pad and first bond pad that is electrically connected this first crooked semiconductor chip.
21. semiconductor package part as claimed in claim 20 further comprises the 4th crooked semiconductor chip, the 4th crooked semiconductor chip comprises first marginal portion, and this first marginal portion is inserted in the 4th groove on this upper surface that is formed on this substrate.
22. semiconductor package part as claimed in claim 21, wherein adhering part is between this first crooked semiconductor chip and the 4th crooked semiconductor chip.
23. semiconductor package part as claimed in claim 19; Further comprise the 5th non-crooked semiconductor chip that is formed on below this first crooked semiconductor chip, wherein adhering part is between this first crooked semiconductor chip and the 5th non-crooked semiconductor chip.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2010-0100740 | 2010-10-15 | ||
| KR20100100740 | 2010-10-15 | ||
| KR10-2011-0096144 | 2011-09-23 | ||
| KR1020110096144A KR20120039464A (en) | 2010-10-15 | 2011-09-23 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102569217A true CN102569217A (en) | 2012-07-11 |
| CN102569217B CN102569217B (en) | 2015-10-07 |
Family
ID=46139835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110458334.XA Expired - Fee Related CN102569217B (en) | 2010-10-15 | 2011-10-14 | Semiconductor package part |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR20120039464A (en) |
| CN (1) | CN102569217B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102033787B1 (en) | 2013-06-05 | 2019-10-17 | 에스케이하이닉스 주식회사 | Flexible stack package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5814885A (en) * | 1997-04-28 | 1998-09-29 | International Business Machines Corporation | Very dense integrated circuit package |
| CN101221945A (en) * | 2007-01-09 | 2008-07-16 | 力成科技股份有限公司 | Packaging body capable of repeatedly stacking |
| US20080251944A1 (en) * | 2006-10-03 | 2008-10-16 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
| CN101755336A (en) * | 2007-07-24 | 2010-06-23 | 美光科技公司 | Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods |
-
2011
- 2011-09-23 KR KR1020110096144A patent/KR20120039464A/en not_active Application Discontinuation
- 2011-10-14 CN CN201110458334.XA patent/CN102569217B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5814885A (en) * | 1997-04-28 | 1998-09-29 | International Business Machines Corporation | Very dense integrated circuit package |
| US20080251944A1 (en) * | 2006-10-03 | 2008-10-16 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
| CN101221945A (en) * | 2007-01-09 | 2008-07-16 | 力成科技股份有限公司 | Packaging body capable of repeatedly stacking |
| CN101755336A (en) * | 2007-07-24 | 2010-06-23 | 美光科技公司 | Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20120039464A (en) | 2012-04-25 |
| CN102569217B (en) | 2015-10-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4498403B2 (en) | Semiconductor device and semiconductor memory device | |
| US7723839B2 (en) | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device | |
| US7170183B1 (en) | Wafer level stacked package | |
| US8089141B1 (en) | Semiconductor package having leadframe with exposed anchor pads | |
| JP4489100B2 (en) | Semiconductor package | |
| US7105919B2 (en) | Semiconductor package having ultra-thin thickness and method of manufacturing the same | |
| US20080316696A1 (en) | Semiconductor memory device and semiconductor memory card using the same | |
| JP4845600B2 (en) | Stacked package | |
| US20080176358A1 (en) | Fabrication method of multichip stacking structure | |
| KR101544508B1 (en) | Semiconductor package and printed circuit board having bond finger | |
| JPH10200013A (en) | Ball grid array semiconductor package and manufacture thereof | |
| US20130093072A1 (en) | Leadframe pad design with enhanced robustness to die crack failure | |
| JP4602223B2 (en) | Semiconductor device and semiconductor package using the same | |
| CN102569217A (en) | Semiconductor package | |
| US20070090507A1 (en) | Multi-chip package structure | |
| US8519522B2 (en) | Semiconductor package | |
| JP2010087403A (en) | Semiconductor device | |
| JP4181557B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4489094B2 (en) | Semiconductor package | |
| KR100668848B1 (en) | Chip stack package | |
| JP2014120501A (en) | Semiconductor device and method for manufacturing the same | |
| US11469188B2 (en) | Semiconductor package | |
| JP5048627B2 (en) | Lead frame and semiconductor device | |
| KR20060133800A (en) | Chip stack package | |
| KR101116731B1 (en) | Dual die package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151007 Termination date: 20161014 |