CN102569214B - 三维***级封装堆栈式封装结构 - Google Patents

三维***级封装堆栈式封装结构 Download PDF

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CN102569214B
CN102569214B CN201110029409.2A CN201110029409A CN102569214B CN 102569214 B CN102569214 B CN 102569214B CN 201110029409 A CN201110029409 A CN 201110029409A CN 102569214 B CN102569214 B CN 102569214B
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package
crystal grain
signaling channel
supporting component
building brick
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CN102569214A (zh
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林南君
郑雅云
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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ADL Engineering Inc
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Abstract

本发明提供一种三维***级封装堆栈式封装结构，包含：一支撑组件形成并包围第一电子组件。一填充材料填入于第一电子组件及支撑组件之间。信号信道耦接第一电子组件的第一晶粒焊垫。导体组件形成于信号信道的第一端与第二电子组件的第二晶粒焊垫之间以信号连接。本发明的三维***级封装堆栈式封装结构，降低封装厚度与面积，并克服封装问题，可提供较佳板级热循环可靠度测试。

Description

三维***级封装堆栈式封装结构
技术领域
本发明涉及一种封装结构，特别是一种三维***级封装堆栈式封装结构。
背景技术
半导体组件的领域中，组件密度持续地提升以及组件尺寸不断地降低。也因此对于如此高密度的封装技术及内联机技术也提升以适用上述的状态。传统的覆晶结构中，锡球数组形成于晶粒的表面，通过传统锡膏借由锡球罩幕制作以形成所欲之图案。芯片封装功能包含散热、信号传输、电源分配、保护等，当芯片更加复杂，传统的封装如导线架封装、软式封装、刚性封装技术无法满足高密度小尺寸芯片的需求。
再者，半导体组件需要保护以避免水分与机械损坏。此结构及涉及封装的技术。在这些技术中，半导体晶粒或芯片通常分别封装于弹性或陶瓷封装中。此封装需要保护晶粒并且散开由组件产生的热。因此，散热在半导体组件中是非常重要的，尤其是对于组件的功率及效能的提升。
由于一般封装技术必须先将晶圆上的晶粒分割为个别晶粒，再将晶粒分别封装，因此上述技术的制程十分费时。因为晶粒封装技术与集成电路的发展有密切关联，因此封装技术对于电子组件的尺寸要求越来越高。基于上述理由，现今的封装技术已逐渐趋向采用球门阵列封装(BGA)、覆晶球门阵列封装、芯片尺寸封装、晶圆级封装的技术。应可理解「晶圆级封装(WLP)」指晶圆上所有封装及交互连接结构，如同其它制程步骤，是于切割为个别晶粒之前进行。一般而言，在完成所有配装制程或封装制程之后，由具有多个半导体晶粒的晶圆中将个别半导体封装分离。上述晶圆级封装具有极小的尺寸及良好的电性。
晶圆级封装技术为高级封装技术，借其晶粒是于晶圆上加以制造及测试，且接着借切割而分离以用于在表面黏着生产线中组装。因晶圆级封装技术利用整个晶圆作为目标，而非利用单一芯片或晶粒，因此于进行分离程序之前，封装及测试皆已完成。此外，晶圆级封装是如此之高级技术，因此打线接合、晶粒黏着及底部填充的程序可予以省略。利用晶圆级封装技术，可减少成本及制造时间且晶圆级封装的最后结构尺寸可相当于晶粒大小，故此技术可满足电子装置的微型化需求。
虽晶圆级封装技术具有上述优点，然而仍存在一些影响晶圆级封装技术接受度的问题。例如，虽利用晶圆级封装技术可减少集成电路与互连基板间的热膨胀系数(CTE)不匹配，然而当组件尺寸缩小，晶圆级封装结构的材料间的热膨胀系数差异变为另一造成结构的机械不稳定的关键因素。再者，形成于半导体晶粒上的数个接合垫是通过包含重分布层(RDL)的重分布制程予以重分布进入数个区域数组形式的金属垫。一般而言，所有经堆栈的重分布层形成于晶粒上的增层上。增层将增加封装大小。封装厚度因此增加。其可能与缩小芯片尺寸的需求相抵触。
集成电路及集成电路封装***可以发现于许多电子组件中，例如移动电话、掌上计算机、数码相机与其它可携式产品。客户及电子***需要这些集成电路***于最小的组件封装、最低的外观及成本最低的封装之下，提供最大的内存及逻辑的功能整合。结果，提供三维封装以得到需要高阶功能整合以支持这些移动电子产品。
不同技术已发展以符合持续需求以提升三维封装内的功能整合及电路密度。不佳的是，导线架基三维封装于处理高阶功能整合***的递增电路密度的需求显得其能力是不足的。一般而言，导线架封装由于一些因素而具有其限制性，例如封装厚度增加、较大的封装面积及不足的输入/输出引线以处理较高的电路密度。
发明内容
为了解决上述技术问题，本发明提出一种新颖的堆栈封装结构以降低封装厚度与面积，并克服上述封装问题以及提供较佳板级热循环可靠度测试。
本发明提供一种三维***级封装堆栈式封装结构，包含至少一第一电子组件，具有第一晶粒焊垫。一支撑组件形成以围绕至少一第一电子组件。一填充材料填入于至少一第一电子组件与支撑组件之间。一介电层形成于至少一第一电子组件、支撑组件与填充材料之上以暴露第一晶粒焊垫。信号信道形成于介电层之上，并耦接第一晶粒焊垫。一第一保护层形成于信号信道之上以暴露信号信道之第一端。导体组件形成于信号信道的第一端之上。一第二电子组件，具有第二晶粒焊垫耦接导体组件。一第二保护层，形成于第二电子组件之下以暴露第二电子组件的第二晶粒焊垫。
根据本发明的一观点，三维***级封装堆栈式封装结构还包含一基底，具有终端垫形成于其上，以及一黏着层形成于基底之上与至少一第一电子组件、支撑组件及填充材料之下。一焊垫形成于信号信道的第二端之上，其中焊垫通过焊线而电性连接至终端垫。一成型材料以用于封装第一电子组件、第二电子组件及基底上的焊垫。第二导体组件形成于基底之下。
根据本发明的另一观点，三维***级封装堆栈式封装结构还包含焊接球垫形成于信号信道的第二端之上，其中焊接球垫电性连接焊接球；一晶粒黏合材料形成于第一电子组件之下。一第三保护层，形成于该晶粒黏合材料、该支撑组件及该填充材料之下。
根据本发明的又一观点，三维***级封装堆栈式封装结构更包含一第二介电层，形成于第一电子组件、支撑组件的第一部分及填充材料之下。一第三保护层形成于第二介电层之下。背部信号信道，形成于第二介电层之下以用于连接至支撑组件的第二部分。焊接球形成于第三保护层及背部信号信道之下，以连接至背部信号信道。一连接层，形成于第一晶粒焊垫及支撑组件的第二部分之上，与信号信道之下。
支撑组件的第二部分的底部表面与第二介电层的下表面为共平面。
上述的三维***级封装堆栈式封装结构，还包含第二信号信道，形成于所述第二电子组件之下，并耦接所述第二晶粒焊垫与所述导电组件之间。
本发明能够达到以下技术效果：
支撑组件预设晶粒接收穿孔；而由于晶粒嵌入支撑组件内部，因此得以产生超薄封装；借由填入硅橡胶作为缓冲区域以吸收硅晶粒及支撑组件间的热膨胀系数(CTE～2.3)不匹配所产生热应力；由于应用简单的制程使得封装产能得以提升(制作时间缩短)。封装及板级的可靠度较传统佳，不会导致热机械应力施加于焊接凸块/球。成本低廉且制程简易。制程可以完全地自动，尤其于模块组装中。易制作多芯片封装(双芯片封装)。由于无粒子污染、制程简易及完全自动化，可以得到较高的良率。
附图说明
图1是本发明第一实施例的基础三维***级封装堆栈式封装结构的截面图。
图2是本发明一实施例的具有焊线及信号信道的三维***级封装堆栈式封装结构的截面图。
图3是本发明一实施例的具有并排的信号信道的三维***级封装堆栈式封装结构的截面图。
图4是本发明一实施例的具有朝上信号信道的三维***级封装堆栈式封装结构的截面图。
图5是本发明一实施例的具有背部信号信道的三维***级封装堆栈式封装结构的截面图。
附图标号说明：
第一晶粒100、100a、100b
第一焊垫101
支撑组件102
第一部分支撑组件102a
第二部分支撑组件102b
填充材料103
连接层104
介电(缓冲)层105
信号信道106、106a、106b
保护层107
第二晶粒108
第二晶粒焊垫109
保护层110
导电组件111
基底120
终端垫121
导电组件122
封装黏合材料123
焊垫124
焊线125
成型材料126
保护层140
焊接凸块/球垫141
焊接凸块/球142
晶粒黏合材料143
连接层151
背部信号信道152
介电层153
保护层154
焊接凸块/球155
具体实施方式
本发明将配合其较佳实施例与附图详述于下。应可理解者为本发明中所有的较佳实施例仅为例示之用，并非用以限制。因此除文中的较佳实施例外，本发明亦可广泛地应用在其它实施例中。且本发明的保护范围并不受限于任何实施例，应以权利要求及其同等领域而定。
本发明提出一种新颖的三维***级封装堆栈式封装结构以降低封装厚度与面积，并提供较佳板级热循环可靠度测试。
图1显示根据本发明一实施例的基础三维***级封装堆栈式封装结构的截面图。如图1所示，三维***级封装堆栈式封装结构包含一第一封装电子构件及第二电子组件，其中第一封装电子构件通过导电组件耦接第二电子组件。第二电子组件(称为上封装)位于第一封装电子构件之上(称为底部封装)，其中第一封装电子构件的主动区域相对于第二电子组件的主动区域。第一封装电子构件包含一支撑组件102、一填充材料103、一第一晶粒100、一介电(缓冲)层105、一连接层104、信号信道106与一保护层107。支撑组件102具有预定的晶粒穿孔及多个开口穿过支撑组件，其中晶粒穿孔得以让第一晶粒100形成于其中。第一晶粒100具有第一焊垫101形成于其上以利于信号连接(电性沟通)。在一实施例中，支撑组件102包含导电材料。支撑组件102的材料包含合金或金属。支撑组件102形成以围绕第一晶粒100，其中第一晶粒100为一电子(半导体)组件。多个晶粒穿孔及开口形成以穿透支撑组件102，从其上表面至下表面。填充材料103填入第一晶粒100及支撑组件102之间的空间(多个开口)，并围绕第一晶粒100。举例而言，填充材料103围绕第一晶粒100及支撑组件102。在一实施例中，填充材料103、第一晶粒100及支撑组件102的底部及上部表面是共平面。介电(缓冲)层105形成于第一晶粒100、支撑组件102及填充材料103之上，并借由微影制程及蚀刻制程以产生多个第二开口以暴露第一晶粒100的第一焊垫101。在一实施例中，介电(缓冲)层105包括弹性材料或感光材料。连接层104形成位于第二开口的第一晶粒100的第一焊垫101之上，并连接第一焊垫101。在一实施例中，连接层104包括导电材料。信号信道106，例如重分布层(redistribution layer)，形成(回流)于介电(缓冲)层105及连接层104之(上表面)上，而连接至连接层104。因此，连接层104连接信号信道106及第一晶粒焊垫101之间。在一实施例中，信号信道106及连接层104可以借由同一制程而同时形成。在另一实施例中，多重信号信道层可以应用于本发明中，形成于介电(缓冲)层105及连接层104之上。保护层107形成于信号信道106之上以保护及覆盖信号信道106与介电(缓冲)层105以形成多个第三开口以暴露信号信道106的第一端。第二晶粒108位于第一晶粒100之上。举例而言，第一晶粒100及第二晶粒108是半导体组件。另一保护层110形成于第二晶粒108之下用以保护，并形成多个第四开口以暴露第二晶粒108的第二晶粒焊垫109。第二晶粒108的主动侧面朝下。在一实施例中，保护层107、110的材料包含硅氧烷聚合物(SINR)、硅橡胶，且保护层可以利用铸模或胶合法(涂布或网印)所形成。基于产品的考虑，另一个信号信道(图中未示出)，例如重分布层，可以选择性地保护层110之(上表面)上及第二晶粒108之下，而耦接于第二晶粒焊垫109及导电组件111之间。导电组件111，例如焊接凸块/球，形成位于第三开口的信号信道106的第一端之上及位于第四开口的第二晶粒焊垫109之下，以利于信号连接，而连接第二晶粒108的第二晶粒焊垫109及信号信道106的第一端。结果，第一晶粒100通过导电组件111而耦接第二晶粒108以形成一三维集成电路封装结构。
图2显示为根据本发明一实施例的具有焊线及信号信道的三维***级封装堆栈式封装结构的截面图。如图2所示，三维***级封装堆栈式封装结构包含一图1中基础三维堆栈式封装结构、焊垫(bonding pads)124、焊线(wirebonds)125、成型材料(molding material)126、终端垫121、封装黏合材料(packageattach)123、导电组件122及一基底120。在本实施例中，保护层107形成于信号信道106之上以保护及覆盖信号信道106与介电(缓冲)层105，以形成多个开口以暴露信号信道106的第一端与第二端。信号信道106之第一端系连接至导电组件111及连接层104，而信号信道106的第二端连接至焊垫124。焊垫124形成于信号信道106的第二端之上。焊线125的一端位于(连接至)基底120的终端垫121之上以利于电性连接，而焊线125的另一端位于(连接至)第一封装电子构件的焊垫124之上。换言之，底部封装结构的焊垫124通过焊线125而电性连接至基底120上的终端垫121之上。终端垫121形成于基底120之中或其上。举例而言，终端垫121位于第一封装电子构件及第二电子组件的侧边，以利于第一晶粒100焊接于基底120之上表面上以建立电性连接。封装黏合材料123，例如黏着材料，形成于基底120之上及第一晶粒100、支撑组件102与填充材料103之下一预定厚度，以黏附第一封装电子构件至基底120。举例而言，封装黏合材料123，一般是指封装黏合环氧树脂，包含导电材料(金属或合金)以用于导电、胶合材料、陶瓷材料或铜膏。封装黏合材料123的面积大约为第一封装电子构件的大小。导电组件122，例如焊接凸块/球，形成于基底120之下以用于信号连接。第一封装电子构件、第二电子组件与基底120上的焊线125是借由成型材料(化合物)126而被封装，提供环境保护并免于机械应力以利于处理操作，并提供一表面以用于标记识别。图2的三维堆栈式封装结构部分的详细叙述可以参考第一图。
图3显示为根据本发明一实施例的具有并排的信号信道的三维***级封装堆栈式封装结构的截面图。在本实施例中，第一封装电子构件包含两个第一晶粒100a及100b，其中第一晶粒100a及第一晶粒100b为并排的配置。信号信道106a及106b，例如重分布层，亦为并排配置。第一晶粒100a及第一晶粒100b分别具有第一晶粒焊垫101a及101b形成于其中以用于信号连接(电性沟通)。图3的大部份类似于图1，因此省略其详细说明。
图4显示为根据本发明一实施例的具有朝上信号信道的三维***级封装堆栈式封装结构的截面图。在本实施例中，第一封装电子构件更包含焊接凸块/球垫141、焊接凸块/球142、晶粒黏合材料(die attach)143及保护层140。晶粒黏合材料143形成于第一晶粒100之下的一特定的厚度。晶粒黏合材料143为一黏着材料(例如铜膏)、含金属基底或含陶瓷基底以利于热传导。在一实施例中，支撑组件102、填充材料103及晶粒黏合材料143的底部表面为共平面。保护层140形成于晶粒黏合材料143、支撑组件102与填充材料103之下以用于保护。在一实施例中，保护层140与支撑组件102为相同材料。换言之，保护层140与支撑组件102可以借由相同制程所形成。在此例子中，无需向下延伸电性传导，保护层140作为底部基底以提升屏蔽效应及封装结构强度。焊接凸块/球142形成(位)于焊接凸块/球垫141之上以用于信号连接。图4大部分类似于图1，因此省略其详细说明。在本实施例中，保护层107形成于信号信道106之上以保护及覆盖信号信道106及介电(缓冲)层105，并形成多个开口以暴露信号信道106的第一端及第二端。信号信道106的第一端连接至导体组件111及连接层104，而信号信道106的第二端连接至焊接凸块/球垫141。焊接凸块/球垫141形成于信号信道106的第二端之上。
图5显示为根据本发明一实施例的具有背部信号信道的三维***级封装堆栈式封装结构的截面图。在本实施例中，第一封装电子构件更包含背部信号信道152、连接层151、焊接凸块/球155、介电层153及保护层154。介电层153形成于第一晶粒100、第一部分支撑组件102a及填充材料103之下的一特定厚度。在一实施例中，第二部分支撑组件102b的底部表面与介电层153的下表面为共平面。背部信号信道152形成于第二部分支撑组件102b与介电层153之下，以连接第二部分支撑组件102b。保护层154形成于介电层153之下以保护及覆盖背部信号信道152与介电层153，并形成多个开口以暴露背部信号信道152。焊接凸块/球155形成(位)于保护层154及背部信号信道152之下，以连接至背部信号信道152以用于信号连接。图5大部分类似于图1，因此图5的三维堆栈式封装结构的部分的详细说明可以参考图1。在本实施例中，介电(缓冲)层105形成于第一晶粒100、支撑组件102及填充材料103支上，而产生多个开口以暴露第一晶粒100的晶粒焊垫101与支撑组件102的上表面，因而连接层151形成于(连接至)第一晶粒100的晶粒焊垫101与支撑组件102上表面之上。
值得注意的是，保护层(薄膜)的厚度较佳为约0.1微米至0.3微米，反射率接近空气反射率1。保护层的材料可以为硅橡胶、弹性材料、感光材料、介电材料、SiO2、Al2O3、玻璃、合金、金属或陶瓷。
电子组件经由穿孔而穿透支撑组件，因此晶粒封装的厚度明显地缩小。本发明的封装比现有技术更薄。再者，支撑组件于封装之前预制。晶粒穿孔与填充穿孔亦预先决定。因此，产能可以比以前得到提升。
因此，本发明的优点包含：
支撑组件预设晶粒接收穿孔；而由于晶粒嵌入支撑组件内部，因此得以产生超薄封装；借由填入硅橡胶作为缓冲区域以吸收硅晶粒及支撑组件间的热膨胀系数(CTE～2.3)不匹配所产生热应力；由于应用简单的制程使得封装产能得以提升(制作时间缩短)。封装及板级的可靠度较传统佳，不会导致热机械应力施加于焊接凸块/球。成本低廉且制程简易。制程可以完全地自动，尤其于模块组装中。易制作多芯片封装(双芯片封装)。由于无粒子污染、制程简易及完全自动化，可以得到较高的良率。
以上所述实施例仅是为充分说明本发明而所举的较佳的实施例，本发明的保护范围不限于此。本技术领域的技术人员在本发明基础上所作的等同替代或变换，均在本发明的保护范围之内。本发明的保护范围以权利要求书为准。

Claims (8)

1.一种三维***级封装堆栈式封装结构，其特征在于，包含：
至少一第一电子组件，具有第一晶粒焊垫；
一支撑组件，形成以围绕所述至少一第一电子组件，所述支撑组件具有预定的晶粒穿孔及多个开口穿过支撑组件，所述支撑组件包含导电材料；
一填充材料，填入于所述至少一第一电子组件与所述支撑组件之间；
一介电层，形成于所述至少一第一电子组件、所述支撑组件与所述填充材料之上以暴露所述第一晶粒焊垫；
信号信道，形成于所述介电层之上，并耦接所述第一晶粒焊垫；
一第一保护层，形成于所述信号信道之上以暴露所述该信号信道的第一端；
导体组件，形成于所述信号信道的第一端之上；
一第二电子组件，具有第二晶粒焊垫耦接所述导体组件；以及
一第二保护层，形成于所述第二电子组件之下以暴露所述第二电子组件的第二晶粒焊垫；
一第二介电层，形成于所述第一电子组件、所述支撑组件的第一部分及所述填充材料之下；
一背部信号信道，形成于所述第二介电层之下，连接至所述支撑组件的第二部分；
一连接层，形成于所述第一晶粒焊垫及所述支撑组件的第二部分之上，与所述信号信道之下，所述连接层包括导电材料；
其中所述第一电子组件通过所述信号信道、连接层、支撑组件的第二部分、背部信号信道而电性连接焊接球；
所述第二电子组件通过所述导体组件、信号信道、连接层、支撑组件的第二部分、背部信号信道而电性连接焊接球。
2.如权利要求1所述的三维***级封装堆栈式封装结构，其特征在于，还包含一第三保护层形成于所述第二介电层之下。
3.如权利要求2所述的三维***级封装堆栈式封装结构，其特征在于，所述焊接球形成于所述第三保护层及所述背部信号信道之下，连接至所述背部信号信道。
4.如权利要求1所述的三维***级封装堆栈式封装结构，其特征在于，所述导电材料包含合金或金属。
5.一种三维***级封装堆栈式封装结构，还包含其特征在于，包含：
至少一第一电子组件，具有第一晶粒焊垫；
一支撑组件，形成以围绕所述至少一第一电子组件，所述支撑组件具有预定的晶粒穿孔及多个开口穿过支撑组件；
一填充材料，填入于所述至少一第一电子组件与所述支撑组件之间；
一介电层，形成于所述至少一第一电子组件、所述支撑组件与所述填充材料之上以暴露所述第一晶粒焊垫；
信号信道，形成于所述介电层之上，并耦接所述第一晶粒焊垫；
一第一保护层，形成于所述信号信道之上以暴露所述该信号信道的第一端；
导体组件，形成于所述信号信道的第一端之上；
一第二电子组件，具有第二晶粒焊垫耦接所述导体组件；
一第二保护层，形成于所述第二电子组件之下以暴露所述第二电子组件的第二晶粒焊垫；
一基底，具有终端垫形成于其上，以及一黏着层形成于所述基底之上与所述至少一第一电子组件、所述支撑组件及所述填充材料之下；以及
一焊垫形成于所述信号信道的第二端上，其中所述焊垫通过焊线而电性连接至所述终端垫。
6.如权利要求5所述的三维***级封装堆栈式封装结构，其特征在于，还包含一成型材料以用于封装所述第一电子组件、所述第二电子组件及所述基底上的终端垫。
7.如权利要求6所述的三维***级封装堆栈式封装结构，其特征在于，还包含第二导体组件形成于所述基底之下。
8.如权利要求5所述的三维***级封装堆栈式封装结构，其特征在于，还包含一连接层，形成于所述信号信道与所述第一晶粒焊垫之间，用以电性连接所述信号信道与所述第一晶粒焊垫。
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