CN102569053B - Method for forming high-dielectric constant metal grid - Google Patents
Method for forming high-dielectric constant metal grid Download PDFInfo
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- CN102569053B CN102569053B CN201210014806.7A CN201210014806A CN102569053B CN 102569053 B CN102569053 B CN 102569053B CN 201210014806 A CN201210014806 A CN 201210014806A CN 102569053 B CN102569053 B CN 102569053B
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- dielectric constant
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- metal grid
- metallic aluminum
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Abstract
The invention discloses a method for forming a high-dielectric constant metal grid. The method comprises the following steps of: firstly, depositing a metal layer on a substrate through physical vapor phase deposition; secondly, patterning aluminum on the metal layer for the first time; thirdly, oxidizing the surface of the aluminum subjected to patterning in pure water electrolyte into uniform and compact high-dielectric constant aluminum oxide to form a grid insulating layer, wherein while a metal retaining layer is removed in an electrolyzing process, a part with certain thickness of the top of the metal grid is also removed in the electrolyzing process, the grid insulating layer is mainly covered on the metal grid, and the electrolyte electrolyzes the two sides of the periphery of the metal layer; fourthly, patterning the high-dielectric constant aluminum oxide for the second time; and finally, forming the high-dielectric constant metal grid. According to the method for forming the high-dielectric constant metal grid, an atom layer deposition method is not adopted, so the yield is effectively improved, at the same time, the utilization of a light shade is reduced and the cost is reduced.
Description
Technical field
The present invention relates to a kind of technology method of semiconductor integrated circuit, particularly relate to the formation method of a kind of high-k (K) metal gate.
Background technology
The main devices of integrated circuit especially in very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOS transistor).Since metal-oxide-semiconductor is invented, its physical dimension is constantly reducing always, and its characteristic size has entered 45nm scope at present.Under this size, various reality with basic restriction and technological challenge start occur, reducing further of device size just becomes more and more difficult.Wherein, MOS transistor device and circuit preparation in, most is challenging be conventional CMOS device in the process reduced due to polysilicon/SiO
2or SiON gate oxide dielectric thickness reduces the high grid Leakage Current that brings.
For this reason, the solution proposed is, adopts metal gate and high-k (K) gate medium to substitute traditional heavily doped polysilicon grid and SiO
2(or SiON) gate medium.According to integrated circuit technique way for development line chart, the practical application of metal gate, high-k (K) gate medium will in sub-65nm technology.Now widely used is substantially all hafnium base high-k (K) gate medium, it is formed by the mode of ald (ALD:atomic layer deposition), metal gate is then formed by the method for physical vapour deposition (PVD), the efficiency of ald is lower, physical vapour deposition (PVD) then easily causes grid plasma damage, and the temperature of these two kinds of techniques is all relatively high, the demand of some products and technique can not be met.
Summary of the invention
The invention provides a kind of formation method of high-dielectric constant metal grid, in order to solve the problem that existing technique needs to adopt inefficient Atomic layer deposition method and higher temperature to produce.
To achieve these goals, the technical scheme that the present invention takes is:
Form a method for high-dielectric constant metal grid, wherein, first, substrate adopts physical vapour deposition (PVD) metal level, then, primary graphical aluminium process is carried out to described metal level; First time implements etching process to metal level, and metal gate covers etch mask, and metal level not the part that hides by mask be etched away to a certain extent; Then patterned described aluminium will be completed in pure water electrolyte by high-k aluminium oxide that surface oxidation is uniformly fine and close, form gate insulator, metal retaining layer be removed in electrolytic process and simultaneously the top of metal gate in electrolytic process, be also removed certain thickness, gate insulator mainly covers on metal gate, and electrolytic treatments is carried out in peripheral for metal level both sides by electrolyte, and secondary graphical treatment is carried out to high-k aluminium oxide, finally, high-dielectric constant metal grid is formed.
A kind of above-mentioned method forming high-dielectric constant metal grid, wherein, the thickness of described metal level substrate adopting the method for deposition deposit is 100nm ~ 500nm.
A kind of above-mentioned method forming high-dielectric constant metal grid, wherein, by protective layer of alumina uniformly fine and close for the surface oxidation completing patterned described metal level in pure water electrolyte.
A kind of above-mentioned method forming high-dielectric constant metal grid, wherein, electrolytic process carries out in pure water, and is anode with aluminium, take platinum as negative electrode.
A kind of above-mentioned method forming high-dielectric constant metal grid, wherein, anode reaction equation is: 2Al+3H
2o → Al
2o
3+ 6H
++ 6e
-; Cathode reaction equation is: 6H
++ 6e
-→ 3H
2.
The application of redundant metal filling of metal layer test light mask, wherein, carries out secondary graphical treatment to high-k aluminium oxide, removes the aluminium oxide beyond high-k and aluminium.
The application of redundant metal filling of metal layer test light mask, wherein, the thickness of the part that described metal gate top is fallen by electrolysis equals the thickness of described metal retaining layer haply.
The application of redundant metal filling of metal layer test light mask, wherein, described metal level is aluminium.
The present invention is owing to have employed above-mentioned technology, and the good effect making it to have is:
(1) the present invention does not adopt atomic layer deposition method, effectively improves productivity ratio.。
(2) the present invention effectively reduces the use of light shield.
(3) the present invention significantly reduces cost.
Accompanying drawing explanation
Fig. 1 is a kind of schematic diagram forming electrolytic process in the method for high-dielectric constant metal grid of the present invention;
Fig. 2 is a kind of flow chart forming the method for high-dielectric constant metal grid of the present invention;
Fig. 3 is a kind of schematic diagram forming the finished product of the method for high-dielectric constant metal grid of the present invention.
Embodiment
A kind of embodiment forming the method for high-dielectric constant metal grid of the present invention is provided below in conjunction with accompanying drawing.
Fig. 1 is a kind of schematic diagram forming electrolytic process in the method for high-dielectric constant metal grid of the present invention, Fig. 2 is a kind of flow chart forming the method for high-dielectric constant metal grid of the present invention, Fig. 3 is a kind of schematic diagram forming the finished product of the method for high-dielectric constant metal grid of the present invention, refers to shown in Fig. 1, Fig. 2 and Fig. 3.A kind of method forming high-dielectric constant metal grid of the present invention, first, at substrate 1(Substrate) the upper method deposited metal 2(metal level 2 of physical vapour deposition (PVD) that adopts can be chosen as aluminium, and metal level 2 prepares metal gate for follow-up).Then, first time graphical aluminium process is carried out to this metal level 2.Implement in etching process in first time to metal level 2, metal gate 21 can cover etch mask (not illustrating), metal level 2 not the part that hides by mask be then etched away to a certain extent.Such as shown in figure, metal level 2 is etched to metal gate 21 and is looped around the metal retaining layer 22 around metal gate 21, and mainly etching removes the certain thickness metal level in the peripheral both sides of metal gate 21.Wherein, the Thickness Ratio of metal retaining layer 22 is thinner, and the thickness of metal gate 21 is much larger than the thickness of metal retaining layer 22.Then, to patterned metal level 2 be completed in pure water electrolyte by high-k (K) aluminium oxide that surface oxidation is uniformly fine and close, form gate insulator 3(Gate dielectric), metal retaining layer 22 be removed in electrolytic process and simultaneously the top of metal gate 21 in electrolytic process, be also removed certain thickness, the thickness of the part that metal gate 21 top is fallen by electrolysis equals the thickness of metal retaining layer 22 haply.Gate insulator 3 mainly covers on metal gate 21, and electrolytic treatments is carried out in peripheral for metal level 2 both sides by electrolyte, and carries out secondary graphical treatment to high-k (K) aluminium oxide, finally, forms high-k (K) metal gate.
The present invention also has following execution mode on above-mentioned basis:
In the first embodiment of the present invention, please continue see shown in Fig. 1, Fig. 2 and Fig. 3.At substrate 1(Substrate) the upper thickness adopting the described metal level 2 of the method deposition of deposition is 100nm ~ 500nm.
In the second embodiment of the present invention, shown in Figure 1.At pure water electrolyte 5(aqueous electrolyte) in by protective layer of alumina uniformly fine and close for the surface oxidation that completes patterned described metal level 2.Meanwhile, electrolytic process carries out in pure water, and with metal level 2 for anode, with platinum 4(Pt) be negative electrode.At power supply 6(Current Source) lower metal layer 2 anode reaction equation is: 2Al+3H
2o → Al
2o
3+ 6H
++ 6e
-, platinum 4(Pt) and cathode reaction equation is: 6H
++ 6e
-→ 3H
2.
In the third embodiment of the present invention, shown in Figure 2.Secondary graphical treatment is carried out to high-k (K) aluminium oxide, removes the aluminium oxide beyond high-k (K) and aluminium.
In the fourth embodiment of the present invention, shown in Figure 3.Fig. 3 is a kind of finished product forming the method for high-dielectric constant metal grid of the present invention, at gate insulator 3(Gate dielectric) peripheral both sides there is source electrode 8(Source respectively) and drain electrode 7(Drain), and at gate insulator 3(Gate dielectric) on semiconductor 9(Semiconductor is set).
In sum, use a kind of method forming high-dielectric constant metal grid of the present invention, make it not adopt atomic layer deposition method, effectively improve productivity ratio, meanwhile, decrease the use of light shield, and reduce cost.
Above specific embodiments of the invention are described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the method wherein do not described in detail to the greatest extent and processing procedure are construed as to be implemented with the common mode in this area; Those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect flesh and blood of the present invention.All any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. form a method for high-dielectric constant metal grid, it is characterized in that, first, substrate adopts physical vapour deposition (PVD) metallic aluminum, then, primary graphical aluminium process is carried out to described metallic aluminum; First time implements etching process to metallic aluminum, and metal gate covers etch mask, and metallic aluminum not the part that hides by mask be etched away to a certain extent; Then patterned described aluminium will be completed in pure water electrolyte by high-k aluminium oxide that surface oxidation is uniformly fine and close, form gate insulator, metal retaining layer be removed in electrolytic process and simultaneously the top of metal gate in electrolytic process, be also removed certain thickness, gate insulator mainly covers on metal gate, and electrolytic treatments is carried out in peripheral for metallic aluminum both sides by electrolyte; Secondary graphical treatment is carried out to high-k aluminium oxide, finally, forms high-dielectric constant metal grid.
2. form the method for high-dielectric constant metal grid according to claim 1, it is characterized in that, the thickness of described metallic aluminum substrate adopting the method for deposition deposit is 100nm ~ 500nm.
3. form the method for high-dielectric constant metal grid according to claim 1, it is characterized in that, by protective layer of alumina uniformly fine and close for the surface oxidation completing patterned described metallic aluminum in pure water electrolyte.
4. form the method for high-dielectric constant metal grid according to claim 3, it is characterized in that, electrolytic process carries out in pure water, and is anode with aluminium, take platinum as negative electrode.
5. form the method for high-dielectric constant metal grid according to claim 4, it is characterized in that, anode reaction equation is: 2Al+3H2O → Al2O3+6H++6e-; Cathode reaction equation is: 6H++6e-→ 3H2.
6. form the method for high-dielectric constant metal grid according to claim 1, it is characterized in that, the thickness of the part that described metal gate top is fallen by electrolysis equals the thickness of described metal retaining layer haply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210014806.7A CN102569053B (en) | 2012-01-18 | 2012-01-18 | Method for forming high-dielectric constant metal grid |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210014806.7A CN102569053B (en) | 2012-01-18 | 2012-01-18 | Method for forming high-dielectric constant metal grid |
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| Publication Number | Publication Date |
|---|---|
| CN102569053A CN102569053A (en) | 2012-07-11 |
| CN102569053B true CN102569053B (en) | 2014-12-24 |
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|---|---|---|---|
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1078068A (en) * | 1992-04-07 | 1993-11-03 | 株式会社半导体能源研究所 | Form the method for semiconductor device |
| CN1081022A (en) * | 1992-03-27 | 1994-01-19 | 株式会社半导体能源研究所 | A kind of semiconductor device and manufacture method thereof |
| US6300203B1 (en) * | 2000-10-05 | 2001-10-09 | Advanced Micro Devices, Inc. | Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
-
2012
- 2012-01-18 CN CN201210014806.7A patent/CN102569053B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1081022A (en) * | 1992-03-27 | 1994-01-19 | 株式会社半导体能源研究所 | A kind of semiconductor device and manufacture method thereof |
| CN1078068A (en) * | 1992-04-07 | 1993-11-03 | 株式会社半导体能源研究所 | Form the method for semiconductor device |
| US6300203B1 (en) * | 2000-10-05 | 2001-10-09 | Advanced Micro Devices, Inc. | Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
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| Publication number | Publication date |
|---|---|
| CN102569053A (en) | 2012-07-11 |
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