CN102569053A - Method for forming high-dielectric constant metal grid - Google Patents
Method for forming high-dielectric constant metal grid Download PDFInfo
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- CN102569053A CN102569053A CN2012100148067A CN201210014806A CN102569053A CN 102569053 A CN102569053 A CN 102569053A CN 2012100148067 A CN2012100148067 A CN 2012100148067A CN 201210014806 A CN201210014806 A CN 201210014806A CN 102569053 A CN102569053 A CN 102569053A
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- metal gate
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- aluminium
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Abstract
The invention discloses a method for forming a high-dielectric constant metal grid. The method comprises the following steps of: firstly, depositing a metal layer on a substrate through physical vapor phase deposition; secondly, patterning aluminum on the metal layer for the first time; thirdly, oxidizing the surface of the aluminum subjected to patterning in pure water electrolyte into uniform and compact high-dielectric constant aluminum oxide to form a grid insulating layer, wherein while a metal retaining layer is removed in an electrolyzing process, a part with certain thickness of the top of the metal grid is also removed in the electrolyzing process, the grid insulating layer is mainly covered on the metal grid, and the electrolyte electrolyzes the two sides of the periphery of the metal layer; fourthly, patterning the high-dielectric constant aluminum oxide for the second time; and finally, forming the high-dielectric constant metal grid. According to the method for forming the high-dielectric constant metal grid, an atom layer deposition method is not adopted, so the yield is effectively improved, at the same time, the utilization of a light shade is reduced and the cost is reduced.
Description
Technical field
The present invention relates to a kind of technology method of semiconductor integrated circuit, relate in particular to the formation method of a kind of high-k (K) metal gate.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOS transistor).Since metal-oxide-semiconductor was invented, its physical dimension was constantly being dwindled always, and its characteristic size has got into the 45nm scope at present.Under this size, various reality and basic restriction and technological challenge begin to occur, device size further dwindle the more and more difficult that just becomes.Wherein, in the preparation of MOS transistor device and circuit, tool is challenging be the traditional cmos device in the process of dwindling because polysilicon/SiO
2Or the SiON gate oxide dielectric thickness high grid Leakage Current that reduces to bring.
For this reason, the solution that has proposed is to adopt metal gate and high-k (K) gate medium to substitute traditional heavily doped polysilicon grid and SiO
2(or SiON) gate medium.According to integrated circuit technique development course figure, the practical application of metal gate, high-k (K) gate medium will be in inferior 65nm technology.At present widely used basically all is hafnium base high-k (K) gate medium; It is that mode through ald (ALD:atomic layer deposition) forms; Metal gate then is that the method through physical vapour deposition (PVD) forms, and the efficient of ald is lower, and physical vapour deposition (PVD) then causes the grid plasma damage easily; And the temperature of these two kinds of technologies is all higher relatively, can not satisfy the demand of some products and technology.
Summary of the invention
The present invention provides a kind of formation method of high-k metal gate, in order to solve the problem that existing arts demand adopts inefficient Atomic layer deposition method and higher temperature to produce.
To achieve these goals, the technical scheme taked of the present invention is:
A kind of method that forms the high-k metal gate wherein, at first, adopts the physical vapour deposition (PVD) metal level on substrate, then, said metal level is carried out primary graphical aluminium handle; For the first time metal level is implemented etching process, cover etch mask on the metal gate, and not being etched away to a certain extent by the part that mask hid of metal level; Then will accomplish patterned said aluminium changes into surface oxygen even compact in pure water electrolyte high-k aluminium oxide; Form gate insulator; The metal retaining layer in electrolytic process, be removed and simultaneously the top of metal gate also in electrolytic process, be removed certain thickness; Gate insulator mainly covers on the metal gate, and electrolyte carries out electrolytic treatments with the peripheral both sides of metal level, and the high-k aluminium oxide is carried out secondary graphical treatment; At last, form the high-k metal gate.
Above-mentioned a kind of method that forms the high-k metal gate, wherein, on substrate, adopting the said metal layer thickness of the method deposition of deposition is 100nm ~ 500nm.
Above-mentioned a kind of method that forms the high-k metal gate, wherein, the surface oxygen that in pure water electrolyte, will accomplish patterned said metal level changes into the protective layer of alumina of even compact.
Above-mentioned a kind of method that forms the high-k metal gate, wherein, electrolytic process carries out in pure water, and is anode with aluminium, is negative electrode with platinum.
Above-mentioned a kind of method that forms the high-k metal gate, wherein, the anode reaction equation is: 2Al+3H
2O → Al
2O
3+ 6H
++ 6e
-The cathode reaction equation is: 6H
++ 6e
-→ 3H
2
The redundant metal filled test light mask of a kind of metal level is used, and wherein, the high-k aluminium oxide is carried out secondary graphical treatment, removes aluminium oxide and aluminium beyond the high-k.
The redundant metal filled test light mask of a kind of metal level is used, and wherein, the thickness of the part that said metal gate top is fallen by electrolysis equals the thickness of said metal retaining layer haply.
The redundant metal filled test light mask of a kind of metal level is used, and wherein, said metal level is an aluminium.
The present invention is owing to adopted above-mentioned technology, and the good effect that makes it to have is:
(1) the present invention does not adopt atomic layer deposition method, has improved productivity ratio effectively.。
(2) the present invention has reduced the use of light shield effectively.
(3) the present invention has reduced cost effectively.
Description of drawings
Fig. 1 is the sketch map of electrolytic process in a kind of method that forms the high-k metal gate of the present invention;
Fig. 2 is a kind of flow chart that forms the method for high-k metal gate of the present invention;
Fig. 3 is the sketch map of the finished product of a kind of method that forms the high-k metal gate of the present invention.
Embodiment
Provide a kind of embodiment that forms the method for high-k metal gate of the present invention below in conjunction with accompanying drawing.
The sketch map of electrolytic process in the method that Fig. 1 forms the high-k metal gate for the present invention is a kind of; Fig. 2 is a kind of flow chart that forms the method for high-k metal gate of the present invention; The sketch map of the finished product of the method that Fig. 3 forms the high-k metal gate for the present invention is a kind of sees also Fig. 1, Fig. 2 and shown in Figure 3.A kind of method that forms the high-k metal gate of the present invention at first, goes up the method deposited metal 2 (metal level 2 can be chosen as aluminium, and metal level 2 is used for the subsequent preparation metal gate) that adopts physical vapour deposition (PVD) at substrate 1 (Substrate).Then, this metal level 2 is carried out the graphical aluminium processing first time.For the first time metal level 2 is being implemented can cover etch mask (not illustrating) on the metal gate 21 in the etching processes then not being etched away to a certain extent of metal level 2 by the part that mask hid.For example shown in the figure, metal level 2 is etched to metal gate 21 and is looped around metal gate 21 metal retaining layer 22 on every side, mainly is that etching is removed the certain thickness metal levels in metal gate 21 peripheral both sides.Wherein, the thickness of metal retaining layer 22 is thinner, and the thickness of metal gate 21 is much larger than the thickness of metal retaining layer 22.Then; With accomplishing patterned metal level 2 changes into surface oxygen even compact in pure water electrolyte high-k (K) aluminium oxide; Form gate insulator 3 (Gate dielectric); Metal retaining layer 22 in electrolytic process, be removed and simultaneously the top of metal gate 21 also in electrolytic process, be removed certain thickness, the thickness of the part that metal gate 21 tops are fallen by electrolysis equals the thickness of metal retaining layer 22 haply.Gate insulator 3 mainly is to cover on the metal gate 21, and electrolyte carries out electrolytic treatments with metal level 2 peripheral both sides, and high-k (K) aluminium oxide is carried out secondary graphical treatment, and is last, forms high-k (K) metal gate.
The present invention also has following execution mode on above-mentioned basis:
In the first embodiment of the present invention, please continue referring to Fig. 1, Fig. 2 and shown in Figure 3.The thickness of going up the said metal level 2 of the method deposition that adopts deposition at substrate 1 (Substrate) is 100nm ~ 500nm.
In the second embodiment of the present invention, see also shown in Figure 1.The surface oxygen that in pure water electrolyte 5 (aqueous electrolyte), will accomplish patterned said metal level 2 changes into the protective layer of alumina of even compact.Simultaneously, electrolytic process carries out in pure water, and is anode with metal level 2, is negative electrode with platinum 4 (Pt).At power supply 6 (Current Source) lower metal layer 2 anode reaction equations be: 2Al+3H
2O → Al
2O
3+ 6H
++ 6e
-, platinum 4 (Pt) cathode reaction equation is: 6H
++ 6e
-→ 3H
2
In the third embodiment of the present invention, see also shown in Figure 2.High-k (K) aluminium oxide is carried out secondary graphical treatment, remove high-k (K) aluminium oxide and aluminium in addition.
In the fourth embodiment of the present invention, see also shown in Figure 3.Fig. 3 is a kind of finished product that forms the method for high-k metal gate of the present invention; Have source electrode 8 (Source) and drain electrode 7 (Drain) in the peripheral both sides of gate insulator 3 (Gate dielectric) respectively, and on gate insulator 3 (Gate dielectric), semiconductor 9 (Semiconductor) is set.
In sum, use a kind of method that forms the high-k metal gate of the present invention, make it not adopt atomic layer deposition method, improved productivity ratio effectively, simultaneously, reduced the use of light shield, and reduced cost.
More than specific embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, method of wherein not describing in detail to the greatest extent and processing procedure are construed as with the common mode in this area to be implemented; Those skilled in the art can make various distortion or modification within the scope of the claims, and this does not influence flesh and blood of the present invention.All any modifications of within spirit of the present invention and principle, being done, be equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a method that forms the high-k metal gate is characterized in that, at first, on substrate, adopts the physical vapour deposition (PVD) metal level, then, said metal level is carried out primary graphical aluminium handle; For the first time metal level is implemented etching process, cover etch mask on the metal gate, and not being etched away to a certain extent by the part that mask hid of metal level; Then will accomplish patterned said aluminium changes into surface oxygen even compact in pure water electrolyte high-k aluminium oxide; Form gate insulator; The metal retaining layer in electrolytic process, be removed and simultaneously the top of metal gate also in electrolytic process, be removed certain thickness; Gate insulator mainly covers on the metal gate, and electrolyte carries out electrolytic treatments with the peripheral both sides of metal level; The high-k aluminium oxide is carried out secondary graphical treatment, last, form the high-k metal gate.
2. according to the method for the said formation high-k of claim 1 metal gate, it is characterized in that on substrate, adopting the said metal layer thickness of the method deposition of deposition is 100nm ~ 500nm.
3. according to the method for the said formation high-k of claim 1 metal gate, it is characterized in that the surface oxygen that in pure water electrolyte, will accomplish patterned said metal level changes into the protective layer of alumina of even compact.
4. according to the method for the said formation high-k of claim 3 metal gate, it is characterized in that electrolytic process carries out in pure water, and be anode with aluminium, is negative electrode with platinum.
5. according to the method for the said formation high-k of claim 4 metal gate, it is characterized in that the anode reaction equation is: 2Al+3H
2O → Al
2O
3+ 6H
++ 6e
-The cathode reaction equation is: 6H
++ 6e
-→ 3H
2
6. according to the method for the said formation high-k of claim 1 metal gate, it is characterized in that, the high-k aluminium oxide is carried out secondary graphical treatment, remove aluminium oxide and aluminium beyond the high-k.
7. according to the method for the said formation high-k of claim 1 metal gate, it is characterized in that the thickness of the part that said metal gate top is fallen by electrolysis equals the thickness of said metal retaining layer haply.
8. according to the method for the said formation high-k of claim 1 metal gate, it is characterized in that said metal level is an aluminium.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210014806.7A CN102569053B (en) | 2012-01-18 | 2012-01-18 | Method for forming high-dielectric constant metal grid |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210014806.7A CN102569053B (en) | 2012-01-18 | 2012-01-18 | Method for forming high-dielectric constant metal grid |
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| Publication Number | Publication Date |
|---|---|
| CN102569053A true CN102569053A (en) | 2012-07-11 |
| CN102569053B CN102569053B (en) | 2014-12-24 |
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|---|---|---|---|
| CN201210014806.7A Active CN102569053B (en) | 2012-01-18 | 2012-01-18 | Method for forming high-dielectric constant metal grid |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1078068A (en) * | 1992-04-07 | 1993-11-03 | 株式会社半导体能源研究所 | Form the method for semiconductor device |
| CN1081022A (en) * | 1992-03-27 | 1994-01-19 | 株式会社半导体能源研究所 | A kind of semiconductor device and manufacture method thereof |
| US6300203B1 (en) * | 2000-10-05 | 2001-10-09 | Advanced Micro Devices, Inc. | Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
-
2012
- 2012-01-18 CN CN201210014806.7A patent/CN102569053B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1081022A (en) * | 1992-03-27 | 1994-01-19 | 株式会社半导体能源研究所 | A kind of semiconductor device and manufacture method thereof |
| CN1078068A (en) * | 1992-04-07 | 1993-11-03 | 株式会社半导体能源研究所 | Form the method for semiconductor device |
| US6300203B1 (en) * | 2000-10-05 | 2001-10-09 | Advanced Micro Devices, Inc. | Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
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|---|---|
| CN102569053B (en) | 2014-12-24 |
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