CN102544032A - 晶片规模x射线检测器及其制造方法 - Google Patents
晶片规模x射线检测器及其制造方法 Download PDFInfo
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Abstract
本发明提供了一种晶片规模x射线检测器及其制造方法。所述晶片规模x射线检测器包括:无缝硅基底,电连接到印刷电路基底;芯片阵列,位于无缝硅基底上并具有形成在芯片阵列的中心区域上的多个芯片焊盘和形成在芯片阵列的边缘上的多个引脚焊盘;多个像素电极,形成为对应于像素焊盘;竖直布线和水平布线,形成为补偿从芯片阵列和像素电极之间的像素焊盘向像素电极扩展的区域的差;再分布层,具有绝缘层以使竖直布线和水平布线分开;光电导体层和共电极,覆盖再分布层上的像素电极。
Description
技术领域
本公开涉及一种实现了无缝图像的晶片规模x射线检测器及其制造方法。
背景技术
数字x射线检测器响应通过x射线拍摄的x射线图像或x射线透视图像来输出数字信号。可通过直接法或间接法对这种x射线检测器进行操作。
在直接法中,x射线被直接转换成光电导体中的电荷。在间接法中,在将x射线转换成闪烁器中的可见光之后,可见光通过诸如光电二极管的光电转换器件被转换成电荷。
直接法x射线检测器包括形成在光电导体层下方的多个像素电极和处理从像素电极传输的电信号的信号处理单元。
为了利用传统的直接法制造大型x射线检测器,在专用集成电路(ASIC)上形成光电导体层。因此,当大规模地铺设具有光电导体层的ASIC时,由于ASIC之间的接缝导致在接缝区域,一部分图像未被检测。具体地讲,铺设ASIC时可形成尺寸为100μm或超过100μm的接缝,因此在这些接缝中的组织可能未被检测。
发明内容
本发明提供了一种利用以晶片规模制造的芯片阵列来实现无缝成像区域的晶片规模x射线检测器及其制造方法。
将在接下来的描述中部分阐述本发明另外的方面,还有一部分通过描述将是清楚的,或者可以经过本发明的实施而得知。
根据本发明的实施例,提供了一种晶片规模x射线检测器,所述晶片规模x射线检测器包括:无缝硅基底,在其表面上具有多个芯片区域;光电导体层,形成在所述无缝硅基底的所述表面上方;多个像素电极,形成在所述无缝硅基底的所述表面和所述光电导体层之间;印刷电路基底,设置成与所述无缝硅基底的另一表面对应;共电极,形成在所述光电导体层上并且x射线照射在所述共电极上,其中,每个芯片区域包括多个像素焊盘和多个引脚焊盘。
所述晶片规模x射线检测器还可包括电连接所述多个像素焊盘和所述多个像素电极的再分布层。
所述再分布层可包括至少一个绝缘层、穿过所述至少一个绝缘层的竖直布线及水平布线。
被与所述多个像素焊盘对应的像素电极覆盖的面积可大于被所述多个像素焊盘覆盖的面积。
所述多个引脚焊盘可被设置成围绕所述多个像素焊盘,并且所述多个引脚焊盘和所述多个像素焊盘相互电连接。
根据本发明的一方面,所述晶片规模x射线检测器还可包括所述无缝硅基底上的多个通孔,其中,每个引脚焊盘通过通路接触件电连接到所述印刷电路基底。
所述晶片规模x射线检测器还可包括设置在所述通路接触件和所述印刷电路基底之间的凸块,其中,所述凸块将所述通路接触件和所述印刷电路基底电连接。
根据本发明的另一方面,所述晶片规模x射线检测器还可包括形成在所述无缝硅基底上的多个通孔和对应通孔上的通路接触件,其中,每个通路接触件电连接到穿过每个引脚焊盘形成的金属。
所述印刷电路基底可为单个印刷电路基底,并可设置成与所述多个芯片区域对应。
所述印刷电路基底可包括多个印刷电路基底,所述多个印刷电路基底中的每个可以以与所述多个芯片区域中的每个一一对应的关系设置。
所述晶片规模x射线检测器还可包括填充在所述无缝硅基底和所述印刷电路基底之间的缝隙中的树脂。
所述无缝硅基底可由单晶硅形成。
所述光电导体层可由从由非晶硒、HgI2、PbI2、CdTe、CdZnTe和PbO组成的组中选择的至少一种材料形成。
根据本发明的一方面,提供了一种制造x射线检测器的方法,所述方法包括:在无缝硅基底的表面上形成多个芯片区域,每个芯片区域具有多个像素焊盘和多个引脚焊盘;在所述无缝硅基底的另一表面上形成通孔以暴露所述多个引脚焊盘;通过经所述通孔将所述多个引脚焊盘电连接到印刷电路基底来将所述印刷电路基底结合在所述无缝硅基底的所述另一表面上;顺序地形成多个像素电极、光电导体层和共电极,所述多个像素电极电连接到所述多个像素焊盘。
所述方法还可包括形成将所述多个像素焊盘电连接到所述多个像素电极的再分布层。
形成再分布层的步骤可包括:形成包括接触所述多个像素焊盘的竖直布线的第一绝缘层;在第一绝缘层上形成第二绝缘层,第二绝缘层包括扩大了所述多个像素电极与所述多个像素焊盘的面积对应的面积的水平布线和竖直布线。
形成第一绝缘层的步骤可包括:在所述多个像素焊盘上形成第一绝缘层;在第一绝缘层中形成连接到所述多个像素焊盘的通孔;通过用金属填充第一绝缘层中的通孔来形成第一绝缘层中的竖直布线。
形成第二绝缘层的步骤可包括:形成将连接到第一绝缘层中的竖直布线的水平布线;在第一绝缘层和水平布线上形成第二绝缘层;在第二绝缘层中形成通孔,第二绝缘层中的通孔连接到水平布线;通过用金属填充第二绝缘层中的通孔来形成第二绝缘层中的竖直布线。
所述印刷电路基底的结合的步骤可包括:在所述无缝硅基底中的通孔上形成通路接触件之后将所述印刷电路基底结合到所述无缝硅基底的所述另一表面上。
所述方法还可包括在形成通路接触件之后且在结合所述印刷电路基底之前在通路接触件和所述印刷电路基底之间形成凸块,其中,所述通路接触件通过所述凸块连接到所述印刷电路基底。
所述印刷电路基底可为与所述多个芯片区域对应的单个印刷电路基底。
所述印刷电路基底可包括以与所述多个芯片区域中的每个一一对应的关系设置的多个印刷电路基底。
附图说明
通过下面结合附图对实施例的描述,这些和/或其它方面将变得清楚且更易于理解,其中:
图1时根据本发明实施例的晶片规模x射线检测器的示意性剖视图;
图2和图3是用于解释根据本发明实施例的晶片规模x射线检测器的芯片阵列的平面图;
图4是用于解释根据本发明实施例的晶片规模x射线检测器中的像素电极和芯片阵列之间的电连接的示意性概念图;
图5A至图5F用于解释根据本发明实施例的制造图1中的x射线检测器的方法的剖视图;
图6A至图6C为用于解释根据本发明的另一实施例的制造x射线检测器的方法的剖视图。
具体实施方式
现在将详细地说明实施例,在附图中示出了实施例的示例,其中,为了说明书的清晰起见,夸大了层和区域的厚度,并且相同的标号始终表示基本相同的元件。
图1是根据本发明实施例的晶片规模x射线检测器100的示意性剖视图。
参照图1,晶片规模x射线检测器100包括印刷电路基底110上的硅基底120。硅基底120的下表面包括通路接触件139,通路接触件139电连接到形成在印刷电路基底110上的接触件112。凸块114形成在印刷电路基底110的接触件112和通路接触件139之间,以电连接接触件112和通路接触件139。
多个芯片区域在硅基底120上形成阵列。在图1中,为了方便,仅描述两个芯片区域A和B。多个像素焊盘132形成在芯片区域A和B中的每个芯片区域的中心区域,围绕像素焊盘132的引脚焊盘134形成在芯片区域A和B的边缘上。每个像素焊盘132通过导线(未示出)连接到对应的引脚焊盘134。第一绝缘层130形成在硅基底120上,以使像素焊盘132和引脚焊盘134与硅基底120绝缘。芯片区域A和B中的每个芯片区域的像素焊盘132、引脚焊盘134和硅基底120构成芯片,并且多个芯片构成芯片阵列。
通过切割单个晶片来形成芯片阵列,以使芯片阵列适用于x射线检测器。图2和图3为用于解释根据本发明实施例的晶片规模x射线检测器100的芯片阵列的平面图。
参照图2,多个芯片C设置在硅晶片W上。每个芯片C对应于上述的芯片区域。为了用于晶片规模x射线检测器100,可沿虚线切割线切割硅晶片W。因此,切割后剩余的芯片C可形成无接缝的单个硅晶片(或单个硅基底)的芯片阵列。
图3为图2中的多个芯片C中的一个芯片的平面图。在单个芯片C中形成多个像素焊盘(参照图1中的132)和围绕芯片焊盘132的引脚焊盘PE(参照图1中的134),并且像素焊盘132和引脚焊盘PE相互电连接。像素焊盘132被简单描述为像素区域PA。像素焊盘132和与像素焊盘132对应的引脚焊盘PE通过再分布层140(将在后面描述)的布线相互连接。
再次参照图1,多个印刷电路基底110可对应地设置到形成有芯片阵列的单个硅基底120。在图1中,为了便于解释,仅描述两个印刷电路基底110。单个的印刷电路基底110可被设置成对应于单个硅基底120。可选择地,印刷电路基底110包括多个印刷电路基底,所述多个印刷电路基底中的每个以与所述多个芯片区域中的每个一一对应的关系设置。此外,可选择地,印刷电路基底110为与所述多个芯片区域对应的单个印刷电路基底。
每个引脚焊盘134连接到形成在硅基底120的通孔135中的通路接触件139,并且通路接触件139通过设置在通路接触件139的端部上的凸块114电连接到印刷电路基底110的接触件112。
树脂116(例如,环氧树脂)可设置在印刷电路基底110和无缝硅基底120之间,以支撑它们。
连接像素焊盘132和像素电极150(将在后面描述)的再分布层140形成在第一绝缘层130上。再分布层140连接像素电极150和与该像素电极150对应的像素焊盘132,由于像素电极150散布在整个芯片区域上,而像素焊盘132设置在每个芯片区域的中心区域中,因此像素电极150电连接到像素电极132,如图1所示。再分布层140扩大了与像素焊盘的面积对应的像素电极150的面积。
再分布层140包括形成在芯片阵列上的第一绝缘层130和绝缘层145及穿入绝缘层130和145形成的竖直布线142、146和水平布线144。
无缝硅基底120可为单晶硅晶片。形成在单晶硅晶片上的电路具有高的操作速度和低噪声,可提高处理从光电导体传输的电信号的速度并将处理的电信号传输到印刷电路基底110。
受半导体工艺中使用的掩模的限制,每个芯片区域可以以大约2cm×2cm的最大尺寸形成。在单个芯片区域中可形成大约几万至几十万的像素焊盘132和引脚焊盘134。
在印刷电路基底110中,通过利用输入的电信号来测量将被测量的物体的x射线透射率来实现图像信号。
环氧树脂116填充在印刷电路基底110和无缝硅基底120之间的间隙中,以固定它们。
包括光电导体层160的x射线检测单元设置在再分布层140上。覆盖像素电极150的光电导体层160可形成为单个材料层。光电导体层160可由从由非晶硒(a-Se)、HgI2、PbI2、CdTe、CdZnTe和PbO组成的组中选择的至少一种材料形成。
光电导体层160的厚度可根据待测量的物体而不同。例如,如果光电导体由HgI2形成,则当测量胸部时,光电导体层160的厚度可在大约900μm至大约1000μm的范围内,并且当测量***时,光电导体层160的厚度可在大约300μm至大约400μm的范围内。另外,如果光电导体层160由a-Se形成,则当测量胸部时,光电导体层160的厚度可在大约900μm至大约1000μm的范围内,并且当测量***时,光电导体层160的厚度可在大约300μm至大约400μm的范围内。
光电导体层160根据在它上面输入的x射线的强度产生电荷。光电导体层160可被划分为多个无缝像素区域,并且像素电极150形成在每个像素区域的下侧,以将从每个像素区域收集的电荷转换成电信号。电信号被传输到对应的像素焊盘132。
连续的共电极170形成在光电导体层160上。根据施加到共电极170的直流电压在光电导体层160中形成电场,并且在光电导体层160中形成的空穴-电子对中的空穴或电子移动到每个像素电极150。从光电导体层160至像素电极150的电荷的类型可根据用于形成光电导体层160的材料而改变,因此,根据电荷的类型对共电极170施加正电压或负电压。
像素电极150通过水平布线144和竖直布线142、146连接到对应的像素焊盘132。将参照图4描述需要水平布线144的原因。在下文中,水平布线144也将被称作连接线。
图4是用于解释根据本发明实施例的晶片规模x射线检测器中的像素电极250和芯片阵列220之间的电连接的示意性概念图。在图4中,为了便于解释,仅描述一个单个芯片区域和像素电极250。
参照图4,芯片阵列220包括设置在其中心芯片区域中的像素焊盘232,并且与像素焊盘232对应的引脚焊盘234被设置成围绕像素焊盘232。同时,在芯片区域中被像素焊盘232占据的面积小于对应的像素电极250占据的面积。因此,为了利用光电导体层260的全部x射线入射面积来连接芯片阵列220的对应的像素电极250和像素焊盘232,连接线240可如图4所示倾斜地连接,或者可通过利用水平或竖直布线被连接(参照图5B、5D、5E、5F和6B)。
在图1中的x射线检测器中,像素焊盘132和像素电极150通过利用再分布层140电连接。因此,在包括相邻的芯片区域之间的间隙的光电导体层160的整个区域中检测的电荷被再分布并传输到像素焊盘132。因此,可准确地实现成像区域中的无缝图像。
图5A至图5F用于解释根据本发明实施例的制造图1中的x射线检测器的方法的剖视图。
参照图5A,多个芯片区域形成在硅晶片320上,其中,每个芯片区域具有:像素焊盘332,形成在每个芯片区域(参照图1中的A和B)的中心区域上;引脚焊盘334,在每个芯片区域的边缘上围绕像素焊盘332;第一绝缘层330,围绕像素焊盘332和引脚焊盘334。每个芯片区域可包括几万个像素焊盘332和与像素焊盘332一样多的引脚焊盘334。在图5A中,为了便于解释,描述了具有五个像素焊盘332和两个引脚焊盘332的芯片区域。连接对应的像素焊盘332和引脚焊盘334的布线未示出。第一绝缘层330使像素焊盘332和引脚焊盘334与硅晶片320绝缘。
参照图5B,通过在第一绝缘层330中形成与像素焊盘332对应的通孔341来暴露每个像素焊盘332,然后通过用金属填充通孔341来形成竖直布线342。接下来,连接到竖直布线342的水平布线343形成在第一绝缘层330上。覆盖水平布线343的第二绝缘层345形成在第一绝缘层330上。当在第二绝缘层345中形成暴露水平布线343的上表面的通孔344之后,通过用金属填充通孔344来形成竖直布线346。
连接到竖直布线346的端部的像素电极350形成在第二绝缘层345上。覆盖像素电极350的第三绝缘层355形成在第二绝缘层345上。像素电极332至像素电极350之间的水平布线343和竖直布线342、346被称作再分布层340。如参照图4所示,再分布层340可将像素焊盘332与x射线测量点一一对应地连接。
在图5B中,再分布层340包括一条水平布线343和两条垂直布线342、346。然而,根据本发明的再分布层340不限于此,并且例如,还可以在第二绝缘层345和像素电极350之间形成额外的绝缘层(未示出),并且还可在竖直布线346和像素电极350之间形成水平布线和竖直布线。
参照图5C,通过利用化学机械抛光(CMP)法对硅晶片320的下表面进行抛光来形成具有期望厚度的硅晶片320。在图5C中,为了方便,省略了第一绝缘层330上的上部结构。在下文中,硅晶片320也被称作无缝硅基底320。
通过从硅晶片320的下表面开始干蚀刻硅晶片320和第一绝缘层330来形成暴露引脚焊盘334的通孔335。尽管在图5B的剖视图中形成了两个引脚焊盘334,但是实际上,引脚焊盘334被形成为对应于像素焊盘332,并且每个引脚焊盘334被暴露。
在形成绝缘层336之后,例如,形成选择性地附于硅晶片320的下表面上的硅的氧化硅层之后,在绝缘层336和暴露的引脚焊盘334上形成阻挡层337(例如,Ti层)。之后,在阻挡层337上形成种子层338(例如,Cu层)。
在硅晶片320的下表面上形成光致抗蚀剂(未示出)以暴露形成通路接触件的区域之后,通过利用电镀法在种子层338上形成通路接触件339。在去除光致抗蚀剂之后,通过蚀刻硅晶片320的下表面来去除暴露的种子层338和阻挡层337。通路接触件339可由Au、Al、导电金属或导电聚合物形成。
参照图5D,去除第三绝缘层355的位于像素电极350上的部分。在图5D中,为了便于描述,省去了通路接触件339下方的种子层338、阻挡层337及绝缘层336。
参照图5E,通过如图2所示切割硅晶片320来形成具有方形形状的硅晶片320。
形成有与引脚焊盘334对应的接触件312的印刷电路基底310利用凸块314电连接到硅晶片320的通路接触件339,并且通过用环氧树脂316填充印刷电路基底310和硅晶片320之间的间隙来固定凸块314。
参照图5F,覆盖像素电极350的光电导体层360和共电极370顺序地形成在第三绝缘层355上。光电导体层360可利用溅射法或电子束沉积法由从由a-Se、HgI2、PbI2、CdTe、CdZnTe和PbO组成的组中选择的材料形成。光电导体层360的厚度可根据待测量的物体而改变,例如,如果光电导体层360由HgI2形成,则当测量胸部时,所述厚度可在大约500μm至大约600μm的范围内,并且当测量***时,光电导体层360的厚度可在大约300μm至大约400μm的范围内。此外,如果光电导体层360由a-Se形成,则当测量胸部时,光电导体层360的厚度可在大约900μm至大约1000μm的范围内,并且当测量***时,光电导体层360的厚度可在大约300μm至大约400μm的范围内。可利用Al或Cu将共电极370沉积为厚度在几百至几千的范围内。
根据依据本发明实施例的制造x射线检测器的方法,由于在该方法中使用了晶片规模芯片阵列,从而能够实现大幅的无缝图像。
图6A至图6C为用于解释根据本发明的另一实施例的制造x射线检测器的方法的剖视图。相同的标号被用于表示与以上描述的元件基本相同的元件,因此将不再重复对它们的详细描述。
参照图6A,在硅晶片320上的每个像素区域A和B(参照图1)上形成芯片阵列。芯片阵列包括:像素焊盘332,形成在芯片区域的中心区域中;引脚焊盘334,在芯片区域的边缘处围绕像素焊盘332;第一绝缘层330,围绕像素焊盘332和引脚焊盘334。
在形成穿透引脚焊盘334和第一绝缘层330的通孔412之后,用金属414填充通孔412。
参照图6B,在第一绝缘层330上形成再分布层340、像素电极350和第三绝缘层355。
参照图6C,通过利用CMP法对硅晶片320的下表面进行抛光来将硅晶片320形成为期望的厚度。在图6C中,为了方便,省略了第一绝缘层330上的上部结构。
通过从硅晶片320的下表面干蚀刻硅晶片320来形成暴露金属414的通孔435。在形成绝缘层436之后,例如,形成选择性地附于硅晶片320的下表面上的硅的氧化硅层之后,在绝缘层436和暴露的金属414上形成阻挡层437(例如,Ti层),之后,在阻挡层437上形成种子层438(例如,Cu层)。
在硅晶片320的下表面上形成暴露用于通路接触件的区域的光致抗蚀剂(未示出)之后,通过利用电镀法在种子层438上形成通路接触件439。在去除光致抗蚀剂之后,通过蚀刻硅晶片320的下表面来去除种子层438和阻挡层437。通路接触件439可由Au或Al形成,并电连接到穿过引脚焊盘334形成的金属414。
剩余的工艺可以与参照图5D至图5F描述的工艺相同,因此将不再重复。
在根据本发明的晶片规模x射线检测器中,在芯片区域之间的无缝区域上的光电导体中产生的电荷通过形成在光电导体下的像素电极被传递到晶片规模的芯片阵列。因此,可以准确地实现成像区域中的无缝图像。
应该理解的是,在此描述的示例性实施例应该被认为仅是描述意义的,而不是出于限制的目的。每个实施例中对特征或方面的描述通常应该被认为对其它实施例中的其它相似特征或方面来说是可用的。
Claims (24)
1.一种晶片规模x射线检测器,所述晶片规模x射线检测器包括:
无缝硅基底,在其表面上具有多个芯片区域;
光电导体层,位于所述无缝硅基底的所述表面上方;
多个像素电极,形成在所述无缝硅基底的所述表面和所述光电导体层之间;
印刷电路基底,设置成与所述无缝硅基底的另一表面对应;
共电极,形成在所述光电导体层上并且x射线照射在所述共电极上,
其中,每个芯片区域包括多个像素焊盘和多个引脚焊盘。
2.根据权利要求1所述的晶片规模x射线检测器,所述晶片规模x射线检测器还包括电连接所述多个像素焊盘和所述多个像素电极的再分布层。
3.根据权利要求2所述的晶片规模x射线检测器,其中,所述再分布层包括至少一个绝缘层、穿入所述至少一个绝缘层的竖直布线及水平布线。
4.根据权利要求1所述的晶片规模x射线检测器,其中,被与所述多个像素焊盘对应的像素电极覆盖的面积大于被所述多个像素焊盘覆盖的面积。
5.根据权利要求1所述的晶片规模x射线检测器,其中,所述多个引脚焊盘被设置成围绕所述多个像素焊盘,并且所述多个引脚焊盘和所述多个像素焊盘相互电连接。
6.根据权利要求5所述的晶片规模x射线检测器,所述晶片规模x射线检测器还包括所述无缝硅基底上的多个通孔和形成在所述多个通孔中的多个通路接触件,其中,每个引脚焊盘通过对应的通路接触件电连接到所述印刷电路基底。
7.根据权利要求6所述的晶片规模x射线检测器,所述晶片规模x射线检测器还包括设置在所述通路接触件和所述印刷电路基底之间的凸块,其中,所述凸块将所述通路接触件和所述印刷电路基底电连接。
8.根据权利要求5所述的晶片规模x射线检测器,所述晶片规模x射线检测器还包括形成在所述无缝硅基底上的多个通孔和对应通孔上的通路接触件,其中,每个通路接触件电连接到穿过每个引脚焊盘形成的金属。
9.根据权利要求1所述的晶片规模x射线检测器,其中,所述印刷电路基底为单个印刷电路基底,并设置成与所述多个芯片区域对应。
10.根据权利要求1所述的晶片规模x射线检测器,其中,所述印刷电路基底包括多个印刷电路基底,所述多个印刷电路基底中的每个以与所述多个芯片区域中的每个一一对应的关系设置。
11.根据权利要求1所述的晶片规模x射线检测器,所述晶片规模x射线检测器还包括填充在所述无缝硅基底和所述印刷电路基底之间的缝隙中的树脂。
12.根据权利要求1所述的晶片规模x射线检测器,其中,所述无缝硅基底由单晶硅形成。
13.根据权利要求1所述的晶片规模x射线检测器,其中,所述光电导体层由从由非晶硒、HgI2、PbI2、CdTe、CdZnTe和PbO组成的组中选择的至少一种材料形成。
14.一种制造x射线检测器的方法,所述方法包括:
在无缝硅基底的表面上形成多个芯片区域,每个芯片区域具有多个像素焊盘和多个引脚焊盘;
在所述无缝硅基底的另一表面上形成通孔以暴露所述多个引脚焊盘;
通过经所述通孔将所述多个引脚焊盘电连接到印刷电路基底来将所述印刷电路基底结合在所述无缝硅基底的所述另一表面上;
顺序地形成多个像素电极、光电导体层和共电极,所述多个像素电极电连接到所述多个像素焊盘。
15.根据权利要求14所述的方法,所述方法还包括形成将所述多个像素焊盘电连接到所述多个像素电极的再分布层。
16.根据权利要求15所述的方法,其中,形成再分布层的步骤包括:
形成包括接触所述多个像素焊盘的竖直布线的第一绝缘层;
在第一绝缘层上形成第二绝缘层,第二绝缘层包括扩大了所述多个像素电极与所述多个像素焊盘的面积对应的面积的水平布线和竖直布线。
17.根据权利要求16所述的方法,其中,形成第一绝缘层的步骤包括:
在所述多个像素焊盘上形成第一绝缘层;
在第一绝缘层中形成连接到所述多个像素焊盘的通孔;
通过用金属填充第一绝缘层中的通孔来形成第一绝缘层中的竖直布线。
18.根据权利要求16所述的方法,其中,形成第二绝缘层的步骤包括:
形成连接到第一绝缘层中的竖直布线的水平布线;
在第一绝缘层和水平布线上形成第二绝缘层;
在第二绝缘层中形成通孔,第二绝缘层中的通孔连接到水平布线;
通过用金属填充第二绝缘层中的第二绝缘层中的通孔来形成第二绝缘层中的竖直布线。
19.根据权利要求14所述的方法,其中,所述印刷电路基底的结合的步骤包括:在所述无缝硅基底中的通孔上形成通路接触件之后将所述印刷电路基底结合到所述无缝硅基底的所述另一表面上。
20.根据权利要求19所述的方法,其中,所述方法还包括:在形成通路接触件之后且在结合所述印刷电路基底之前在通路接触件和所述印刷电路基底之间形成凸块,其中,所述通路接触件通过所述凸块连接到所述印刷电路基底。
21.根据权利要求20所述的方法,其中,所述印刷电路基底为与所述多个芯片区域对应的单个印刷电路基底。
22.根据权利要求14所述的方法,其中,所述印刷电路基底包括以与所述多个芯片区域中的每个一一对应的关系设置的多个印刷电路基底。
23.根据权利要求14所述的方法,其中,所述无缝硅基底为单晶硅基底。
24.根据权利要求14所述的方法,其中,所述光电导体层由从由非晶硒、HgI2、PbI2、CdTe、CdZnTe和PbO组成的组中选择的至少一种材料形成。
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