CN102544009B - High-mobility complementary metal oxide semiconductor (CMOS) integrated unit - Google Patents
High-mobility complementary metal oxide semiconductor (CMOS) integrated unit Download PDFInfo
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Abstract
The invention discloses a high-mobility complementary metal oxide semiconductor (CMOS) integrated unit, belonging to the field of semiconductor integration technology. According to the high-mobility CMOS integrated unit, a high-electron-mobility In-Ga-As n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) and a high-hole-mobility Ge p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) are integrated on a monocrystalline silicon substrate by a plane, so that integrated CMOS devices with different channel materials and excellent characteristics can be realized, and the high-mobility CMOS integrated unit has the potential of replacing the traditional silicon-based CMOS device and has practical application value in the post-Moors period. The CMOS integrated unit also can be integrated with the traditional silicon-based device and a semiconductor device of III-V compounds and the like, so that multifunctional module monolithic integration can be realized, the power consumption is reduced, and the performance is improved.
Description
Technical field
The present invention relates to semiconductor integrated technology field, relate in particular to a kind of high mobility CMOS integrated unit.
Background technology
Semiconductor technology, as core and the basis of information industry, is regarded as weighing the important symbol of a national science technological progress and overall national strength.In in the past more than 40 year, the silicon CMOS technology of take is followed Moore's Law as basic integrated circuit technique and is improved operating rate, the increase integrated level of chip and reduced costs by the characteristic size of reduction of device, and the characteristic size of integrated circuit evolves to nanoscale by micro-meter scale.But when the grid length of MOS device is reduced to after 90 nanometers, the thickness of gate oxide will be less than 1.2 nanometers, and Moore's Law starts to face the double challenge from physics and technical elements.
Academia and industrial circle generally believe: adopt high mobility channel material to substitute traditional silicon material by the important development direction that is CMOS technology, wherein Zhe Yu III-V family semiconductor channel material is most likely at and realizes in the recent period large-scale application.The high preparation PMOSFET that is applicable to of hole mobility of germanium, and the high preparation NMOSFET that is applicable to of the electron mobility of III-V family semi-conducting material, in III-V family semi-conducting material, tool application potential quality is indium gallium arsenic material, and the cmos device that indium gallium arsenic NMOSFET and germanium PMOSFET are combined becomes and solves the problem effective way that silicon base CMOS runs into.Yet indium gallium arsenic NMOSFET and germanium PMOSFET Planar integration have been become to emphasis and the difficult point of current research.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of high mobility CMOS integrated unit, with by indium gallium arsenic NMOSFET and germanium PMOSFET Planar integration on monocrystalline substrate, realize the integrated CMOS device with different channel material and excellent.
(2) technical scheme
For achieving the above object, the invention provides a kind of high mobility CMOS integrated unit, this high mobility CMOS integrated unit comprises monocrystalline substrate, resilient coating, barrier layer, P type light dope indium gallium arsenic single crystal layer, N-type heavy doping indium gallium arsenic single crystal layer, the first barrier layer, the second barrier layer, the first N-type heavy doping germanium single crystal layer, the second N-type heavy doping germanium single crystal layer, N-type light dope germanium single crystal layer, P type heavy doping germanium single crystal layer, the 3rd N-type heavy doping germanium single crystal layer, indium gallium arsenic NMOSFET gate oxide, indium gallium arsenic NMOSFET grid metal level, indium gallium arsenic NMOSFET grid side wall, extraction electrode is leaked in indium gallium arsenic NMOSFET source, isolated area, germanium PMOSFET grid passivation layer, germanium PMOSFET gate oxide, germanium PMOSFET grid metal level, extraction electrode is leaked in germanium PMOSFET grid side wall and germanium PMOSFET source, wherein to take described P type light dope indium gallium arsenic single crystal layer be raceway groove and backing material to indium gallium arsenic NMOSFET, it is raceway groove and backing material that germanium PMOSFET be take described N-type light dope germanium single crystal layer, described isolated area is isolated by described indium gallium arsenic NMOSFET and described germanium PMOSFET, described monocrystalline substrate is positioned at the bottom of described high mobility CMOS integrated unit, described resilient coating is stacked on described monocrystalline substrate, described barrier layer is stacked on described resilient coating, described P type light dope indium gallium arsenic single crystal layer is stacked on described barrier layer.
In such scheme, described resilient coating is used for filtering dislocation, discharges stress, and described resilient coating is the GaAs of low-temperature epitaxy, and its surface matches with lattice of described barrier layer material, and described buffer layer thickness is between 1 nanometer to 3 micron; Described barrier layer is the single crystalline layer of GaAs or indium gallium phosphorus, each atomicity ratio indium in indium gallium phosphorus: gallium: phosphorus=0.5: 0.5: 1, the thickness of described barrier layer was between 1 nanometer to 2 micron.
In such scheme, indium, gallium, arsenic atomicity ratio indium in described P type light dope indium gallium arsenic single crystal layer and described N-type heavy doping indium gallium arsenic single crystal layer: gallium: arsenic=x: (1-x): 1, the span of x can be set between 0 < x < 0.6, and the thickness of described P type light dope indium gallium arsenic single crystal layer is between 1 nanometer to 100 nanometer.
In such scheme, described the first barrier layer and described the second barrier layer are for suppressing the counterdiffusion doping effect between its upper and lower germanium single crystal and indium gallium arsenic single crystal, and improve described indium gallium arsenic NMOSFET gate dielectric layer and channel interface, reduce interface state density, described the first barrier layer, described P type light dope indium gallium arsenic single crystal layer and described barrier layer form superlattice quantum well simultaneously, are conducive to improve described indium gallium arsenic NMOSFET channel electron mobility, described the first barrier layer and described the second barrier layer are indium phosphide, gallium phosphide, indium aluminium phosphorus, indium gallium phosphorus, the single crystalline layer of aluminum phosphate or gallium aluminium phosphorus, each atomicity ratio indium in indium aluminium phosphorus: aluminium: phosphorus=y: (1-y): 1, the span of y can be set between 0 < y < 1, each atomicity ratio indium in indium gallium phosphorus: gallium: phosphorus=z: (1-z): 1, the span of z can be set between 0 < z < 1, each atomicity ratio indium in gallium aluminium phosphorus: gallium: phosphorus=a: (1-a): 1, the span of a is set between 0 < a < 1, described the first barrier layer and described the second barrier layer difference are that the first barrier layer is for doped single crystal layer not, and described the second barrier layer is N-type heavy doping, the thickness on described the first barrier layer and described the second barrier layer is between 3 dust to 20 nanometers.
In such scheme, the raceway groove of described indium gallium arsenic NMOSFET and substrate are described P type light dope indium gallium arsenic single crystal layer, P type light dope element is one or more of magnesium, beryllium, zinc, the grid of described indium gallium arsenic NMOSFET are followed successively by described the first barrier layer, described indium gallium arsenic NMOSFET gate oxide and described indium gallium arsenic NMOSFET grid metal level from bottom to up, and both sides are indium gallium arsenic NMOSFET grid side walls, described the first barrier layer is on described P type light dope indium gallium arsenic single crystal layer, the oxide that described indium gallium arsenic NMOSFET gate oxide is high-k, these oxides comprise aluminium base, zirconium base, hafnium base, gadolinium base, gallium base, lanthanum base, tantalum base oxide, doped chemical in oxide can be aluminium, zirconium, hafnium, gadolinium, gallium, lanthanum, tantalum, nitrogen, phosphorus, ratio=the m of the atomic quantity of the atomic quantity of doped chemical and total metallic element in oxide: (1-m), the span of m can be set to 0≤m < 1, the thickness of described indium gallium arsenic NMOSFET gate oxide is between 3 dust to 100 nanometers, one deck or above various metals material layer multiple layer combination that described indium gallium arsenic NMOSFET grid metal level is tantalum nitride, titanium nitride, gold, titanium, nickel, platinum or aluminium form, and described indium gallium arsenic NMOSFET grid side wall is silicon dioxide, silicon nitride or nitrogen-oxygen-silicon.
In such scheme, the source of described indium gallium arsenic NMOSFET and leakage are followed successively by described N-type heavy doping indium gallium arsenic single crystal layer from bottom to up, described the second barrier layer, described the second N-type heavy doping germanium single crystal layer, described the 3rd N-type heavy doping germanium single crystal layer and described indium gallium arsenic NMOSFET source are leaked extraction electrode and are formed, wherein said N-type heavy doping indium gallium arsenic single crystal layer, described the second barrier layer is identical with the doping content of described the 3rd N-type heavy doping germanium single crystal layer, the doping content of described the second N-type heavy doping germanium single crystal layer is the doping content sum of above-mentioned N-type heavy doping indium gallium arsenic single crystal layer doping content and described the first N-type heavy doping germanium single crystal layer, and heavy doping element is nitrogen, phosphorus, sulphur, selenium, one or more of tellurium, it is nickel that extraction electrode is leaked in described indium gallium arsenic NMOSFET source, gold, nisiloy, palladium, titanium, copper, platinum, zinc, one or more layers metallization of cadmium forms, and the thickness of described N-type heavy doping indium gallium arsenic single crystal layer is between 3 dust to 50 nanometers, and upper surface and described P type light dope indium gallium arsenic single crystal layer are in same level.
In such scheme, described the first N-type heavy doping germanium single crystal layer is identical with the thickness of described the second N-type heavy doping germanium single crystal layer, between 3 dust-50 nanometers; Described N-type light dope germanium single crystal layer is identical with the thickness of described the 3rd N-type heavy doping germanium single crystal layer, and between 1 nanometer-200 nanometer, the thickness of P type heavy doping germanium single crystal layer is less than the thickness of described N-type light dope germanium single crystal layer.
In such scheme, it is N-type light dope raceway groove and backing material that described germanium PMOSFET be take described N-type light dope germanium single crystal layer, and doped chemical can be one or more of nitrogen phosphate and sulfur, selenium, tellurium.The grid of described germanium PMOSFET are followed successively by described germanium PMOSFET grid passivation layer from bottom to up, described germanium PMOSFET gate oxide and described germanium PMOSFET grid metal level, both sides are described germanium PMOSFET grid side wall, described germanium PMOSFET grid passivation layer can be silicon, germanium oxynitride, silica, aluminium nitride, alumina nitrogen, the channel interface of germanium PMOSFET, reduces interface state density described in passivation, and thickness is between 3 dust-50 nanometers, and described germanium PMOSFET gate oxide can be the oxide of high-k, comprises aluminium base, zirconium base, hafnium base, gadolinium base, gallium base, lanthanum base, tantalum base oxide, the doped chemical in oxide can be aluminium, zirconium, hafnium, gadolinium, gallium, lanthanum, tantalum, nitrogen, phosphorus, ratio=the n of the atomic quantity of the atomic quantity of doped chemical and total metallic element in oxide: (1-n), the span of n can be set to 0≤n < 1, the thickness of described germanium PMOSFET gate oxide is between 3 dust-100 nanometers, and described germanium PMOSFET grid metal level can be tantalum nitride, titanium nitride, gold, titanium, nickel, one deck of platinum or aluminium or above various metals material layer multilevel metallization form, and described germanium PMOSFET grid side wall can be silicon dioxide, silicon nitride or nitrogen-oxygen-silicon.
In such scheme, the source of described germanium PMOSFET is leaked and by described P type heavy doping germanium single crystal layer and described germanium PMOSFET source, is leaked extraction electrode and form, and the doped chemical in described P type heavy doping germanium single crystal layer can be one or more of boron, magnesium, beryllium, aluminium, gallium, zinc; Extraction electrode and described indium gallium arsenic NMOSFET source are leaked in described germanium PMOSFET source, and to leak extraction electrode identical, can be that one or more layers metallization of nickel, gold, silicon, palladium, titanium, copper, platinum, zinc, cadmium is drawn and formed.
In such scheme, in described high mobility CMOS integrated unit, indium gallium arsenic NMOSFET and germanium PMOSFET are kept apart by isolated area.Described isolated area can be silicon dioxide, silicon nitride or nitrogen-oxygen-silicon, and the degree of depth of described isolated area is greater than the thickness sum of described P type light dope indium gallium arsenic single crystal layer, described the first barrier layer, described the first N-type heavy doping germanium single crystal layer and described N-type light dope germanium single crystal layer.
In such scheme, described indium gallium arsenic NMOSFET and described germanium PMOSFET are integrated in monocrystalline substrate, and described indium gallium arsenic NMOSFET and the source of germanium PMOSFET and the upper surface of leakage are in same plane.
In such scheme, the source of described indium gallium arsenic NMOSFET and leakage upper surface are higher than indium gallium arsenic raceway groove upper surface, have source and leak the effect promoting, source and leakage consist of described N-type heavy doping indium gallium arsenic single crystal layer, described the second barrier layer, described the second N-type heavy doping germanium single crystal layer and described the 3rd N-type heavy doping germanium single crystal layer from bottom to up successively.
In such scheme, it is all germanium single crystal layer that upper surface is leaked in the source of described indium gallium arsenic NMOSFET and described germanium PMOSFET, can adopt metal of the same race to metallize and draw, and can realize the metallic electrode leaking in indium gallium arsenic NMOSFET and germanium PMOSFET source simultaneously and draw.
In such scheme, described the first N-type heavy doping germanium single crystal layer is between described barrier layer and described N-type light dope germanium single crystal layer, in order to prevent that source leakage, the first barrier layer, the P type light dope indium gallium arsenic single crystal layer of germanium PMOSFET from communicating, form path and cause component failure, the thickness of described the first N-type heavy doping germanium single crystal layer is between 3 dust to 50 nanometers.
In such scheme, described the first barrier layer, described P type light dope indium gallium arsenic single crystal layer and described barrier layer form superlattice quantum well, charge carrier is confined to described P type light dope indium gallium arsenic single crystal layer channel surface, reduces scattering, improve described indium gallium arsenic NMOSFET channel electron mobility.
(3) beneficial effect
From technique scheme, can find out, the present invention has following beneficial effect:
This high mobility CMOS integrated unit provided by the invention, the source region of indium gallium arsenic NMOSFET and drain region and raceway groove, not in same level, have the effect that lifting is leaked in source, are conducive to reduce the source-drain series resistance of NMOSFET, improve the characteristic of indium gallium arsenic NMOSFET.The upper surface that leak in the source of indium gallium arsenic NMOSFET and germanium PMOSFET is in same plane, and indium gallium arsenic NMOSFET and germanium PMOSFET are Planar integration, are conducive to the expansion of CMOS integrated technology subsequent technique.It is all germanium single crystal that upper surface is drawn in the source leakage of indium gallium arsenic NMOSFET and germanium PMOSFET, can adopt metallization of the same race and metal of the same race to draw, can realize the metallization and the electrode that leak in indium gallium arsenic NMOSFET and germanium PMOSFET source simultaneously and draw, reduce processing step, reduce costs.The gate medium of indium gallium arsenic NMOSFET is comprised of barrier layer and gate oxide lamination, with directly gate oxide growth is compared in channel material, there is the gate medium on barrier layer can effectively reduce the channel interface density of states, and barrier layer, P type light dope indium gallium arsenic single crystal layer, barrier layer can form superlattice quantum well, reduce channel electrons scattering, improve electron mobility.And indium gallium arsenic NMOSFET and germanium PMOSFET be integrated on monocrystalline substrate and III-V family semi-conducting material, this device can integrate with traditional silicon base device and III-V family device, realizes many device blocks monolithic integrated, reduces power consumption, improves performance.
Accompanying drawing explanation
Fig. 1 is the structural representation of high mobility CMOS integrated unit provided by the present invention; Wherein, 1 is monocrystalline substrate; 2 is resilient coating; 3 is barrier layer; 4a is P type light dope indium gallium arsenic single crystal layer; 4b is N-type heavy doping indium gallium arsenic single crystal layer; 5a is the first barrier layer; 5b is the second barrier layer; 6a is the first N-type heavy doping germanium single crystal layer; 6b is the second N-type heavy doping germanium single crystal layer; 6c is N-type light dope germanium single crystal layer; 6d is P type heavy doping germanium single crystal layer; 6e is the 3rd N-type heavy doping germanium single crystal layer; 7 is indium gallium arsenic NMOSFET gate oxide; 8 is indium gallium arsenic NMOSFET grid metal levels; 9 is indium gallium arsenic NMOSFET grid side walls; 10 is that extraction electrode is leaked in indium gallium arsenic NMOSFET source; 11 is isolated area; 12 is germanium PMOSFET grid passivation layers; 13 is germanium PMOSFET gate oxide; 14 is germanium PMOSFET grid metal levels; 15 is germanium PMOSFET grid side walls; 16 is that extraction electrode is leaked in germanium PMOSFET source.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present embodiment specifically describes a kind of high mobility CMOS integrated unit provided by the present invention.
As shown in Figure 1, high mobility CMOS integrated unit provided by the present invention, described high mobility CMOS integrated unit comprises monocrystalline substrate 1, resilient coating 2, barrier layer 3, P type light dope indium gallium arsenic single crystal layer 4a, N-type heavy doping indium gallium arsenic single crystal layer 4b, the first barrier layer 5a, the second barrier layer 5b, the first N-type heavy doping germanium single crystal layer 6a, the second N-type heavy doping germanium single crystal layer 6b, N-type light dope germanium single crystal layer 6c, P type heavy doping germanium single crystal layer 6d, the 3rd N-type heavy doping germanium single crystal layer 6e, indium gallium arsenic NMOSFET gate oxide 7, indium gallium arsenic NMOSFET grid metal level 8, indium gallium arsenic NMOSFET grid side wall 9, extraction electrode 10 is leaked in indium gallium arsenic NMOSFET source, isolated area 11, germanium PMOSFET grid passivation layer 12, germanium PMOSFET gate oxide 13, germanium PMOSFET grid metal level 14, extraction electrode 16 is leaked in germanium PMOSFET grid side wall 15 and germanium PMOSFET source.
As shown in Figure 1, described monocrystalline substrate 1 is positioned at the bottom of described high mobility CMOS integrated unit; Described resilient coating 2 is stacked in described monocrystalline substrate 1; Described barrier layer 3 is stacked on described resilient coating 2; Described P type light dope indium gallium arsenic single crystal layer 4a is stacked on described barrier layer 3.
As shown in Figure 1, the effect of described resilient coating 2 is that filter bit is wrong, discharges stress, and described resilient coating can be the GaAs of low-temperature epitaxy, and its surface matches with the lattice of barrier layer material, and described buffer layer thickness is 1 micron; Described barrier layer 3 can be GaAs, and the thickness of described barrier layer 3 is 1.5 microns;
As Fig. 1, in described high mobility CMOS integrated unit, the raceway groove of indium gallium arsenic NMOSFET and substrate are described P type light dope indium gallium arsenic single crystal layer 4a, and doped chemical is beryllium, and doping content is 5*10
17cm
-3in described high mobility CMOS integrated unit, the grid of indium gallium arsenic NMOSFET are followed successively by described the first barrier layer 5a, described indium gallium arsenic NMOSFET gate oxide 7 and described indium gallium arsenic NMOSFET grid metal level 8 from bottom to up, both sides are described indium gallium arsenic NMOSFET grid side wall 9, described the first barrier layer 5a is on described P type light dope indium gallium arsenic single crystal layer 4a, described indium gallium arsenic NMOSFET gate oxide 7 is aluminium oxide, and the thickness of described alumina layer is 10 nanometers; Described indium gallium arsenic NMOSFET grid metal level 8 is tantalum nitride, and described indium gallium arsenic NMOSFET grid side wall 9 is silicon dioxide.
As shown in Figure 1, in described high mobility CMOS integrated unit, the source of indium gallium arsenic NMOSFET and leakage are followed successively by described N-type heavy doping indium gallium arsenic single crystal layer 4b, described the second barrier layer 5b, described the second N-type heavy doping germanium single crystal layer 6b, described the 3rd N-type heavy doping germanium single crystal layer 6e and described indium gallium arsenic NMOSFET source leakage extraction electrode 10 compositions from bottom to up, the doping content of wherein said N-type heavy doping indium gallium arsenic single crystal layer 4b, described the second barrier layer 5b and described the 3rd N-type heavy doping germanium single crystal layer 6e is basic identical, doped chemical is sulphur, and doping content is 5*10
19cm
-3, the doping content of described the second N-type heavy doping germanium single crystal layer 6b is 1*10
20cm
-3, doped chemical p and s respectively accounts for half; It is nickel that extraction electrode 10 is leaked in described indium gallium arsenic NMOSFET source, and in metallization processes, nickel reacts with germanium and generates germanium nickel, forms ohmic contact; The thickness of described N-type heavy doping indium gallium arsenic single crystal layer 4b is 20 nanometers, and the upper surface of described N-type heavy doping indium gallium arsenic single crystal layer 4b and described P type light dope indium gallium arsenic single crystal layer 4a are in same level.
As shown in Figure 1, indium, gallium, arsenic atomicity ratio indium in described P type light dope indium gallium arsenic single crystal layer 4a and described N-type heavy doping indium gallium arsenic single crystal layer 4b: gallium: arsenic=0.1: 0.9: 1, the thickness of described P type light dope indium gallium arsenic single crystal layer 4a was 60 nanometers; Described the first barrier layer 5a and described the second barrier layer 5b are indium gallium phosphorus single crystalline layer, each atomicity ratio indium in gallium aluminium phosphorus: gallium: phosphorus=0.5: 0.5: 1, described the first barrier layer 5a and described the second barrier layer 5b difference are that the first barrier layer 5a is for not doping, and described the second barrier layer 5b is N-type heavy doping, the thickness of described the first barrier layer 5a and described the second barrier layer 5b is 3 nanometers; Described the first N-type heavy doping germanium single crystal layer 6a is all 20 nanometers mutually with the thickness of described the second N-type heavy doping germanium single crystal layer 6b, and the doped chemical of described the first N-type heavy doping germanium single crystal layer 6a is phosphorus, and doping content is 5*10
19cm
-3; Described N-type light dope germanium single crystal layer 6c is all 60 nanometers mutually with the thickness of described the 3rd N-type heavy doping germanium single crystal layer 6e.
As shown in Figure 1, in described high mobility CMOS integrated unit, to take described N-type light dope germanium single crystal layer 6c be raceway groove and backing material to germanium PMOSFET, and doped chemical is phosphorus, and doping content is 5*10
17cm
-3.The grid of described germanium PMOSFET are followed successively by described germanium PMOSFET grid passivation layer 12, described germanium PMOSFET gate oxide 13 and described germanium PMOSFET grid metal level 14 from bottom to up, and both sides are described germanium PMOSFET grid side wall 15; Described germanium PMOSFET grid passivation layer 12 is germanium oxynitride, and thickness is 2 nanometers; Described germanium PMOSFET gate oxide 13 can be aluminium oxide, and the thickness of described germanium PMOSFET gate oxide 13 is 10 nanometers; Described germanium PMOSFET grid metal level 14 is titanium nitride; Described germanium PMOSFET grid side wall 15 is silicon dioxide.
As shown in Figure 1, in described high mobility CMOS integrated unit, the source of germanium PMOSFET and leakage are comprised of described P type heavy doping germanium single crystal layer 6d and described germanium PMOSFET source leakage extraction electrode 16, doped chemical in described P type heavy doping germanium single crystal layer 6d is boron, and doping content is 5*10
19cm
-3, it is identical also nickel with described indium gallium arsenic NMOSFET source leakage extraction electrode 10 that extraction electrode 16 is leaked in described germanium PMOSFET source, in preparation process, nickel and germanium interfacial reaction generate germanium nickel, form ohmic contact.
As shown in Figure 1, described in described high mobility CMOS integrated unit, indium gallium arsenic NMOSFET and described germanium PMOSFET are kept apart by isolated area 11.Described isolated area 11 is silicon dioxide, and the degree of depth of described isolated area is 200 nanometers.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. a high mobility CMOS integrated unit, it is characterized in that, this high mobility CMOS integrated unit comprises monocrystalline substrate, resilient coating, barrier layer, P type light dope indium gallium arsenic single crystal layer, N-type heavy doping indium gallium arsenic single crystal layer, the first barrier layer, the second barrier layer, the first N-type heavy doping germanium single crystal layer, the second N-type heavy doping germanium single crystal layer, N-type light dope germanium single crystal layer, P type heavy doping germanium single crystal layer, the 3rd N-type heavy doping germanium single crystal layer, indium gallium arsenic NMOSFET gate oxide, indium gallium arsenic NMOSFET grid metal level, indium gallium arsenic NMOSFET grid side wall, extraction electrode is leaked in indium gallium arsenic NMOSFET source, isolated area, germanium PMOSFET grid passivation layer, germanium PMOSFET gate oxide, germanium PMOSFET grid metal level, extraction electrode is leaked in germanium PMOSFET grid side wall and germanium PMOSFET source, wherein to take described P type light dope indium gallium arsenic single crystal layer be raceway groove and backing material to indium gallium arsenic NMOSFET, it is raceway groove and backing material that germanium PMOSFET be take described N-type light dope germanium single crystal layer, described isolated area is isolated by described indium gallium arsenic NMOSFET and described germanium PMOSFET, described monocrystalline substrate is positioned at the bottom of described high mobility CMOS integrated unit, described resilient coating is stacked on described monocrystalline substrate, described barrier layer is stacked on described resilient coating, described P type light dope indium gallium arsenic single crystal layer is stacked on described barrier layer,
Wherein, described monocrystalline substrate is positioned at the bottom of described high mobility CMOS integrated unit; Described resilient coating is stacked in described monocrystalline substrate; Described barrier layer is stacked on described resilient coating; Described P type light dope indium gallium arsenic single crystal layer is stacked on described barrier layer; Described isolated area is stacked on described barrier layer, and described isolated area is isolated into NMOSFET and PMOSFET two parts by described high mobility CMOS integrated unit part more than described barrier layer, described NMOSFET on the left side, and described PMOSFET is on the right;
Described NMOSFET leaks extraction electrode by the left-hand component of described P type light dope indium gallium arsenic single crystal layer, described N-type heavy doping indium gallium arsenic single crystal layer, the left-hand component on described the first barrier layer, described the second barrier layer, described the second N-type heavy doping germanium single crystal layer, described the 3rd N-type heavy doping germanium single crystal layer, described indium gallium arsenic NMOSFET gate oxide, described indium gallium arsenic NMOSFET grid metal level, described indium gallium arsenic NMOSFET grid side wall and described indium gallium arsenic NMOSFET source and forms; Described N-type heavy doping indium gallium arsenic single crystal layer is stacked on the both sides of left-hand component of described P type light dope indium gallium arsenic single crystal layer; The left-hand component on described the first barrier layer is stacked on the centre of left-hand component of described P type light dope indium gallium arsenic single crystal layer; Described the second barrier layer is in the both sides of the left-hand component on described the first barrier layer; Described the second barrier layer is stacked on described N-type heavy doping indium gallium arsenic single crystal layer; Described the second N-type heavy doping germanium single crystal layer is stacked on described the second barrier layer; Described the 3rd N-type heavy doping germanium single crystal layer is on described the second N-type heavy doping germanium single crystal layer; Described indium gallium arsenic NMOSFET gate oxide is stacked on the left-hand component on described the first barrier layer; Described indium gallium arsenic NMOSFET grid metal level is stacked on described indium gallium arsenic NMOSFET gate oxide; Described indium gallium arsenic NMOSFET grid side wall is stacked on the both sides of left-hand component on described the first barrier layer; Described indium gallium arsenic NMOSFET grid side wall is in the both sides of described indium gallium arsenic NMOSFET grid metal level and described indium gallium arsenic NMOSFET gate oxide lamination; The both sides of described the second N-type heavy doping germanium single crystal layer and described the 3rd N-type heavy doping germanium single crystal layer laminate are respectively described isolated area and described indium gallium arsenic NMOSFET grid side wall;
Described PMOSFET by the right-hand component of described P type light dope indium gallium arsenic single crystal layer, extraction electrode is leaked in the right-hand component on described the first barrier layer, described the first N-type heavy doping germanium single crystal layer, described N-type light dope germanium single crystal layer, described P type heavy doping germanium single crystal layer, described germanium PMOSFET grid passivation layer, described germanium PMOSFET gate oxide, described germanium PMOSFET grid metal level, described germanium PMOSFET grid side wall and described germanium PMOSFET source forms; The right-hand component on described the first barrier layer is stacked on the right-hand component of described P type light dope indium gallium arsenic single crystal layer; Described the first N-type heavy doping germanium single crystal layer is stacked on the right-hand component on described the first barrier layer; Described N-type light dope germanium single crystal layer is stacked on described the first N-type heavy doping germanium single crystal layer; Described P type heavy doping germanium single crystal layer is stacked on the both sides of described N-type light dope germanium single crystal layer; Described germanium PMOSFET grid passivation layer is stacked on the centre of described N-type light dope germanium single crystal layer; Described germanium PMOSFET gate oxide is stacked on described germanium PMOSFET grid passivation layer; Described germanium PMOSFET grid metal level is stacked on described germanium PMOSFET gate oxide; Described germanium PMOSFET grid side wall is in the both sides of described germanium PMOSFET grid passivation layer, described germanium PMOSFET gate oxide, described germanium PMOSFET grid metal level lamination; Described germanium PMOSFET grid side wall is stacked on described P type heavy doping germanium single crystal layer; Described germanium PMOSFET source is leaked extraction electrode and is stacked on described P type heavy doping germanium single crystal layer.
2. high mobility CMOS integrated unit according to claim 1, it is characterized in that, described resilient coating is used for filtering dislocation, discharge stress, described resilient coating is the GaAs of low-temperature epitaxy, its surface matches with lattice of described barrier layer material, and described buffer layer thickness is between 1 nanometer to 3 micron; Described barrier layer is the single crystalline layer of GaAs or indium gallium phosphorus, each atomicity ratio indium in indium gallium phosphorus: gallium: phosphorus=0.5:0.5:1, the thickness of described barrier layer is between 1 nanometer to 2 micron.
3. high mobility CMOS integrated unit according to claim 1, it is characterized in that, described the first barrier layer and described the second barrier layer for suppressing the counterdiffusion doping effect between its upper and lower germanium single crystal and indium gallium arsenic single crystal, and improve described indium gallium arsenic NMOSFET gate dielectric layer and channel interface, reduce interface state density, described the first barrier layer, described P type light dope indium gallium arsenic single crystal layer and described barrier layer form superlattice quantum well simultaneously, are conducive to improve described indium gallium arsenic NMOSFET channel electron mobility, described the first barrier layer and described the second barrier layer are indium phosphide, gallium phosphide, indium aluminium phosphorus, indium gallium phosphorus, the single crystalline layer of aluminum phosphate or gallium aluminium phosphorus, each atomicity ratio indium in indium aluminium phosphorus: aluminium: phosphorus=y:(1-y): 1, the span of y can be set between 0<y<1, each atomicity ratio indium in indium gallium phosphorus: gallium: phosphorus=z:(1-z): 1, the span of z can be set between 0<z<1, each atomicity ratio indium in gallium aluminium phosphorus: gallium: phosphorus=a:(1-a): 1, the span of a is set between 0<a<1, described the first barrier layer and described the second barrier layer difference are that the first barrier layer is for doped single crystal layer not, and described the second barrier layer is N-type heavy doping, the thickness on described the first barrier layer and described the second barrier layer is between 3 dust to 20 nanometers.
4. high mobility CMOS integrated unit according to claim 1, it is characterized in that, the source of described indium gallium arsenic NMOSFET and leakage upper surface are higher than indium gallium arsenic raceway groove upper surface, have source and leak the effect promoting, the source of described indium gallium arsenic NMOSFET and leakage are followed successively by from bottom to up described N-type heavy doping indium gallium arsenic single crystal layer, described the second barrier layer, described the second N-type heavy doping germanium single crystal layer, described the 3rd N-type heavy doping germanium single crystal layer and described indium gallium arsenic NMOSFET source leakage extraction electrode and form.
5. high mobility CMOS integrated unit according to claim 1, it is characterized in that, described indium gallium arsenic NMOSFET and described germanium PMOSFET are integrated in monocrystalline substrate, and described indium gallium arsenic NMOSFET and the source of germanium PMOSFET and the upper surface of leakage are in same plane.
6. high mobility CMOS integrated unit according to claim 1, it is characterized in that, it is all germanium single crystal layer that upper surface is leaked in the source of described indium gallium arsenic NMOSFET and described germanium PMOSFET, can adopt metal of the same race to metallize and draw, can realize the metallic electrode leaking in indium gallium arsenic NMOSFET and germanium PMOSFET source simultaneously and draw.
7. high mobility CMOS integrated unit according to claim 1, it is characterized in that, described the first N-type heavy doping germanium single crystal layer is between described barrier layer and described N-type light dope germanium single crystal layer, in order to prevent that source leakage, the first barrier layer, the P type light dope indium gallium arsenic single crystal layer of germanium PMOSFET from communicating, form path and cause component failure, the thickness of described the first N-type heavy doping germanium single crystal layer is between 3 dust to 50 nanometers.
8. high mobility CMOS integrated unit according to claim 1, it is characterized in that, the degree of depth of described isolated area is greater than the thickness sum of described P type light dope indium gallium arsenic single crystal layer, described the first barrier layer, described the first N-type heavy doping germanium single crystal layer and described N-type light dope germanium single crystal layer.
9. high mobility CMOS integrated unit according to claim 1, it is characterized in that, described the first barrier layer, described P type light dope indium gallium arsenic single crystal layer and described barrier layer form superlattice quantum well, charge carrier is confined to described P type light dope indium gallium arsenic single crystal layer channel surface, reduce scattering, improve described indium gallium arsenic NMOSFET channel electron mobility.
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