CN102543907B - Package and manufacture method for thermal enhanced quad flat no-lead flip chip - Google Patents
Package and manufacture method for thermal enhanced quad flat no-lead flip chip Download PDFInfo
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- CN102543907B CN102543907B CN201110460400.7A CN201110460400A CN102543907B CN 102543907 B CN102543907 B CN 102543907B CN 201110460400 A CN201110460400 A CN 201110460400A CN 102543907 B CN102543907 B CN 102543907B
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Abstract
The invention discloses a packaging and manufacturing method for a thermal enhanced quad flat no-lead flip chip. A thermal enhanced quad flat no-lead flip chip package piece structure comprises a lead framework, a first metal material layer, a second metal material layer, IC chips with convex points, an insulating filler material, a sticking material, radiating fins, heat conducting spacers and a plastic package material, wherein the lead framework comprises a chip carrier and a plurality of pins arranged in multiple circles around the chip carrier; the first metal material layer and the second metal material layer are respectively configured on the upper surface and the lower surface of the lead framework; the IC chips with the convex points are invertedly welded and configured at the position of the first metal material on the upper surface of the lead framework; the insulating filler material is configured below the stepped structure of the lead framework; the heat conducting spacers are configured between the IC chips and the chip carrier through the sticking material; and the radiating fins are configured on the edgeless surfaces of the IC chips through the sticking material and wrapped by the plastic package material to form a package piece. The QFN (Quad Flat No-lead) package piece structure provided by the invention has the advantages of high reliability, low cost and high I/O (Input/Output) density.
Description
Technical field
The present invention relates to semiconductor components and devices manufacturing technology field, refer more particularly to and there is thermal-enhanced multi-circle pin and arrange four limit flat non-pin Flip-Chip Using (Flip Chip Quad Flat Non-lead Package, FCQFN), the present invention also comprises the manufacture method of this packaging part.
Background technology
Along with electronic product is if mobile phone, notebook computer etc. are towards miniaturization, portable, ultrathin, multimedization and meet popular needed low-cost future development, high density, high-performance, high reliability and cheaply packing forms and packaging technology thereof have obtained development fast.Compare with packing forms such as expensive BGA, fast-developing novel encapsulated technology in recent years, i.e. four limit flat non-pin QFN (Quad Flat Non-lead Package) encapsulation, owing to thering is good hot property and electrical property, size is little, cost is low and the many merits such as high production rate, has caused a new revolution in microelectronic packaging technology field.
Figure 1A and Figure 1B are respectively schematic rear view and the edge of traditional Q FN encapsulating structure
the generalized section of section, this QFN encapsulating structure comprises lead frame 11, capsulation material 12, bonding die material 13, IC chip 14, plain conductor 15, wherein lead frame 11 comprises chip carrier 111 and the pin 112 of arranging around chip carrier 111 surroundings, IC chip 14 is fixed on chip carrier 111 by bonding die material 13, IC chip 13 is realized electrical connection with the pin 112 that surrounding is arranged by plain conductor 15, 12 pairs of IC chips 14 of capsulation material, plain conductor 15 and lead frame 11 are sealed the effect that reaches protection and support, the exposed bottom surface at capsulation material 12 of pin 112, by scolder, be welded on the circuit boards such as PCB to realize and extraneous electrical connection.The exposed chip carrier 111 in bottom surface is welded on by scolder on the circuit boards such as PCB, has direct heat dissipation channel, can effectively discharge the heat that IC chip 14 produces.Encapsulate and compare with SOIC with traditional TSOP, QFN encapsulation does not have gull wing lead-in wire, and conductive path is short, and coefficient of self-inductance and impedance are low, thereby good electrical property can be provided, and can meet at a high speed or the application of microwave.Exposed chip carrier provides remarkable heat dispersion.
Along with the raising of IC integrated level and the continuous enhancing of function, the I/O number of IC increases thereupon, the also corresponding increase of I/O number of pins of corresponding Electronic Packaging, but four traditional limit flat leadless package parts, the pin of individual pen is periphery around chip carrier and arranges, limited the raising of I/O quantity, can not meet high density, the needs with the IC of more I/O numbers, and owing to thering is the existence of the plain conductor of certain length, can cause the delay of signal transmission and crosstalk, also may cause breasting the tape, the defective workmanships such as silk of collapsing, the bank with certain altitude has limited reducing of packaging body thickness.Along with reducing of package body sizes, the power of chip is increasing simultaneously, cause the density of heat flow rate in packaging body day by day to improve, therefore need to select low thermal resistance material, heat-conducting glue or fin etc. effectively to derive the heat of package interior, remain potted temperature in allowed limits, thereby improve the reliability of packaging body.Traditional lead frame designs without staircase structural model, cannot effectively pin plastic material, cause lead frame and capsulation material bond strength low, the layering that is easy to cause lead frame and capsulation material is coming off of pin or chip carrier even, and cannot effectively stop moisture to be diffused into Electronic Packaging inside along lead frame and capsulation material combination interface, thereby had a strong impact on the reliability of packaging body.Traditional Q FN product needs in advance at lead frame back side Continuous pressing device for stereo-pattern, to prevent flash phenomenon, also to need to remove the cleanings such as adhesive tape, plastic packaging material overlap after plastic packaging when plastic package process, has increased packaging cost and has increased.Use four traditional limit flat leadless package parts of cutter cutting and separating, cutter also can cut to lead frame metal in cutting capsulation material, not only can cause reduction and the shortening in cutting blade life-span of cutting efficiency, and can produce metallic bur power, affected the reliability of packaging body.Therefore, in order to break through the bottleneck of the low I/O quantity of traditional Q FN, improve the reliability of packaging body and reduce packaging cost, being badly in need of QFN encapsulation and the manufacture method thereof of a kind of high reliability of research and development, low cost, high I/O density.
Summary of the invention
The invention provides a kind of high density, thermal-enhanced multi-circle pin is arranged four limit flat non-pin Flip-Chip Using (Flip Chip Quad Flat Non-lead Package, FCQFN) and manufacture method, to reach the bottleneck of the low I/O quantity that breaks through traditional Q FN and to improve the object of the reliability of packaging body.
To achieve these goals, the present invention adopts following technical proposals:
The present invention proposes a kind of thermal-enhanced multi-circle pin and arranges four limit flat non-pin flip chip encapsulating piece structures, comprises lead frame, the first metal material layer, the second metal material layer, the IC chip with salient point, insulation filling material, adhesive material, heat conduction partition, fin and capsulation material.Lead frame through-thickness has staircase structural model, has upper surface, lower surface and ledge surface.Lead frame comprises chip carrier and a plurality of pin that is multi-turn arrangement around chip carrier.Chip carrier is disposed at lead frame central part, and chip carrier four edge, limit through-thickness have staircase structural model.The shape of cross section that is the pin that multi-turn arranges around chip carrier is rounded or rectangular-shaped, and wherein each pin comprises the interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface.The first metal material layer and the second metal material layer are disposed at respectively upper surface position and the lower surface position of lead frame.The IC chip face-down bonding with salient point is disposed at the first metal material layer position of lead frame upper surface.Insulation filling material is disposed under the staircase structural model of lead frame, supports, protects lead frame.Heat conduction partition is disposed at IC chip by adhesive material and has chance with between face and chip carrier.Salient point on IC chip is connected with lead frame by Reflow Soldering or thermocompression bonding, to realize electrical interconnection.Fin is disposed at IC chip by adhesive material and has no chance on face, by capsulation material, is coated and is formed packaging part.
According to embodiments of the invention, nead frame has a plurality of pins that are three circles arrangements around chip carrier.
According to embodiments of the invention, comprise chip carrier and there is staircase structural model around the lead frame that chip carrier is the pin that three circles arrange.
According to embodiments of the invention, around chip carrier, be the rounded shape of shape of cross section of the pin of three circles arrangements.
According to embodiments of the invention, around chip carrier, be the shape of cross section rectangular shaped of the pin of three circles arrangements.
According to embodiments of the invention, the pin arrangements mode on the every limit of chip carrier is for being arranged in parallel.
According to embodiments of the invention, the pin arrangements mode on the every limit of chip carrier is for being staggered.
According to embodiments of the invention, lead frame upper surface and lower surface dispose respectively the first metal material layer and the second metal material layer.
According to embodiments of the invention, the first metal material layer that lead frame upper surface and lower surface configure respectively and the second metal material layer comprise nickel (Ni), palladium (Pd), gold (Au) metal material.
According to embodiments of the invention, by core equipment in upside-down mounting, the IC chip face-down bonding with salient point is disposed to the first metal material layer position of lead frame upper surface, the salient point on IC chip is connected with lead frame by Reflow Soldering or thermocompression bonding.
According to embodiments of the invention, the adhesive material by heat conduction is disposed at IC chip by heat conduction partition and has chance with between face and chip carrier.
According to embodiments of the invention, on IC chip, salient point is that three circles are arranged and face battle array is arranged.
According to embodiments of the invention, on IC chip, salient point is lead-free solder salient point, solder containing pb salient point or metal salient point.
According to embodiments of the invention, heat conduction separator material kind is the metal material that copper, aluminium etc. have good heat conductive performance.According to embodiments of the invention, under lead frame staircase structural model, configure insulation filling material.
According to embodiments of the invention, under lead frame staircase structural model, configuring insulation filling material kind is thermosetting capsulation material, or the material such as plug socket resin, ink and welding resistance green oil.
According to embodiments of the invention, fin arrangement has no chance on face in IC chip.
According to embodiments of the invention, fin material kind is the metal material that copper, aluminium etc. have good heat conductive performance.
According to embodiments of the invention, expose IC chip and have no chance face.
The present invention proposes a kind of thermal-enhanced multi-circle pin and arranges four limit flat non-pin flip chip encapsulating piece (FCQFN) manufacture methods, comprises the following steps:
Step 1: configuration mask material layer
Thin plate base material is cleaned and preliminary treatment, in the upper surface of thin plate base material and lower surface configuration, there is the mask material layer pattern of window.
Step 2: configure the first metal material layer and the second metal material layer
In the window of mask material layer that is disposed at thin plate base material upper surface and lower surface, configure respectively the first metal material layer and the second metal material layer.
Step 3: lower surface selectivity is partially-etched
Remove the mask material layer of thin plate base material lower surface, take the second metal material layer as resist layer, thin plate base material lower surface is carried out to selectivity partially-etched, form groove.
Step 4: configuration insulation filling material
In thin plate base material bottom lease making selectivity, etch partially fill insulant in the groove of formation.
Step 5: upper surface selectivity is partially-etched
Remove the mask material layer of thin plate base material upper surface, take the first metal material layer as corrosion preventing layer, thin plate base material upper surface is carried out to selectivity partially-etched, form the lead frame with staircase structural model, comprise separated chip carrier and multi-circle pin.
Step 6A: configuration heat conduction partition (optional)
Adhesive material by heat conduction is disposed at heat conduction partition on the first metal material layer of chip carrier.
Step 6B: configuration has the IC chip of salient point
By core equipment in upside-down mounting, the IC chip face-down bonding with salient point is disposed to the first metal material layer position of lead frame upper surface, the salient point on IC chip is connected with lead frame.
Step 7: configuration fin (optional)
Adhesive material by heat conduction by fin arrangement on the face for no reason at all of IC chip.
Step 8: plastic packaging
By capsulation material, be coated and form packaging part product array.
Step 9: print
Product array after plastic packaging is carried out to laser printing.
Step 10: cutting and separating product
Cutting and separating product, forms independently single package.
According to embodiments of the invention, by plating or chemical plating method, configure the first metal material layer and the second metal material layer.
According to embodiments of the invention, take the first metal material layer and the second metal material layer is resist layer, partially-etched to thin plate base material upper surface and lower surface selectivity.
According to embodiments of the invention, insulation filling material is configured in and is etched partially in groove by methods such as silk screen printing or coatings.
According to embodiments of the invention, the salient point on IC chip is connected with interior pin, the chip carrier of multi-circle pin by Reflow Soldering or thermocompression bonding.
According to embodiments of the invention, select the method cutting and separating products such as blade cuts, laser cutting or the cutting of water cutter, and only cut capsulation material and insulation filling material, not cutting lead framework.
Based on above-mentioned, according to the present invention, the pin that multi-turn is arranged has higher I/O density, the staircase structural model of lead frame has increased the bonded area with capsulation material and insulation filling material, there is the effect mutually locking with capsulation material and insulation filling material, can effectively prevent lead frame and the layering of capsulation material and insulation filling material and coming off of pin or chip carrier, effectively stop moisture from package structure outside to diffusion inside, the generation of bridging phenomenon when the outer pin of small size size can effectively prevent surface mount, the first metal material layer that lead frame upper surface and lower surface configure respectively and the second metal material layer can effectively improve face-down bonding quality and surface mount quality, salient point on IC chip is as electrically connected passage, shortened signal transmission path, reduced signal delay and crosstalked, also and reduced the height of packaging body, salient point and heat conduction partition are as heat conducting passage, promoted the hot property of packaging body, the fin and the IC chip back that on the face for no reason at all of IC chip, configure expose outside packaging body, increased the ability of packaging body heat radiation, can the heat dispersion of packaging part be promoted more than 30%, and improved the reliability of packaging body, owing to being only connected with insulation filling material by capsulation material between single package body, therefore when using cutter cutting and separating product, can not cut to lead frame metal material, thereby improved cutting efficiency, extended the life-span of cutter, prevented the generation of metallic bur power, before having saved the plastic packaging in traditional Q FN encapsulation flow process, glued membrane is pasted at the lead frame back side simultaneously, after plastic packaging, remove the techniques such as glued membrane and plastic packaging material overlap, reduced packaging cost.
Special embodiment below, and coordinate accompanying drawing to elaborate to above-mentioned feature and advantage of the present invention.
Accompanying drawing explanation
Figure 1A is the schematic rear view of traditional Q FN encapsulating structure;
Figure 1B is along in Figure 1A
the generalized section of section;
Fig. 2 A be the pin cross section drawn according to embodiments of the invention for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view that the thermal-enhanced multi-circle pin that is arranged in parallel is arranged FCQFN encapsulating structure;
Fig. 2 B for the pin cross section of drawing according to embodiments of the invention be rectangle, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view that the thermal-enhanced multi-circle pin that is arranged in parallel is arranged FCQFN encapsulating structure;
Fig. 3 A is that the pin cross section of drawing according to embodiments of the invention is circle, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view that staggered thermal-enhanced multi-circle pin is arranged FCQFN encapsulating structure;
Fig. 3 B is that the pin cross section of drawing according to embodiments of the invention is rectangle, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view that staggered thermal-enhanced multi-circle pin is arranged FCQFN encapsulating structure;
Fig. 4 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B;
Fig. 5 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B;
Fig. 6 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B;
Fig. 7 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B;
Fig. 8 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B;
Fig. 9 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B;
Figure 10 A to Figure 10 L is the manufacturing process generalized section of arranging FCQFN package structure according to the thermal-enhanced multi-circle pin of embodiments of the invention drafting, and all generalized sections are all along the generalized section shown in Fig. 4 section.
2 thermal-enhanced multi-circle pin array packages parts after Figure 10 M cutting and separating.
Number in the figure: 100. traditional four limit flat non-leaded packages, 11. nead frames, 111. chip carrier 112. pins, 12. capsulation materials, 13. bonding die materials, 14.IC chip, 15. plain conductors, 200, 200a, 200b, 200c, 200d, 200A, 200B, 200C, 200D, 200E, the thermal-enhanced multi-circle pin of 200F. is arranged four limit flat non-pin flip chip encapsulating piece structures, 201. lead frames, 202. chip carriers, 203. pins, 20. thin plate base materials, 20a. thin plate base material upper surface, lead frame upper surface, 20b. thin plate base material lower surface, lead frame lower surface, 21a, 21b. mask material layer, 22. first metal material layers, 23. second metal material layers, 22a. the first metal material layer surface, 23a. the second metal material layer surface, 24. grooves, 24a. staircase structural model surface, 24b. staircase structural model, 25. insulation filling materials, 25a. insulation filling material surface, 26.IC chip, the 26a.IC chip face of having chance with, 26b.IC chip has no chance face, 27. salient points, 28. adhesive materials, 29. fin, 30. capsulation materials, 31. heat conduction partitions.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail:
Fig. 2 A be the pin cross section drawn according to embodiments of the invention for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view that the thermal-enhanced multi-circle pin that is arranged in parallel is arranged FCQFN encapsulating structure.Fig. 2 B for the pin cross section of drawing according to embodiments of the invention be rectangle, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view that the thermal-enhanced multi-circle pin that is arranged in parallel is arranged FCQFN encapsulating structure.
With reference to above-mentioned Fig. 2 A-B, can find out, in the present embodiment, the lead frame 201 that thermal-enhanced multi-circle pin is arranged FCQFN encapsulating structure 200a and 200b comprises chip carrier 202 and is around chip carrier 202 pin 203 that multi-turn is arranged, and the arrangement mode of the pin 203 on chip carrier 202 every limits is for being arranged in parallel, at lead frame 201 lower surfaces, dispose the second metal material layer 23, in lead frame 201, dispose insulation filling material 25.Difference is that the pin cross section that the thermal-enhanced multi-circle pin of Fig. 2 A is arranged in four limit flat non-pin flip chip encapsulating piece structures is circle, and the pin cross section that the thermal-enhanced multi-circle pin of Fig. 2 B is arranged in four limit flat non-pin flip chip encapsulating piece structures is rectangle.
Fig. 3 A is that the pin cross section of drawing according to embodiments of the invention is circle, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view that staggered thermal-enhanced multi-circle pin is arranged FCQFN encapsulating structure.Fig. 3 B is that the pin cross section of drawing according to embodiments of the invention is rectangle, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view that staggered thermal-enhanced multi-circle pin is arranged FCQFN encapsulating structure.
With reference to above-mentioned Fig. 3 A-B, can find out, in the present embodiment, the lead frame 201 that thermal-enhanced multi-circle pin is arranged FCQFN encapsulating structure 200c and 200d comprises chip carrier 202 and is around chip carrier 202 pin 203 that multi-turn is arranged, and the arrangement mode of the pin 203 on chip carrier 202 every limits is for being staggered, at lead frame 201 lower surfaces, dispose the second metal material layer 23, in lead frame 201, dispose insulation filling material 25.Difference is that the pin cross section that the thermal-enhanced multi-circle pin of Fig. 3 A is arranged in four limit flat non-pin flip chip encapsulating piece structures is circle, and the pin cross section that the thermal-enhanced multi-circle pin of Fig. 3 B is arranged in four limit flat non-pin flip chip encapsulating piece structures is rectangle.
Fig. 4 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B, with reference to Fig. 4, in the present embodiment, thermal-enhanced multi-circle pin arrangement FCQFN encapsulating structure 200A comprises lead frame 201, the first metal material layer 22, the second metal material layer 23, insulation filling material 25, IC chip 26, salient point 27, adhesive material 28, fin 29, capsulation material 30.
Fig. 5 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B, with reference to Fig. 5, in the present embodiment, thermal-enhanced multi-circle pin arrangement FCQFN encapsulating structure 200B comprises lead frame 201, the first metal material layer 22, the second metal material layer 23, insulation filling material 25, IC chip 26, salient point 27, adhesive material 28, fin 29, capsulation material 30.
Fig. 6 draws according to embodiments of the invention, along the generalized section of the I-I section in Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B, with reference to Fig. 6, in the present embodiment, thermal-enhanced multi-circle pin arrangement FCQFN encapsulating structure 200C comprises lead frame 201, the first metal material layer 22, the second metal material layer 23, insulation filling material 25, IC chip 26, salient point 27, adhesive material 28, fin 29, capsulation material 30, heat conduction partition 31.
In the embodiment of Fig. 4, Fig. 5 and Fig. 6, lead frame 201 is as the passage of conduction, heat radiation, connection external circuit, through-thickness has staircase structural model 24b, has upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 24a of staircase structural model 24b.Lead frame 201 comprises chip carrier 202 and is around chip carrier 202 pin 203 that multi-turn is arranged, chip carrier 202 and be around chip carrier 202 pin 203 that multi-turn arranges and all have staircase structural model 24b.Chip carrier 202 is disposed at lead frame 201 central parts, and chip carrier 202 4 edge, limit through-thickness have staircase structural model 24b.A plurality of pins 203 are disposed at chip carrier 202 surroundings, around chip carrier 202, being multi-turn arranges, and through-thickness has ledge structure 24b, its shape of cross section is rounded or rectangular-shaped, and wherein each pin 203 comprises the interior pin that is disposed at this upper surface 20a and the outer pin that is disposed at this lower surface 20b.
The first metal material layer 22 and the second metal material layer 23 are disposed at respectively the upper surface 20a position of lead frame 201 and the lower surface 20b position of lead frame 201, the first metal material layer 22 has same size size with the interior pin of pin 203, and the second metal material layer 23 has same size size with the outer pin of pin 203.The first metal material layer 22 has metal material layer surface 22a, and the second metal material layer 23 has metal material layer surface 23a.
The face 26b for no reason at all that fin 29 is disposed at IC chip 26 by heat conduction adhesive material 28 is upper, as the passage of heat radiation, and exposes fin 29.
Fig. 4, embodiment difference shown in Fig. 5 and Fig. 6 is, in the embodiment of Fig. 4, a plurality of salient points 27 face-down bondings that are three circles arrangements of IC chip 26 are disposed at respectively on the interior pin of a plurality of pins 203 that are three circles arrangements, without salient point 27 face-down bondings, be disposed on chip carrier 202, in the embodiment of Fig. 5, a plurality of salient points 27 face-down bondings that are the arrangement of face battle array of IC chip 26 are disposed at respectively on the interior pin and chip carrier 202 of a plurality of pins 203 that are three circles arrangements, in the embodiment of Fig. 6, a plurality of salient points 27 face-down bondings that are three circles arrangements of IC chip 26 are disposed at respectively on the interior pin of a plurality of pins 203 that are three circles arrangements, and heat conduction partition 31 is disposed between IC chip 26 and chip carrier 202 by adhesive material 28.
The coated above-mentioned IC chip 26 of capsulation material 30, salient point 27, adhesive material 28, fin 29, heat conduction partition 31, lead frame 201 and the first metal material layer 22, expose the fin 29 on the face 26b for no reason at all that is disposed at the second metal material layer 23 of lead frame lower surface 20b and is disposed at IC chip 26, or coated above-mentioned IC chip 26, salient point 27, lead frame 201 and the first metal material layer 22, expose the fin 29 on the face 26b for no reason at all that is disposed at the second metal material layer 23 of lead frame lower surface 20b and is disposed at IC chip 26.
In the embodiment of Fig. 7, Fig. 8 and Fig. 9, lead frame 201 is as the passage of conduction, heat radiation, connection external circuit, through-thickness has staircase structural model 24b, has upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 24a of staircase structural model 24b.Lead frame 201 comprises chip carrier 202 and is around chip carrier 202 pin 203 that multi-turn is arranged, chip carrier 202 and be around chip carrier 202 pin 203 that multi-turn arranges and all have staircase structural model 24b.Chip carrier 202 is disposed at lead frame 201 central parts, the rectangular shape of its shape of cross section, and chip carrier 202 4 edge, limit through-thickness have staircase structural model 24b.A plurality of pins 203 are disposed at chip carrier 202 surroundings, around chip carrier 202, being multi-turn arranges, and through-thickness has ledge structure 24b, its shape of cross section is rounded or rectangular-shaped, and wherein each pin 203 comprises the interior pin that is disposed at this upper surface 20a and the outer pin that is disposed at this lower surface 20b.
The first metal material layer 22 and the second metal material layer 23 are disposed at respectively the upper surface 20a position of lead frame 201 and the lower surface 20b position of lead frame 201, the first metal material layer 22 has same size size with the interior pin of pin 203, and the second metal material layer 23 has same size size with the outer pin of pin 203.The first metal material layer 22 has metal material layer surface 22a, and the second metal material layer 23 has metal material layer surface 23a.
Expose for no reason at all face 26b of IC chip 26, make heat that IC chip produces directly, fast transport is in external environment condition, to promote the heat dispersion of packaging part.
Fig. 7, embodiment difference shown in Fig. 8 and Fig. 9 is, in the embodiment of Fig. 7, a plurality of salient points 27 face-down bondings that are three circles arrangements of IC chip 26 are disposed at respectively on the interior pin of a plurality of pins 203 that are three circles arrangements, without salient point 27 face-down bondings, be disposed on chip carrier 202, in the embodiment of Fig. 8, a plurality of salient points 27 face-down bondings that are the arrangement of face battle array of IC chip 26 are disposed at respectively on the interior pin and chip carrier 202 of a plurality of pins 203 that are three circles arrangements, in the embodiment of Fig. 9, heat conduction partition 31 is disposed between IC chip 26 and chip carrier 202 by heat conduction adhesive material 28.
The coated above-mentioned IC chip 26 of capsulation material 30, salient point 27, adhesive material 28, heat conduction partition 31, lead frame 201 and the first metal material layer 22, expose and be disposed at the second metal material layer 23 of lead frame lower surface 20b and the face 26b for no reason at all of IC chip 26, or coated above-mentioned IC chip 26, salient point 27, lead frame 201 and the first metal material layer 22, expose and be disposed at the second metal material layer 23 of lead frame lower surface 20b and the face 26b for no reason at all of IC chip 26.The manufacturing process that a kind of thermal-enhanced multi-circle pin is arranged four limit flat non-pin flip chip encapsulating piece structures will be described with Figure 10 A to Figure 10 L in detail below.
Figure 10 A to Figure 10 L is the manufacturing process generalized section of arranging FCQFN package structure according to the thermal-enhanced multi-circle pin of embodiments of the invention drafting, and all generalized sections are all along the generalized section shown in Fig. 4 section.
Please refer to Figure 10 A, provide to have upper surface 20a and with respect to the thin plate base material 20 of the lower surface 20b of upper surface 20a, the material of thin plate base material 20 can be that copper, copper alloy, iron, ferroalloy, nickel, nickel alloy and other are applicable to make the metal material of lead frame.The thickness range of thin plate base material 20 is 0.1mm-0.25mm, for example, be 0.127mm, 0.152mm, 0.203mm.The upper surface 20a of thin plate base material 20 and lower surface 20b are cleaned and preliminary treatment, such as using plasma water degreasing, dust etc., to realize upper surface 20a and the clean object of lower surface 20b of thin plate base material 20.
Please refer to Figure 10 B; on the upper surface 20a of thin plate base material 20 and lower surface 20b, configuration has mask material layer 21a and the mask material layer 21b of window respectively; window described here refers to not by the thin plate base material 20 of mask material layer 21a and mask material layer 21b covering; mask material layer 21a and mask material layer 21b protection is by the thin plate base material 20 of its covering, in the processing step below, will the thin plate base material 20 being covered by mask material layer 21a and mask material layer 21b be carried out to etching.
Please refer to Figure 10 C, in the window of mask material layer 21a on being disposed at the upper surface 20a of thin plate base material 20, configure the first metal material layer 22, the first metal material layer 22 has the first metal material layer surface 22a, in the window of mask material layer 21b on being disposed at the lower surface 20b of thin plate base material 20, configure the second metal material layer 23, the second metal material layers 23 and there is the second metal material layer surface 23a.The collocation method of the first metal material layer 22 and the second metal material layer 23 is the methods such as plating, chemical plating, evaporation, sputter, and allow to be formed by different metal materials, in the present embodiment, preferential selection plating or chemical plating are as the collocation method of the first metal material layer 22 and the second metal material layer 23.The material of the first metal material layer 22 and the second metal material layer 23 is nickel (Ni), palladium (Pd), gold (Au), silver (Ag), metal material and the alloys thereof such as tin (Sn), in the present embodiment, the first metal material layer 22 and the second metal material layer 23 are for example nickel-palladium-gold plates, for the first metal material layer 22, the gold plate of outside and middle palladium coating are to guarantee the face-down bonding quality of salient point 27 on lead frame 201, the nickel coating of the inside is the generation with the blocked up cocrystalization compound that prevents from being caused by Elements Diffusion-chemical reaction as diffusion impervious layer, blocked up cocrystalization compound affects the reliability in bonding region, for the second metal material layer 23, the gold plate of outside and middle palladium coating be guarantee scolder at lead frame 201 can wettability, improve the quality that packaging body mounts at circuit board upper surfaces such as PCB, the nickel coating of the inside is the generation with the blocked up cocrystalization compound that prevents from being caused by Elements Diffusion-chemical reaction as diffusion impervious layer, blocked up cocrystalization compound affects the reliability of surface mount welding region.
Please refer to Figure 10 D, mask material layer 21b on the lower surface 20b of thin plate base material 20 removed, removing method in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is the alkaline solution of selecting solubility, for example potassium hydroxide (KOH), NaOH (NaOH), mask material layer 21b on the lower surface 20b of the modes such as employing spray and thin plate base material 20 carries out chemical reaction, thereby its dissolving is reached to the effect removing, remove after mask material layer 21b, on the lower surface 20b of thin plate base material 20, be only left the second metal material layer 23.
Please refer to Figure 10 E, second metal material layer 23 of usining on the lower surface 20b of thin plate base material 20 is as etched resist layer, adopt spray mode to carry out selectivity to thin plate base material 20 lower surface 20b partially-etched, form groove 24 and staircase structural model surface 24a, etch depth scope can be the 40%-90% that accounts for the thickness of thin plate base material 20.In the present embodiment, the preferential above spray mode that adopts of spray mode, etching solution is preferentially selected alkaline etching liquid, as alkaline etching liquids such as alkaline copper chloride etching solution, ammonium chlorides, to reduce the destruction of etching solution to the second metal material layer 23.
Please refer to Figure 10 F, lower surface 20b at thin plate base material 20 fills insulation filling material 25 in the groove 24 of the partially-etched formation of selectivity, insulation filling material 25 has insulation filling material surface 25a, and this surface and the second metal material layer 23a are in same level.In the present embodiment, insulation filling material 25 is thermosetting capsulation materials, plug socket resin, the insulating material such as ink and welding resistance green oil, insulation filling material 25 has enough acidproof, alkali resistance, to guarantee that follow-up technique can not damage forming insulation filling material 25, the fill method of insulation filling material 25 is to be filled in groove 24 by methods such as injection moulding or silk screen printings, after configuration, with mechanical grinding method or chemical treatment method, remove too much insulation filling material 25, to eliminate the flash of insulation filling material 25, the insulation filling material surface 25a that makes insulation filling material 25 with the surperficial 23a of the second metal material layer in same level, for insulation filling materials 25 such as photosensitive type welding resistance green oils, by developing method, remove flash.
Please refer to Figure 10 G, mask material layer 21a on the upper surface 20a of thin plate base material 20 removed, removing method in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is the alkaline solution of selecting solubility, for example potassium hydroxide (KOH), NaOH (NaOH), mask material layer 21a chemical reaction on the upper surface 20a of the modes such as employing spray and thin plate base material 20, thereby its dissolving is reached to the effect removing, remove after mask material layer 21a, on the upper surface 20a of thin plate base material 20, be only left the first metal material layer 22.
Please refer to Figure 10 H, first metal material layer 22 of usining on the upper surface 20a of thin plate base material 20 is as etched resist layer, adopt spray mode to carry out selectivity to thin plate base material 20 upper surface 20a partially-etched, be etched to staircase structural model surface 24a, expose insulation filling material 25.Form lead frame 201, lead frame 201 comprises chip carrier 202 and is around chip carrier 202 pin 203 that multi-turn is arranged, in lead frame 201, dispose insulation filling material 25, i.e. chip carrier 202 and be around chip carrier 202 pin 203 that multi-turn arranges and be fixed together by insulation filling material 25.The separated pin 203 forming after selectivity is partially-etched has interior pin and outer pin, and interior pin connects the salient point 27 of IC chip 26 in follow-up IC chip face-down bonding technique, and outer pin is as the passage that connects external circuit.Form staircase structural model 24b, staircase structural model 24b has staircase structural model surface 24a.In the present embodiment, the preferential above spray mode that adopts of the spray mode of etching solution, etching solution is preferentially selected alkaline etching liquid, as alkaline etching liquids such as alkaline copper chloride etching solution, ammonium chlorides, to reduce the destruction of etching solution to the first metal material layer 22.
Please refer to Figure 10 I, IC chip 26 has have chance with face 26a and corresponding with the face 26a that has chance with face 26b for no reason at all, and is a plurality of salient points 27 that three circles arrange and is disposed on the face of the having chance with 26a of IC chip 26.By core equipment in upside-down mounting by IC chip 26 flip-chip configuration in the first metal material layer 22 positions of lead frame upper surface 20a, a plurality of salient points 27 that are three circles arrangements on IC chip 26 are disposed at respectively on the interior pin of a plurality of pins 203 that are three circles arrangements, in the present embodiment, on IC chip 26, salient point 27 is lead-free solder salient point, solder containing pb salient point or metal salient point.
Please refer to Figure 10 J, a plurality of salient points 27 that three circles arrange of being on IC chip 26 are connected on a plurality of interior pins that are a plurality of pins 203 that three circles arrange that dispose the first metal material layer 22, to realize electrical interconnection by Reflow Soldering or thermocompression bonding.
Please refer to Figure 10 K, adopt the adhesive material 28 of heat conduction that fin 29 is disposed on the face 26b for no reason at all of IC chip 26.
Please refer to Figure 10 L, adopt injection moulding process, by the coated above-mentioned IC chip 26 of environment-friendly type plastic closure material 30, salient point 27, adhesive material 28, fin 29, lead frame 201 and the first metal material layer 22, form product array, expose and be disposed at the second metal material layer 23 of lead frame lower surface 20b and the face 26b for no reason at all of IC chip 26.In the present embodiment, capsulation material 30 can be the materials such as thermosetting polymer, the insulation filling material 25 of filling has the physical property similar to capsulation material 30, thermal coefficient of expansion for example, to reduce the product failure being caused by thermal mismatching, improve the reliability of product, insulation filling material 25 can be commaterial with capsulation material 30.After toasting after plastic packaging, solidify, capsulation material 30 and insulation filling material 25 have mutual lock function with the lead frame 201 with staircase structural model 24b, can effectively prevent lead frame 201 and capsulation material 30 and the layering of insulation filling material 25 and coming off of pin 203 or chip carrier 202, and effectively stop moisture to be diffused into package interior along lead frame 201 and the combination interface of capsulation material 30 and insulation filling material 25, improved the reliability of packaging body.After plastic packaging, product array is carried out to laser printing.
Please refer to Figure 10 M, cut thermal-enhanced multi-circle pin and arrange FCQFN products of separated array, thoroughly cutting and separating capsulation material 30 and insulation filling material 25 form single thermal-enhanced multi-circle pin and arrange FCQFN packaging part 200, in the present embodiment, single product separation method is the methods such as blade cuts, laser cutting or the cutting of water cutter, and only cut capsulation material 30 and insulation filling material 25, cutting lead framework metal material, does not only draw out 2 thermal-enhanced multi-circle pins arrangement FCQFN packaging parts 200 after cutting and separating in Figure 10 M.
To the description of embodiments of the invention, be for effectively illustrating and describe object of the present invention, not in order to limit the present invention, under any, those skilled in the art is to be understood that: not departing under the condition of inventive concept of the present invention and scope, can change above-described embodiment.Therefore the present invention is not limited to disclosed specific embodiment, but cover the modification in the defined the spirit and scope of the invention of claim.
Claims (2)
1. a manufacture method for thermal-enhanced four limit flat non-pin flip chip encapsulating piece structures, this package structure comprises:
Lead frame, through-thickness has staircase structural model, has upper surface, lower surface and ledge surface, and wherein lead frame comprises chip carrier, a plurality of pin:
Chip carrier, is disposed at lead frame central part, and chip carrier four edge, limit through-thickness have staircase structural model, have upper surface, lower surface and ledge surface, and
A plurality of pins, be disposed at chip carrier surrounding, be multi-turn arrange around chip carrier, through-thickness has staircase structural model, have upper surface, lower surface and ledge surface, wherein each pin comprises the interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface;
The first metal material layer, is disposed at the upper surface position of lead frame;
The second metal material layer, is disposed at the lower surface position of lead frame;
The IC chip with salient point, is disposed at by face-down bonding on the first metal material layer of lead frame upper surface position;
Insulation filling material, is disposed under the staircase structural model of lead frame;
Capsulation material, coated IC chip, lead frame and first metal material layer with salient point, forms packaging part,
The manufacture method of described package structure is characterised in that and comprises:
Configuration mask material layer, the mask material layer pattern that there is window in upper surface and the lower surface configuration of thin plate base material;
Configure the first metal material layer and the second metal material layer, in the window of mask material layer that is disposed at thin plate base material upper surface and lower surface, configure respectively the first metal material layer and the second metal material layer;
Lower surface selectivity is partially-etched, removes the mask material layer of thin plate base material lower surface, take the second metal material layer as resist layer, thin plate base material lower surface is carried out to selectivity partially-etched, forms groove;
Configuration insulation filling material, at thin plate base material lower surface fill insulant in the groove of the partially-etched formation of selectivity;
Upper surface selectivity is partially-etched, remove the mask material layer of thin plate base material upper surface, take the first metal material layer as corrosion preventing layer, thin plate base material upper surface is carried out to selectivity partially-etched, formation has the lead frame of staircase structural model, comprises separated chip carrier and multi-circle pin;
Configuration has the IC chip of salient point, by core equipment in upside-down mounting, the IC chip face-down bonding with salient point is disposed to the metal material layer position of lead frame upper surface, realizes salient point be connected with lead frame by Reflow Soldering or thermocompression bonding;
Form packaging part, with coated IC chip, lead frame and first metal material layer with salient point of capsulation material, form packaging part;
Cutting and separating forms single package, and cutting and separating forms independently single package.
2. method according to claim 1, it is characterized in that, the separated chip carrier and the multi-circle pin that through this etching, form are connected and fixed by insulation filling material, by forming single package by blade cuts, laser cutting or water cutter cutting method cutting and separating, and only cut capsulation material and insulation filling material.
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| CN201110460400.7A CN102543907B (en) | 2011-12-31 | 2011-12-31 | Package and manufacture method for thermal enhanced quad flat no-lead flip chip |
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| GB2520952A (en) | 2013-12-04 | 2015-06-10 | Ibm | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| CN103730429B (en) * | 2013-12-05 | 2017-06-20 | 通富微电子股份有限公司 | Encapsulating structure |
| CN103824785B (en) * | 2013-12-05 | 2017-01-11 | 南通富士通微电子股份有限公司 | Package structure forming method |
| CN103745965B (en) * | 2013-12-05 | 2017-02-01 | 通富微电子股份有限公司 | Packaging structure |
| CN103730378B (en) * | 2013-12-05 | 2016-08-31 | 南通富士通微电子股份有限公司 | The forming method of encapsulating structure |
| CN103745939B (en) * | 2013-12-05 | 2017-02-15 | 通富微电子股份有限公司 | Packaging structure forming method |
| CN103745964A (en) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | Packaging structure |
| TWI570856B (en) * | 2014-11-10 | 2017-02-11 | 恆勁科技股份有限公司 | Package structure and method of manufacture |
| CN105720036A (en) * | 2014-12-03 | 2016-06-29 | 恒劲科技股份有限公司 | Package structure and method of manufacture |
| CN105789068B (en) * | 2014-12-25 | 2019-11-08 | 无锡华润安盛科技有限公司 | A kind of preparation method of QFN packaging |
| KR101905240B1 (en) | 2015-01-29 | 2018-10-05 | 앰코테크놀로지코리아(주) | Semiconductor package and manufacturing method thereof |
| US10043737B2 (en) * | 2015-12-02 | 2018-08-07 | Novatek Microelectronics Corp. | Chip on film package |
| US10770368B2 (en) | 2015-12-02 | 2020-09-08 | Novatek Microelectronics Corp. | Chip on film package and heat-dissipation structure for a chip package |
| CN110660681A (en) * | 2018-06-28 | 2020-01-07 | 上海怡英新材料科技有限公司 | Flip chip assembly and packaging method thereof |
| DE102019122382B3 (en) * | 2019-08-20 | 2020-09-10 | Infineon Technologies Ag | POWER SEMI-CONDUCTOR ENCLOSURE AND METHOD FOR MANUFACTURING A POWER SEMICONDUCTOR ENCLOSURE |
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| CN100485917C (en) * | 2006-08-22 | 2009-05-06 | 南茂科技股份有限公司 | Method for manufacturing non-exterior pin semiconductor packaging construction plated in sealing glue |
| CN100559577C (en) * | 2006-08-23 | 2009-11-11 | 南茂科技股份有限公司 | Wafer packaging construction and manufacture method thereof with array connecting pad |
| CN101877334B (en) * | 2009-04-28 | 2012-03-07 | 钰桥半导体股份有限公司 | Semiconductor device with heat radiation and gain |
| CN102263077A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | Double flat carrier-free pin-free IC chip packaging part |
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