CN102543897A - 半导体芯片及具有该半导体芯片的半导体封装件 - Google Patents
半导体芯片及具有该半导体芯片的半导体封装件 Download PDFInfo
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Abstract
一种半导体芯片及具有该半导体芯片的半导体封装件。该半导体芯片包括:半导体芯片主体,具有第一表面和背对该第一表面的第二表面,并且包括设置在该第一表面上的多个接合焊盘。另外,该半导体芯片包括距离保持构件,该距离保持构件连接到该半导体芯片主体的该第一表面,并且与电路图案电连接。
Description
技术领域
本发明涉及半导体封装件,更具体地,涉及具有改善的安装可靠性的半导体芯片及具有该半导体芯片的半导体封装件。
背景技术
已经提出了采用凸块的倒装芯片封装件以缩短半导体芯片和印刷电路板之间的电信号传输通道。
倒装芯片封装件具有这样的结构,其中半导体芯片通过半导体芯片的接合焊盘上形成的凸块物理地连接到且同时电连接到印刷电路板。倒装芯片封装件具有这样的优点:因为半导体芯片和印刷电路板之间的电连接仅由凸块形成,所以信号传输通道短,并且可获得优良的电特性。
然而,倒装芯片封装件却有这样的问题:湿气很可能泄漏到连接部分,并且由于半导体芯片和印刷电路板之间的CTE(热膨胀系数)的差别,应力连续地施加到连接部分。从而,这些连接部分中可能经常发生疲劳断裂。
当前,为了解决这些问题,进行用间隙填充物质填充半导体芯片和印刷电路板之间的间隔的底料填充工艺。然而,底料填充工艺导致另外的问题:难于控制处理,并且间隙填充物质中容易产生空洞。
而且,在采用底料填充工艺的情况下,在随后的工艺中可能不会适当地进行润湿,这可能降低处理稳定性和可加工性,从而降低了倒装芯片封装件的可靠性和产率。
除了采用以间隙填充物质填充间隔的底料填充工艺外,已经提出了这样的方法,其中在印刷电路板上形成膜或非导电粘合剂(NCA)后连接半导体芯片。在该方法中,与底料填充工艺相比减少了空洞的产生。
然而,在膜或非导电粘合剂的厚度充分大的情况下,半导体芯片的凸块和印刷电路板可能由于膜或非导电粘合剂的充分大的厚度而易于非适当连接,并且在传输电信号时可能发生问题。
发明内容
本发明的实施例针对于能够改善安装可靠性的半导体芯片。
另外,本发明的实施例针对于具有能够改善安装可靠性的半导体芯片的半导体封装件。
在本发明的实施例中,半导体芯片包括半导体芯片主体和距离保持构件,该半导体芯片主体具有第一表面和背对第一表面的第二表面,并且包括设置在第一表面上的多个接合焊盘;该距离保持构件连接到半导体芯片主体的第一表面,并且与电路图案电连接。
电路图案形成在半导体芯片主体中,并且可包括转换和放大输入电压的电路。
距离保持构件可包括:传感元件,构造为感应半导体芯片主体的第一表面和设置半导体芯片主体的表面之间的距离;以及补偿元件,构造为适当地保持该距离。
补偿元件可设置在相邻于传感元件的位置。
在距离保持构件内,补偿元件的数量可大于传感元件的数量。
传感元件可包括第一压电元件,该第一压电元件构造为产生传送到电路图案的第一级信号(first level signal),其中第一级信号根据施加到第一压电元件的第一应力产生;并且补偿元件可包括第二压电元件,该第二压电元件构造为接收基于第一级信号的来自电路图案的第二级信号(second levelsignal)。
第一级信号和第二级信号可具有相反的极性和基本上相同的幅度。
至少一个距离保持构件可连接到半导体芯片主体的第一表面。
半导体芯片还可包括连接到接合焊盘的连接构件。
连接构件可与半导体芯片主体的第一表面上形成的距离保持构件具有基本上相同的高度。
在本发明的另一个实施例中,半导体封装件包括:半导体芯片,包括半导体芯片主体和距离保持构件,半导体芯片主体具有第一表面和背对第一表面的第二表面,并且包括第一表面上设置的多个接合焊盘,距离保持构件连接到半导体芯片主体的第一表面,并且与电路图案电连接;以及基板,具有上表面和背对上表面的下表面,半导体芯片安装在上表面上,并且与距离保持构件接触。
电路图案形成在半导体芯片主体中,并且可包括转换和放大输入电压的电路。
距离保持构件可包括传感元件和补偿元件,传感元件构造为感应半导体芯片主体的第一表面和基板的上表面之间的距离,补偿元件构造为适当地保持该间隔。
补偿元件可设置在相邻于传感元件的位置。
在距离保持构件内,补偿元件的数量可大于传感元件的数量。
传感元件可包括第一压电元件,该第一压电元件构造为产生第一级信号以传送到电路图案,其中第一级信号根据施加到第一压电元件的第一应力产生;并且补偿元件可包括第二压电元件,该第二压电元件构造为接收由电路图案基于第一级信号产生的第二级信号。
第一级信号和第二级信号可具有相反的极性和基本上相同的幅度。
至少一个距离保持构件可连接到半导体芯片主体的第一表面。
半导体封装件还可包括连接构件,该连接构件将接合焊盘与基板的至少一部分电连接。
连接构件可与半导体芯片主体的第一表面上形成的距离保持构件具有基本上相同的高度。
附图说明
图1是示出根据本发明实施例的半导体芯片的截面图。
图2是示出根据本发明另一个实施例的半导体封装件的截面图。
具体实施方式
在下文,将参考附图详细描述本发明的具体实施例。应该理解,本发明不限于所描述的本发明的这些示范性实施例。
这里应理解的是,附图不一定按比例,并且在某些情况下,可能会为了更清楚地描绘本发明的某些特征而被放大。
图1是示出根据本发明实施例的半导体芯片的截面图。
参考图1,根据本发明实施例的半导体芯片110包括半导体芯片主体102、电路图案104、连接构件108和距离保持构件106。
半导体芯片主体102例如可为具有顶表面和底表面的矩形六面体(rectangular hexahedral)形状,并具有设置在底表面上的多个接合焊盘(未示出)。
每个电路图案104形成在半导体芯片主体102中,并且可包括转换和放大输入电压的电路。一个或更多个电路图案104可形成在半导体芯片主体102中。尽管图中没有示出,但是电路图案104可设置在半导体芯片主体102的外面。
距离保持构件106连接到半导体芯片主体102的底表面以从底表面凸出,并且与电路图案104电连接。电路图案104和距离保持构件106由电路配线R彼此电连接。
每个距离保持构件106用作保持半导体芯片主体102的底表面和要设置半导体芯片主体102的目标物之间的间隔的部件。距离保持构件106包括用于感应间隔的传感元件A和用于间隔补偿的补偿元件B。补偿元件B设置为相邻于传感元件A。例如,补偿元件B的数量可为传感元件A的数量的两倍。
传感元件A和补偿元件B例如包括压电元件。如本技术领域所通常知晓的,压电元件具有与施加的应力成比例地产生电压的特性。反之亦然。因此,压电元件的特性为诸如体积上的收缩或膨胀的物理位移取决于施加的电压而发生。
在本发明的实施例中,传感元件A包括第一压电元件,该第一压电元件根据施加到第一压电元件的第一应力产生第一级信号,并且将第一级信号传输到对应的电路图案104,该电路图案104处理第一级信号以输出第二级信号。补偿元件B包括第二压电元件,该第二压电元件根据来自电路图案104的第二级信号改变其形状。第一级信号和第二级信号可具有适当的相互关系,从而第一级信号的幅度产生第二级信号,该第二级信号允许补偿元件B的第二压电元件减轻在传感元件A的第一压电元件中的应力。
例如,每个电路图案104可用于施加第二级电压到补偿元件B的第二压电元件,从而其体积改变与传感元件A的第一压电元件相同的幅度。电路图案104的实施例可取决于传感元件A和补偿元件B所采用的压电材料。
如图所示,电路图案104形成在半导体芯片主体102中。然而,尽管图中没有示出,但是可考虑电路图案104可设置在半导体芯片主体102的外面。用于产生与第一级信号相反极性的第二级信号的示范性电路图案104可包括放大电路和转换电路,它们与传感元件A和补偿元件B电连接。尽管它通常描述为两个单独的电路-放大电路和转换电路,但是电路图案104例如可包括进行放大和转换的单一电路。
连接构件108连接到接合焊盘,并且例如包括诸如焊料块和柱凸块(studbump)的凸块。
图2是示出具有根据本发明另一个实施例的具有倒装芯片封装件结构的半导体封装件的截面图。
参考图2,根据本发明另一个实施例的半导体封装件120包括基板100和安装在基板100上的半导体芯片110。
基板100例如可为印刷电路板(PCB)。基板100具有上表面和下表面。尽管没有示出,但是基板100可包括设置在上表面上的多个连接指、设置在下表面上的多个球焊垫以及基板中设置的多个通路图案,该多个通路图案例如以一对一的对应关系将连接指和球焊垫电连接。
以与图1所示相同的方式,半导体芯片110包括半导体芯片主体102、电路图案104、连接构件108和距离保持构件106。半导体芯片110以面向下(face-down)的方式设置在基板100的上表面上,并且由连接构件108安装到基板100的上表面。
半导体芯片主体102具有顶表面和底表面,并且包括设置在底表面上的多个接合焊盘(未示出)。每个电路图案104形成在半导体芯片主体102中,并且接收第一级信号及输出对应于第一级信号的第二级信号。连接构件108形成在半导体芯片主体102的底表面上设置的接合焊盘上,并且例如包括凸块。从而,半导体芯片110的接合焊盘和基板100的连接指由连接构件108彼此电连接。
每个距离保持构件106包括传感元件A和补偿元件B,其二者都与对应的电路图案104电连接。传感元件A和补偿元件B可与连接构件108具有相同的高度。因此,当半导体芯片110由连接构件108安装到基板100的上表面时,距离保持构件106的传感元件A和补偿元件B与基板100的上表面接触。
距离保持构件106和电路图案104的至少之一可插设在基板100和半导体芯片110之间。电路图案104可设置在半导体芯片110的内部或外部。
尽管没有示出,但是根据本发明实施例的半导体封装件120还可包括包封构件,其密封基板100的上表面、以及半导体芯片110和连接到基板100的下表面的用作到外部电路的安装装置的外部连接端(未示出)。
在根据本发明另一个实施例的半导体封装件120中,基板100和半导体芯片110之间的间隔由传感元件A和补偿元件B的作用保持,可通过其改善接合的可靠性。
如上所述,距离保持构件106插设在基板100和半导体芯片110之间。距离保持构件106包括传感元件A和补偿元件B。传感元件A和补偿元件B由电路配线R与半导体芯片110中形成的电路图案104电连接。
传感元件A和补偿元件B例如包括压电元件。压电元件的特性为其体积根据施加的电压而增加或减小。反之,压电元件因外力而与其体积的增加或减小成比例地产生电压。在本发明的实施例中,当传感元件A的压电元件因拉应力产生电压时,补偿元件B的压电元件被提供压应力的电压。就是说,当传感元件A伸长时,导致补偿元件B收缩以减小传感元件A的伸长。类似地,如果传感元件A受压,则导致补偿元件B伸长以减小传感元件A的受压。
因此,距离保持构件106可通过采用来自传感元件A的第一级信号保持基板100和半导体芯片110之间的间隔而适当地控制补偿元件B的形状。
例如,如果在传感元件A上引起拉应力,则传感元件A产生的第一级信号由电路图案104适当处理,以输出施加给补偿元件B的第二级信号。补偿元件B因施加的第二级信号而收缩,以补偿传感元件A上的拉应力。
因此,如果导致补偿元件B收缩,则减少施加到传感元件A的拉应力。从而,减小了施加到电路图案104的第一级信号,并且也减小了施加给补偿元件B的压应力。结果,在半导体芯片110和基板100之间的初始设计间隙高度附近达到平衡。
反之,如果传感元件A上引起压应力,则第二级信号导致补偿元件B增加其体积。从而,减小了传感元件A上的压应力。因此,减小了施加到电路图案104的第一级信号,也减小了施加到补偿元件B的拉应力。结果,基本上保持了半导体芯片110和基板100之间的初始设计间隙高度。
因此,根据施加到传感元件A的第一应力且传送到电路图案104的第一级信号,以及通过由电路图案104处理第一级信号产生且传送到补偿元件B以对补偿元件B引起第二应力的第二级信号,可理解为具有相反的极性和类似的幅度。此外,第一应力和第二应力可理解为相反的应力:如果第一应力是压应力,则第二应力是拉应力,反之亦然。
这样,在本发明的实施例中,传感元件A和补偿元件B采用压电元件,以通过自动补偿程序最小化半导体芯片110和基板100之间的间隔变化。结果,可减小施加到诸如凸块的连接构件108的应力,由此可改善连接构件108的接合可靠性,并且可改善半导体封装件120的可靠性。尽管本发明的各种实施例涉及半导体芯片110和基板100,但是本发明不限于此。例如,本发明的实施例可用在垂直堆叠的两个半导体芯片110之间。
在根据本发明实施例的半导体封装件120中,因为距离保持构件106用于保证基板100和半导体芯片110的安装可靠性,所以距离保持构件106可替代根据常规技术进行的底料填充工艺以保证安装可靠性。从而,在本发明的各实施例中,通过省略底料填充工艺可降低制造成本,并且也可解决采用底料填充工艺引起的由于可靠性变坏导致的问题。
另外,在本发明的各实施例中,因为不必进行形成膜或非导电粘合剂的工艺取代底料填充工艺,所以能够解决在传输电信号时由于采用膜或非导电粘合剂可能导致的问题。
尽管以说明的目的已经描述了本发明的具体实施例,但是本领域的技术人员可理解的是,各种修改、添加和替代是可能的,而不脱离如权利要求公开的本发明的范围和精神。
本申请要求2010年12月17日提交的韩国专利申请第10-2010-0129868号的优先权,其通过全文引用结合于此。
Claims (20)
1.一种半导体芯片,包括:
半导体芯片主体,具有第一表面和背对该第一表面的第二表面,并且包括设置在该第一表面上的多个接合焊盘;以及
距离保持构件,连接到该半导体芯片主体的该第一表面,并且与电路图案电连接。
2.根据权利要求1所述的半导体芯片,其中该电路图案形成在该半导体芯片主体中,并且包括转换和放大输入电压的电路。
3.根据权利要求1所述的半导体芯片,其中该距离保持构件包括:
传感元件,构造为感应该半导体芯片主体的该第一表面和设置该半导体芯片主体的表面之间的距离;以及
补偿元件,构造为适当地保持该距离。
4.根据权利要求3所述的半导体芯片,其中该补偿元件设置在相邻于该传感元件的位置。
5.根据权利要求3所述的半导体芯片,其中在该距离保持构件内,该补偿元件的数量大于该传感元件的数量。
6.根据权利要求3所述的半导体芯片,其中该传感元件包括第一压电元件,该第一压电元件构造为产生第一级信号以传送到该电路图案,其中该第一级信号根据施加到该第一压电元件的第一应力产生;并且该补偿元件包括第二压电元件,该第二压电元件构造为接收由该电路图案基于该第一级信号产生的第二级信号。
7.根据权利要求6所述的半导体芯片,其中该第一级信号和该第二级信号具有相反的极性和基本上相同的幅度。
8.根据权利要求1所述的半导体芯片,其中至少一个距离保持构件连接到该半导体芯片主体的该第一表面。
9.根据权利要求1所述的半导体芯片,还包括:
连接构件,连接到该接合焊盘。
10.根据权利要求9所述的半导体芯片,其中该连接构件与形成在该半导体芯片主体的该第一表面上的该距离保持构件具有基本上相同的高度。
11.一种半导体封装件,包括:
半导体芯片,包括半导体芯片主体和距离保持构件,该半导体芯片主体具有第一表面和背对该第一表面的第二表面,并且包括设置在该第一表面上的多个接合焊盘,该距离保持构件连接到该半导体芯片主体的该第一表面,并且与电路图案电连接;以及
基板,具有上表面和背对该上表面的下表面,该半导体芯片安装在该上表面上并且与该距离保持构件接触。
12.根据权利要求11所述的半导体封装件,其中该电路图案形成在该半导体芯片主体中,并且包括转换和放大输入电压的电路。
13.根据权利要求12所述的半导体封装件,其中该距离保持构件包括:
传感元件,构造为感应该半导体芯片主体的该第一表面和该基板的上表面之间的距离;以及
补偿元件,构造为适当地保持该距离。
14.根据权利要求13所述的半导体封装件,其中该补偿元件设置在相邻于该传感元件的位置。
15.根据权利要求13所述的半导体封装件,其中在该距离保持构件内,该补偿元件的数量大于该传感元件的数量。
16.根据权利要求13所述的半导体封装件,其中该传感元件包括第一压电元件,该第一压电元件构造为产生第一级信号以传送到该电路图案,其中该第一级信号根据施加到该第一压电元件的第一应力产生;并且该补偿元件包括第二压电元件,该第二压电元件构造为接收由该电路图案基于该第一级信号产生的第二级信号。
17.根据权利要求15所述的半导体封装件,其中该第一级信号和该第二级信号具有相反的极性和基本上相同的幅度。
18.根据权利要求11所述的半导体封装件,其中至少一个距离保持构件连接到该半导体芯片主体的该第一表面。
19.根据权利要求11所述的半导体封装件,还包括:
连接构件,将该接合焊盘与该基板的至少一部分电连接。
20.根据权利要求19所述的半导体封装件,其中该连接构件与形成在该半导体芯片主体的该第一表面上的该距离保持构件具有基本上相同的高度。
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US20040189141A1 (en) * | 1997-09-08 | 2004-09-30 | Avto Tavkhelidze | Thermionic vacuum diode device with adjustable electrodes |
US6333104B1 (en) * | 2000-05-30 | 2001-12-25 | International Business Machines Corporation | Conductive polymer interconnection configurations |
US20070126435A1 (en) * | 2005-12-02 | 2007-06-07 | Formfactor, Inc. | Apparatus And Method For Adjusting An Orientation Of Probes |
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