CN102543890A - Method for improving erasing speed of SONOS (Silicon Oxide Nitride Oxide Silicon) by utilizing strained silicon technology - Google Patents
Method for improving erasing speed of SONOS (Silicon Oxide Nitride Oxide Silicon) by utilizing strained silicon technology Download PDFInfo
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- CN102543890A CN102543890A CN2012100473805A CN201210047380A CN102543890A CN 102543890 A CN102543890 A CN 102543890A CN 2012100473805 A CN2012100473805 A CN 2012100473805A CN 201210047380 A CN201210047380 A CN 201210047380A CN 102543890 A CN102543890 A CN 102543890A
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Abstract
The invention discloses a method for improving an erasing speed of an SONOS (Silicon Oxide Nitride Oxide Silicon) by utilizing a strained silicon technology. The method is characterized by comprising the following steps of: after manufacturing a sidewall of a grid electrode on a P-type substrate forming a plurality of shallow channel isolation regions, (1) depositing a baffle layer to cover a transistor; (2) etching to remove the baffle layer covering above an NMOS (N-channel Metal Oxide Semiconductor) region to expose the NMOS region; (3) etching silicon of active regions on two sides of the grid electrode of the NMOS region; (4) depositing silicon carbide at the active regions through a selectivity epitaxy process; and (5) carrying out high-temperature annealing to enable the silicon carbide to generate tensile stress on a channel. According to the method for increasing the erasing speed of the SONOS by utilizing the strained silicon technology, disclosed by the invention, an energy band of silicon is broken up so that effective mass of electron in the direction of the channel is reduced; simultaneously, energy valley scattering probability of the electron is also reduced, and mobility of the electron of the SONOS unit transistor is remarkably improved, thus the SONOS programming efficiency and speed of a hot electron injection mechanism are improved.
Description
Technical field
The present invention relates to silicon-silica-silicon-nitride and silicon oxide-silicon (SONOS) memory, particularly, relate to a kind of erasable method of velocity of utilizing strained silicon technology to improve SONOS.
Background technology
The basic functional principle of non-volatile semiconductor memory is a stored charge in the gate medium of a MOSFET.Wherein the device that is stored in the trapping centre of separation of a suitable dielectric layer of electric charge is called as the electric charge capture device.The most frequently used in this type device is silicon-silica-silicon-nitride and silicon oxide-silicon (SONOS) memory.
The main two kinds of memory mechanisms that are used for the storage data of flash memory cells are that channel hot electron (CHE) injects and the F-N tunneling effect.Channel hot electron injects and is considered to after through long-term circulation, remain quite reliable, and reason is that it does not apply very big stress on tunnel oxide.But the shortcoming of CHE is that programming efficiency is low.It is that transverse electric field with raceway groove comes accelerated electron that channel hot electron injects, and obtains one when being enough to overcome the high-energy of potential barrier when electronics is accelerated to, and the hot electron injection will take place.During programming, drain and gate all will apply relative higher voltage, and drain electrode directly links to each other with voltage source, and grid voltage then depends on capacitive coupling.For effective programming, transistor should be biased in the saturation region, makes the electronics that passes pinch-off point in the drain terminal depletion region, set up big transverse electric field.This bias state of grid makes near the channel inversion layer broad the source, and along with the convergence pinch-off point, it is narrower that channel inversion layer becomes, so that pass in the high electric field of electronics in the drain terminal depletion region of pinch-off point by strong acceleration.When portions of electronics obtains enough high-energy like this, hot electron just takes place inject, but because to have only the sub-fraction raceway groove be effectively to programming, so hot electron injection programming efficient is not high.
Therefore, provide a kind of erasable method of velocity of strained silicon technology raising SONOS and SONOS cell transistor of high erasable speed of utilizing just to seem particularly important.
Summary of the invention
The objective of the invention is to improve, thereby realize improving SONOS programming efficiency and the speed that hot electron injects mechanism through the electron mobility that makes the SONOS cell transistor.
The present invention discloses a kind of strained silicon technology of utilizing and improves the transistorized erasable method of velocity of SONOS, wherein, after having made the side wall of grid on the P type substrate that forms some shallow channel isolation areas, also comprises the steps:
Step 1, the deposition barrier layer covers said transistor;
Step 2, etching are removed the barrier layer that covers top, nmos area territory exposes said nmos area territory;
Step 3 is carried out carbon ion and is injected on the P type substrate between said grid both sides and the shallow channel isolation area;
Step 4 is carried out high annealing, makes said carborundum produce tensile stress to raceway groove.
Above-mentioned method wherein, behind completing steps 4, also comprises the step of removing the barrier layer.
According to another aspect of the present invention, also disclose a kind of SONOS cell transistor that adopts above-mentioned method to make, comprised some paired PMOS and NMOS, said NMOS comprises:
Have the P type silicon substrate of some paired active areas, each is to being formed with raceway groove between the active area;
Grid is positioned at said raceway groove top, has silica-silicon-nitride and silicon oxide layer between the side wall of said grid, is polysilicon on said silica-silicon-nitride and silicon oxide layer;
The both sides of the periphery of said paired active area are respectively arranged with shallow channel isolation area;
Wherein, the paired active area of the active area of said NMOS comprises carborundum.
Above-mentioned SONOS cell transistor, wherein, said paired active area comprises source electrode and drain electrode.
In order to improve SONOS programming efficiency and the speed that hot electron injects mechanism, the present invention sets about from the angle that improves the channel carrier mobility.Carrier mobility can be by equation μ=qt/m* decision, and wherein q is an electron charge, and m* is the charge carrier effective mass, and t is the average life span between double scattering, so probability of scattering is 1/t.
The present invention utilizes the stress si technology, after the SONOS side wall forms, returns back depositing silicon carbide at quarter at source-drain area; Through annealing the source is leaked the SONOS cell channel is produced tensile stress; Being with of silicon divided, and the result of division causes reducing along the electron effective mass of channel direction, and the energy valley probability of scattering of electronics also reduces simultaneously; The electron mobility of SONOS cell transistor is significantly improved, thereby improve SONOS programming efficiency and speed that hot electron injects mechanism.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the part parts, for same parts, only indicated wherein part, those skilled in the art can combine embodiment partly to understand.
Fig. 1 shows according to the present invention, the profile after SONOS unit component side wall forms;
Fig. 2 is that nmos area territory window is opened, and carries out carbon ion and injects the sketch map that forms carborundum; And
Fig. 3 makes the sketch map of the carborundum of source and drain areas to raceway groove generation tensile stress for through high-temperature annealing process.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further elaborated.Embodiment described herein only is used to explain the present invention, and is not used in qualification protection scope of the present invention.
In conjunction with reference to figure 1 and Fig. 2, disclose the present invention and utilized strained silicon technology to improve the erasable method of velocity of SONOS, among Fig. 1, after having made the side wall 102 of grid 101 on the P type substrate 104 that forms some shallow channel isolation areas 105, also comprise the steps:
Step 1, deposition barrier layer (not shown in figure 1) covers said transistor;
Step 2, etching are removed the barrier layer that covers top, nmos area territory exposes said nmos area territory, in this step; Elder generation's spin coating photoresist is on said barrier layer; Carry out photoetching again, those skilled in the art can combine the said step of existing techniques in realizing, do not repeat them here;
Step 3 is carried out carbon ion and is injected on the P type substrate 104 between said grid 101 both sides and the shallow channel isolation area 105, as shown in Figure 2;
Step 4 is carried out high annealing, makes said carborundum produce tensile stress (as shown in Figure 3) to raceway groove.
The present invention divides being with of silicon; The result of division causes reducing along the electron effective mass of channel direction; The energy valley probability of scattering of electronics also reduces simultaneously; The electron mobility of SONOS cell transistor is significantly improved, thereby improve SONOS programming efficiency and speed that hot electron injects mechanism.
Further, in above-mentioned method, behind the completing steps 4, also comprise the step of removing the barrier layer.
Again with reference to figure 3; As shown in the figure the comprising of SONOS cell transistor of the erasable speed of height of the present invention: comprise some paired PMOS (not shown in the accompanying drawing) and NMOS; Said NMOS comprises: have the P type silicon substrate 104 of some paired active areas 103, each is to being formed with raceway groove (not shown among Fig. 3) between the active area 103; Grid 101 is positioned at said raceway groove top, has silica-silicon-nitride and silicon oxide layer 111 (ONO layer) between the side wall 102 of said grid 101, is polysilicon 121 on said silica-silicon-nitride and silicon oxide layer 111; The both sides of the periphery of said paired active area 103 are respectively arranged with shallow channel isolation area 105; Wherein, the active area 103 paired active areas 103 of said NMOS comprise carborundum (SiC).
Particularly, in the SONOS cell transistor of the erasable speed of described height, said paired active area 103 comprises source electrode and drain electrode.
The present invention improves through the electron mobility that makes the SONOS cell transistor, thereby realizes improving SONOS programming efficiency and the speed that hot electron injects mechanism.
Those skilled in the art combine prior art and the foregoing description can realize said variant, and such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (4)
1. one kind is utilized strained silicon technology to improve the transistorized erasable method of velocity of SONOS, it is characterized in that, after having made the side wall of grid on the P type substrate that forms some shallow channel isolation areas, also comprises the steps:
Step 1, the deposition barrier layer covers said transistor;
Step 2, etching are removed the barrier layer that covers top, nmos area territory exposes said nmos area territory;
Step 3 is carried out carbon ion and is injected on the P type substrate between said grid both sides and the shallow channel isolation area;
Step 4 is carried out high annealing, makes said carborundum produce tensile stress to raceway groove.
2. method according to claim 1 is characterized in that, behind completing steps 4, also comprises the step of removing the barrier layer.
3. a SONOS cell transistor that adopts claim 1 or 2 described methods to make comprises some paired PMOS and NMOS, and said NMOS comprises:
Have the P type silicon substrate of some paired active areas, each is to being formed with raceway groove between the active area;
Grid is positioned at said raceway groove top, has silica-silicon-nitride and silicon oxide layer between the side wall of said grid, is polysilicon on said silica-silicon-nitride and silicon oxide layer;
The both sides of the periphery of said paired active area are respectively arranged with shallow channel isolation area;
It is characterized in that the paired active area of the active area of said NMOS comprises carborundum.
4. SONOS cell transistor according to claim 3 is characterized in that, said paired active area comprises source electrode and drain electrode.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110931491A (en) * | 2019-11-08 | 2020-03-27 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111463217A (en) * | 2020-04-09 | 2020-07-28 | 中国科学院微电子研究所 | Charge trapping memory and manufacturing method thereof |
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| US20050035409A1 (en) * | 2003-08-15 | 2005-02-17 | Chih-Hsin Ko | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
| US20070066087A1 (en) * | 2005-09-20 | 2007-03-22 | Dongbuanam Semiconductors Inc. | Method of manufacturing a semiconductor device |
| US20070173022A1 (en) * | 2006-01-20 | 2007-07-26 | Chih-Hao Wang | Defect-free SiGe source/drain formation by epitaxy-free process |
| US20090212347A1 (en) * | 2004-09-15 | 2009-08-27 | Koninklijke Philips Electronics N.V. | Sonos memory device with optimized shallow trench isolation |
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| CN1581508A (en) * | 2003-08-12 | 2005-02-16 | 台湾积体电路制造股份有限公司 | Semiconductor device its making method |
| US20050035409A1 (en) * | 2003-08-15 | 2005-02-17 | Chih-Hsin Ko | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
| US20090212347A1 (en) * | 2004-09-15 | 2009-08-27 | Koninklijke Philips Electronics N.V. | Sonos memory device with optimized shallow trench isolation |
| US20070066087A1 (en) * | 2005-09-20 | 2007-03-22 | Dongbuanam Semiconductors Inc. | Method of manufacturing a semiconductor device |
| US20070173022A1 (en) * | 2006-01-20 | 2007-07-26 | Chih-Hao Wang | Defect-free SiGe source/drain formation by epitaxy-free process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110931491A (en) * | 2019-11-08 | 2020-03-27 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN110931491B (en) * | 2019-11-08 | 2023-06-23 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111463217A (en) * | 2020-04-09 | 2020-07-28 | 中国科学院微电子研究所 | Charge trapping memory and manufacturing method thereof |
| CN111463217B (en) * | 2020-04-09 | 2023-04-18 | 中国科学院微电子研究所 | Charge trapping memory and manufacturing method thereof |
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