CN102130179A - Silicon-oxide-nitride-oxide-silicon (SONOS) device - Google Patents

Abstract

The invention discloses a silicon-oxide-nitride-oxide-silicon (SONOS) device. The SONOS device is characterized in that: a silicon carbide (20) is arranged on a well (10); the well (10) and the silicon carbide (20) form a hetero-junction; an oxide-nitride-oxide (ONO) layer (12) is arranged on the silicon carbide (20); the ONO layer (12) specifically comprises a silicon oxide (121) which is positioned below the ONO layer (12), a silicon nitride (122) which is positioned in the middle of the ONO layer (12) and a silicon oxide (123) which is positioned on the ONO layer (12); a polysilicon gate (13) and silicon nitride side walls (14) arranged on two sides of the polysilicon gate (13) are arranged on the ONO layer (12); light doping drain injection regions (15) are arranged in the well (10) below the two sides of the silicon nitride side walls (14); and drain injection regions (16) are arranged in the well (10) outside the silicon carbide (20) and the light doping drain injection regions (15). Made of a silicon carbide material, the silicon-oxide-nitride-oxide-silicon (SONOS) device has higher writing and erasing speeds at the same external voltage.

Description

The SONOS device

Technical field

The present invention relates to a kind of nonvolatile memory (NVM, non volatile memory), particularly relate to a kind of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon-oxide-nitride--silica-silicon) device.

Background technology

See also Fig. 1, this is the generalized section of traditional SONOS device.It on the p trap 10 ONO (Oxide-Nitride-Oxide, silica-silicon-nitride and silicon oxide) layer 12.ONO layer 12 specifically comprises silica 121, silicon nitride 122 in the middle of being positioned at that is positioned at the below and the silica 123 that is positioned at the top.It on the ONO layer 12 the silicon nitride side wall 14 of polysilicon gate 13 and both sides thereof.Has n type lightly doped drain injection region 15 in the p trap 10 of silicon nitride side wall 14 down either side.Have the n type in the p trap 10 and in 15 outsides, n type lightly doped drain injection region and leak injection region 16, as the source drain terminal of SONOS device.

The each several part structure doping type of SONOS device shown in Figure 1 is opposite, also be feasible.

When the SONOS device not being operated, being with as shown in Figure 2 of its p trap 10, silica 121, silicon nitride 122, silica 123, polysilicon 13, numerical value wherein only is signal.Contact potential difference between electronics in the p trap 10 (silicon) and the silica 121 (tunnel oxide) is φ 1.Contact potential difference between hole in the p trap 10 and the silica 121 is φ 2.

When above-mentioned SONOS device is carried out write operation, add positive voltage VPOS at polysilicon gate 13, source drain terminal 16 and p trap 10 ground connection so just form the tunnelling voltage difference VPOS from channel region (p trap 10) to polysilicon gate 13.Being with as shown in Figure 3 of this write operation, numerical value wherein only are signal.Under the effect that adds positive voltage VPOS, being with of SONOS device bends, as extra electric field EOT＞φ 1/XOT, when wherein XOT is the thickness of silica 121, the conduction band height of p trap 10 is higher than the conduction band height of silica 121, and electronics passes through silica 121 from p trap 10, F-N promptly takes place wear (Fowler-Nordheim tunneling then, the Fowler-Nordheim tunnelling), enter into silicon nitride 122 and being hunted down then.

When above-mentioned SONOS device is carried out write operation, add negative voltage VNEG at polysilicon gate 13, source drain terminal 16 and p trap 10 ground connection so just form the tunnelling voltage difference VNEG from channel region (p trap 10) to polysilicon gate 13.Being with as shown in Figure 4 of this erase operation, numerical value wherein only are signal.Under the effect that adds negative voltage VNEG, being with of ONOS device bends, as extra electric field EOT＞φ 2/XOT, when wherein XOT is the thickness of silica 121, the conduction band height of p trap 10 is higher than the conduction band height of silica 121, silica 121 is passed through in the hole from p trap 10, F-N promptly takes place wear then, enters into silicon nitride 122 then and is hunted down.

Under the certain condition of the membranous and thickness of ONO layer 12, existing SONOS device write and erasing speed depend on the effective mass in electronics in the silicon (being p trap 10) or hole and p trap 10 near the electronics on the surface of silica 121 1 sides or hole and silica 121 between contact potential difference.

Summary of the invention

Technical problem to be solved by this invention provides a kind of SONOS device, has to write faster and erasing speed.

For solving the problems of the technologies described above, SONOS device of the present invention is: be carborundum (SiC) 20 on the trap 10, p trap 10 and carborundum 20 form a heterojunction; It on the carborundum 20 ONO layer 12; ONO layer 12 specifically comprises silica 121, silicon nitride 122 in the middle of being positioned at that is positioned at the below and the silica 123 that is positioned at the top; It on the ONO layer 12 the silicon nitride side wall 14 of polysilicon gate 13 and both sides thereof; Has lightly doped drain injection region 15 in the trap 10 of silicon nitride side wall 14 down either side; Has the injection region 16 of leakage in the trap 10 and at the carborundum 20 and 15 outsides, lightly doped drain injection region.

In the above-mentioned SONOS device, trap 10 is the p type; Lightly doped drain injection region 15, leakage injection region 16, carborundum 20 are the n type.

Perhaps, in the above-mentioned SONOS device, trap 10 is the n type; Lightly doped drain injection region 15, leakage injection region 16, carborundum 20 are the p type.

SONOS device of the present invention, increase one deck carborundum in the silicon surface, utilize the contact potential difference between that carbofrax material obtains the effective mass in lower electronics or hole and littler electronics or hole and the tunnel oxidation layer, thereby under identical applied voltage, obtain to write more fast and erasing speed.

Description of drawings

Fig. 1 is the generalized section of existing SONOS device;

Fig. 2 be existing SONOS device can be with schematic diagram;

Fig. 3 is that existing SONOS device can be with schematic diagram when write operation;

Fig. 4 is that existing SONSO device can be with schematic diagram when erase operation;

Fig. 5 is the generalized section of SONOS device of the present invention.

Description of reference numerals among the figure:

10 is the p trap; 12 is the ONO layer; 121 is silica; 122 is silicon nitride; 123 is silica; 13 is polysilicon gate; 14 is the silicon nitride side wall; 15 is n type lightly doped drain injection region; 16 for leaking the injection region in the source; 20 is carborundum.

Embodiment

F-N tunnelling current density formula is as follows:

$J=\mathrm{\&alpha;}\&times;{\mathrm{<figure-callout\; id="2"\; label="EOT"\; filenames="H2010100273265E00012.png,H2010100273265E00022.png"\; state="\{\{state\}\}">EOT</figure-callout>}}^2\&times;e^{\frac{-\mathrm{\&beta;}}{\mathrm{EOT}}}$

$\mathrm{\&alpha;}=\frac{q^3\&times;m}{8\&times;\mathrm{\&pi;}\&times;\mathrm{\&phi;}\&times;b\&times;\mathrm{ma}}$

$\mathrm{EOT}=\frac{\mathrm{\&phi;}}{\mathrm{XOT}}$

$\mathrm{\&beta;}=\frac{4\&times;\sqrt{2\&times;\mathrm{ma}}\&times;{\mathrm{\&phi;}}^{\frac{3}{2}}}{3\&times;b\&times;q}$

Wherein J is a F-N tunnelling current density, and EOT is an extra electric field, and b is a Planck's constant, and q is the electric charge of single electronics, and m is the effective mass of an electronics, and ma is SiO ₂The forbidden band in the effective mass of an electronics, φ gets φ 1 or φ 2, XOT is the thickness of tunnel oxide (silica 121).

When φ gets φ 1, calculating be the write operation of SONOS device the time, the current density of F-N tunnelling takes place in electronics.

When φ gets φ 2, calculating be SONOS device erase operation the time, the current density of F-N tunnelling takes place in the hole.

According to formula, under the situation that does not change operating voltage, the effective way that increases F-N tunnelling current density is for reducing electronics or hole effective mass ma.Increase F-N tunnelling current density, just mean and improve writing and erasing speed of SONOS device.

If φ 1 or φ 2 reduce, just mean the starting voltage that can reduce to take place the F-N tunnelling, thereby reduce the requirement of withstand voltage of SONOS device.

See also Fig. 5, this is the generalized section of SONOS device of the present invention.Be carborundum 20 on the p trap 10, formed a PN heterojunction between p trap 10 and the carborundum 20.It on the carborundum 20 ONO layer 12.ONO layer 12 specifically comprises silica 121, silicon nitride 122 in the middle of being positioned at that is positioned at the below and the silica 123 that is positioned at the top.It on the ONO layer 12 the silicon nitride side wall 14 of polysilicon gate 13 and both sides thereof.Has n type lightly doped drain injection region 15 in the p trap 10 of silicon nitride side wall 14 down either side.Has n type leakage injection region 16 in the p trap 10 and at the carborundum 20 and 15 outsides, n type lightly doped drain injection region, as the source drain terminal of SONOS device.

The each several part structure doping type of SONOS device shown in Figure 5 is opposite, also be feasible.

Compare with traditional SONOS device, the present invention has increased carborundum 20 at the channel region of p trap 10, thereby with the raceway groove of carborundum 20 as whole SONOS device.

Contact potential difference φ 1 ' between the electronics of carborundum 20 and the tunnel oxide (being silica 121) is than electronics in the silicon (being p trap 10) and the 1 little 0.05eV of the contact potential difference φ between the tunnel oxide.

Hole in the carborundum 20 and the contact potential difference φ 2 ' between the tunnel oxide are than hole in the silicon and the 2 little 1.45eV of the contact potential difference φ between the tunnel oxide.

The electronics in the carborundum 20 or the effective mass ma ' in hole are littler by about 50% than the effective mass ma in electronics in the silicon or hole.

More than three aspects all can make SONOS device of the present invention under same applied voltage, obtain F-N tunnelling current density much larger than traditional SONOS device.

Particularly, for the write operation of SONOS device, because φ 1 ' reduces 2.7% than φ 1, ma ' reduces 50% than ma, and the present invention can make the F-N tunnel current density of electronics increase by 90%.

For the erase operation of SONOS device, because φ 2 ' reduces 8.2% than φ 2, ma ' reduces 50% than ma, and the present invention can make the F-N tunnel current density in hole increase by 30%.

Because φ 1 ' reduces 2.7% than φ 1, and φ 2 ' reduces 8.2% than φ 2, the present invention also can make and write the corresponding reduction by 3%～8% with erasing voltage VNEG of voltage VPOS simultaneously.

Write and wipe of the integration decision of the charge Q of as much by current density, J and time t.

Q＝∫Jdt

Therefore under the situation that obtains same effect (electric charge), the present invention can reduce time of writing and wiping, has promptly improved the speed that writes and wipe.Simultaneously, the present invention can also reduce writing with erasing voltage of SONOS device.

Claims (3)

1. a SONOS is characterized in that, is carborundum (20) on the trap (10), and trap (10) and carborundum (20) form a heterojunction; On the carborundum (20) ONO layer (12); ONO layer (12) specifically comprise silica (121), the silicon nitride (122) in the middle of being positioned at that is positioned at the below and be positioned at above silica (123); It on the ONO layer (12) the silicon nitride side wall (14) of polysilicon gate (13) and both sides thereof; Has lightly doped drain injection region (15) in the trap (10) of silicon nitride side wall (14) down either side; Has leakage injection region (16) in the trap (10) and at carborundum (20) and lightly doped drain injection region (15) outside.

2. SONOS according to claim 1 is characterized in that, in the described SONOS device, trap (10) is the p type; Lightly doped drain injection region (15), leakage injection region (16), carborundum (20) are the n type.

3. SONOS according to claim 1 is characterized in that, in the described SONOS device, trap (10) is the n type; Lightly doped drain injection region (15), leakage injection region (16), carborundum (20) are the p type.

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