CN102543873B

CN102543873B - Autoregistration P+ shallow junction doping process

Info

Publication number: CN102543873B
Application number: CN201010605394.5A
Authority: CN
Inventors: 桂林春; 张明敏; 邵永军; 王乐
Original assignee: CSMC Technologies Corp
Current assignee: CSMC Technologies Corp
Priority date: 2010-12-27
Filing date: 2010-12-27
Publication date: 2015-08-19
Anticipated expiration: 2030-12-27
Also published as: CN102543873A

Abstract

The present invention is about a kind of autoregistration P+ shallow junction doping process, it comprises step: 1) N+ photoetching/N+ injects: on the P-type silicon substrate P-SUB being formed with P type trap PW and N-type trap NW, photoresist PR and field oxide FOX, carry out the photoetching of N-type impurity source electrode and inject, and forms N+ source electrode and the N+ drain electrode of P type trap; 2) depositing silica at low pressure (LPTEOS) deposition: deposit one deck LPTEOS at silicon chip surface; 3) P+S/D photoetching/corrosion: p type impurity drain electrode photoetching and corrosion; After this step, what there occurs compared with previous step.4) N+S/D annealing (P+S/D doping): carry out furnace anneal under BH3 atmosphere, thus reach P+ region doping and N+ doping activation; 5) P+ source electrode and the P+ drain electrode of N-type trap is formed.By autoregistration P+ shallow junction doping process, achieve P+ source-drain area shallow junction, reduce junction capacitance and overlap capacitance.

Description

Autoregistration P+ shallow junction doping process

[technical field]

The present invention relates to CMOS source-drain area formation process method, particularly relate to a kind of process adopting solid-source doping method to form CMOS source-drain area.

[background technology]

Along with reducing of device feature size, junction depth requires more and more shallow, namely requires shallow junction even for ultra-shallow junctions.Shallow junction is in substrate, form the shallow degree of depth, has high concentration and overactivity rate dopant, and has the knot of abrupt junction section in the horizontal and vertical directions.

Shallow junction is formed by ion implantation or solid phase diffusion method usually.In ion implantation, the high accelerating voltage accelerated impurity ion of ion implantor, is then injected in substrate by foreign ion, forms shallow junction.In solid phase diffusion method, substrate forms solid-state diffusion source, the dopant then in solid-state diffusion source spreads and mixes in substrate, forms shallow junction.

Referring to Fig. 1 to Fig. 3, is all that the mode adopting N+ photoetching/injections-> P+ photoetching/injection-> source-drain area to anneal is to realize the source-drain area of metal-oxide-semiconductor in the process that traditional deep-submicron CMPS technique is formed at source-drain area.But the boron of the P+ source-drain area that this mode is formed follow-up source and drain annealing thermal process in because its diffusion rate is much larger than arsenic, therefore the P+ junction depth in CMOS technology is always greater than N+ junction depth, simultaneously because diffusion rate accelerates the horizontal proliferation that causes seriously, therefore the channel length of PMOS always prevents channel punchthrough slightly larger than NMOS channel length.In addition, the horizontal proliferation of P+ source-drain area seriously also can make the overlapping size of source-drain area and grid increase, and causes the overlap capacitance of source-drain area and grid to increase and the increase of junction capacitance, thus reduces the switching speed of logical circuit and the transient response of RF circuit.

Therefore, need to provide a kind of process forming shallow junction source-drain area CMPS.

[summary of the invention]

The object of the present invention is to provide a kind of autoregistration P+ shallow junction doping process, it achieves P+ source-drain area shallow junction, reduces junction capacitance and overlap capacitance, improves device performance.

For achieving the above object, the invention relates to a kind of autoregistration P+ shallow junction doping process, it comprises step:

1) N+ photoetching/N+ injects: on the P-type silicon substrate P-SUB being formed with P type trap PW and N-type trap NW, photoresist PR and field oxide FOX, carry out the photoetching of N-type impurity source-drain electrode and inject, and forms N+ source electrode and the N+ drain electrode of P type trap;

2) depositing silica at low pressure (LPTEOS) deposition: deposit one deck LPTEOS in surface of silicon;

3) P+S/D photoetching/corrosion: refer to Fig. 6, the photoetching of p type impurity source-drain electrode and corrosion, etch away the LPTEOS in P+ region;

4) N+S/D annealing and P+S/D doping: carry out furnace anneal under BH3 atmosphere, thus reach P+ region doping and N+ doping activation;

5) P+ source electrode and the P+ drain electrode of N-type trap is formed.

As a further improvement on the present invention, in described annealing steps, main thermal process is used for boron to silicon chip surface diffusion from BH3 atmosphere, and the atom of High temperature diffusion doping is activated.

The invention has the beneficial effects as follows: by autoregistration P+ shallow junction doping process, achieve P+ source-drain area shallow junction, reduce junction capacitance and overlap capacitance.

[accompanying drawing explanation]

Fig. 1 is the process schematic representation of N+ photoetching/injection in cmos process flow in prior art;

Fig. 2 is the process schematic representation of P+ photoetching/injection in cmos process flow in prior art;

Fig. 3 is that in prior art, in cmos process flow, S/D anneals and forms the process schematic representation of resulting devices CMOS;

Fig. 4 is the schematic diagram of N+ photoetching/N+ injection technology in autoregistration P+ shallow junction doping process of the present invention;

Fig. 5 is the schematic diagram of LPTEOS depositing operation in autoregistration P+ shallow junction doping process of the present invention;

Fig. 6 is the schematic diagram of P+S/D photoetching/etching process in autoregistration P+ shallow junction doping process of the present invention;

Fig. 7 is the schematic diagram of N+S/D annealing (P+S/D doping) technique in autoregistration P+ shallow junction doping process of the present invention;

Fig. 8 is the pattern schematic diagram of the device CMOS that autoregistration P+ shallow junction doping process of the present invention is finally formed.

[embodiment]

Autoregistration P+ shallow junction doping process of the present invention comprises the following steps:

N+ photoetching/N+ injects: refer to Fig. 4, the P-type silicon substrate P-SUB being formed with P type trap PW and N-type trap NW, photoresist PR and field oxide FOX carries out the photoetching of N-type impurity source-drain electrode and injects, and forms N+ source electrode and the N+ drain electrode of P type trap;

Depositing silica at low pressure (LPTEOS) deposits: refer to Fig. 5, deposit one deck LPTEOS in surface of silicon;

P+S/D photoetching/corrosion: refer to Fig. 6, the photoetching of p type impurity source-drain electrode and corrosion, etch away the LPTEOS in P+ region;

N+S/D annealing and P+S/D doping: refer to Fig. 7, under BH3 atmosphere, carry out furnace anneal, thus reach P+ region doping and N+ doping activation.In annealing process, main thermal process is used for boron to silicon chip surface diffusion from BH3 atmosphere, and the atom of High temperature diffusion doping is activated, and activates, therefore achieve P+ shallow junction object without the need to subsequent thermal process.The As in N+ region is because there is LPTEOS to protect simultaneously, so can not disturb by boron element, does not also have the risk of doped chemical outdiffusion.

Resulting devices shape appearance figure as shown in Figure 8, therefore forms P+ source electrode and the P+ drain electrode of N-type trap.

Special needs to be pointed out is, in the specific embodiment of the invention only with this autoregistration P+ shallow junction doping process exemplarily, the autoregistration P+ shallow junction doping process of any type is all suitable for the principle that the present invention discloses in actual applications.For the person of ordinary skill of the art, done for equivalence change of the present invention under the teachings of the present invention, must be included in the scope that the claims in the present invention advocate.

Claims

1. an autoregistration P+ shallow junction doping process, it comprises step:

3) P+S/D photoetching/corrosion: the photoetching of p type impurity source-drain electrode and corrosion, etches away the LPTEOS in P+ region;

5) P+ source electrode and the P+ drain electrode of N-type trap is formed.

2. autoregistration P+ shallow junction doping process as claimed in claim 1, is characterized in that, in described annealing steps, main thermal process is used for boron to surface of silicon diffusion from BH3 atmosphere, and the atom of High temperature diffusion doping is activated.