CN102543853A - Dummy metal filling method and integrated circuit layout structure - Google Patents
Dummy metal filling method and integrated circuit layout structure Download PDFInfo
- Publication number
- CN102543853A CN102543853A CN2011104606981A CN201110460698A CN102543853A CN 102543853 A CN102543853 A CN 102543853A CN 2011104606981 A CN2011104606981 A CN 2011104606981A CN 201110460698 A CN201110460698 A CN 201110460698A CN 102543853 A CN102543853 A CN 102543853A
- Authority
- CN
- China
- Prior art keywords
- metal
- redundant
- redundant metal
- zone
- interconnection line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a dummy metal filling method. According to the invention, a plurality of dummy metals are filled in an area required to be filled by the dummy metals including first dummy metals and second dummy metals; the filling area of each first dummy metal is larger than that of each second dummy metal; and the second dummy metals are positioned between interconnection lines of the first dummy metals and the area where the dummy metals are positioned. Accordingly, the invention further provides an integrated circuit layout structure. Through the dummy metal filling method provided by the invention, the thickness consistency of an integrated circuit layout is realized, and the capacitance increment between the interconnection lines of an integrated circuit is reduced at the same time, the function of the chip is prevented from being damaged due to the introduction of the dummy metals, the dummy metals in different areas can be filled in the area required to be filled by the dummy metals, the filling number of the dummy metals is reduced, and other calculation data quality is reduced.
Description
Technical field
The present invention relates to integrated circuit manufacturing and field of electron design automation, be specifically related to integrated circuit diagram is carried out redundant metal filled method and integrated circuit layout structure.
Background technology
At integrated circuit (Integrated Circuit; IC) in the manufacture process; Metal, dielectric and other materials are used the surface that is produced on silicon chip like physical vapour deposition (PVD), chemical vapour deposition (CVD) at interior the whole bag of tricks; Formation comprises the structured metal layer of the metal interconnecting wires between electronic component and the element, links to each other with a plurality of metal filled through holes between every layer of structured metal layer, makes integrated circuit have very high complexity and current densities.In the manufacturing of each layer structured metal layer; In order to guarantee the evenness on structured metal layer surface; Usually use chemico-mechanical polishing (Chemical Mechanical Polishing; CMP) technology is come planarization material and dielectric layer surface by the chemical corrosion effect of polishing fluid and the abrasive action of ultramicron.
When the integrated circuit technology node is reduced to below the 90nm; Especially arrive 65nm and 45nm when following; Surface smoothness after the CMP process highlights the dependence problem of underlying metal pattern, owing to the different height change that produce of underlying metal pattern can be greater than 30%.Simultaneously CMP technology is also brought the problem that metal and dielectric layer surface topography change, and forms metal dish and dielectric layer erosion, these problems also with integrated circuit diagram in metal interconnected live width relevant with distance between centers of tracks.For reduce as far as possible domain in the CMP process each layer circuit surface evenness to the dependence of underlying metal pattern; Method in common is before the CMP process at present; Some zones on integrated circuit diagram; For example fill redundant metal at a distance of certain distance, improve each layer structured metal layer surface smoothness after the CMP process at interconnection line density less zone and interconnection line.The metal filled method of the existing redundancy of integrated circuit foundries be in all zones according to filling with a kind of fill pattern, i.e. a plurality of redundant metals of each zone filling with same shape, size and spacing.
Fill redundant metal at integrated circuit,, the electric capacity between interconnection line is increased owing to added unnecessary metal between metal interconnecting wires.The increase of interconnection line capacitance can influence the signal integrity of integrated circuit, and (Signal Integrity SI), and then causes the capability error of integrated circuit.Along with constantly reducing of integrated circuit technology node, the electronic component in the circuit is more and more meticulousr, and the filling of redundant metal can not be ignored the influence of interconnection line capacitance.It is metal filled how in side circuit, to carry out redundancy targetedly, make the thickness of integrated circuit after the CMP process consistent as far as possible, and the recruitment of the line capacitance that will interconnect is controlled at the problem that has become a key in the acceptable scope.And existingly at present general fill a plurality of redundant metal process with same shape, size and spacing in each zone, and only consider the consistency of thickness after the CMP process, consider the increase of interconnection line capacitance.The applicant finds in research process, adopts general redundant metal filled method at present, makes that capacitance increase can reach great percentage between interconnection line, can not satisfy the as far as possible little requirement of increment of the line capacitance that interconnects well.
Summary of the invention
Fill behind the redundant metal the excessive problem of capacitance increase between interconnection line in order to solve integrated circuit, the present invention proposes a kind of method of filling the redundant metal of different area in zones of different.
In order to achieve the above object, the present invention provides a kind of redundancy metal filled method, comprises step:
Integrated circuit diagram to be filled is provided, and said integrated circuit diagram comprises at least one structured metal layer;
Confirm that according to the figure of each said structured metal layer needs fill the zone of redundant metal, said area distribution has interconnection line;
Fill several redundant metals in said zone; In said several redundant metals; Comprise the first redundant metal and the second redundant metal; The filling area of each said first redundant metal is greater than the filling area of each said second redundant metal, and the said second redundant metal is between the said first redundant metal and said interconnection line.
Correspondingly, the present invention also provides a kind of integrated circuit layout structure, comprises at least one structured metal layer and several redundant metals, wherein,
Comprise the zone of the redundant metal of needs filling in the said structured metal layer, said zone comprises interconnection line;
Said several redundant metals are positioned at said zone; Comprise the first redundant metal and the second redundant metal in said several redundant metals; The filling area of each said first redundant metal is greater than the filling area of each said second redundant metal, and the said second redundant metal is between the said first redundant metal and said interconnection line.
Compared with prior art, the present invention has advantage:
The present invention proposes the metal filled method of a kind of redundancy; The technical scheme of this method is to fill at needs to fill several redundant metals in the zone of redundant metal; Wherein, near the filling area of the redundant metal of interconnection line less than filling area away from the redundant metal of same interconnection line.Compared with prior art, adopt the redundant metal process of filling of the present invention, reduced the increase of electric capacity between integrated circuit interconnection line when realizing the integrated circuit diagram consistency of thickness.At the IC chip that adopts this method to make, can guarantee that when guaranteeing the chip flatness function of chip can not destroyed because of the introducing of redundant metal.
In addition, method of the present invention is filled the redundant metal that filling area varies in size in the zone of redundant metal at needs, has reduced redundant metal filled quantity.The existing filling needs in the redundant metal process to fill the bulk redundancy metal, makes that the mask data amount is excessive, increased computational burden.Compared with prior art, the computational burden of method of the present invention is less.
Description of drawings
Shown in accompanying drawing, of the present invention above-mentioned and other purposes are more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention according to actual size equal proportion convergent-divergent.
Fig. 1 is the flow chart of the redundant metal filled method of the present invention;
Fig. 2 is the area schematic that needs to fill redundant metal in the embodiment of the invention;
Fig. 3 fills redundant metal sketch map in the embodiment of the invention;
Fig. 4 is for to fill square redundant metal sketch map with interconnection line close together position;
Fig. 5 fills the redundant metal sketch map of rectangle with the interconnection line distance than distant positions.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention will be carried out clear, intactly description.Obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Secondly; The present invention combines sketch map to be described in detail; When the embodiment of the invention was detailed, for ease of explanation, the interconnection line in the said sketch map can be disobeyed general ratio with the sketch map of filling metal and done local the amplification; And said sketch map is example, and it should not limit the scope of the present invention's protection at this.In plane graph, square redundant metal is meant that the redundant metal filled zone that occupies is square, and the redundant metal of rectangle is meant that the redundant metal filled zone that occupies is a rectangle.After actual integrated circuit manufacturing was accomplished, redundant metal filled space was a solid space, and the cross section of redundant metal is a square or rectangular.
The metal filled method of the existing redundancy of integrated circuit foundries be in all zones according to filling with a kind of fill pattern, i.e. a plurality of redundant metals of each zone filling with same shape, size and spacing.The applicant finds in research process; Capacitance increase is excessive between at present general redundant metal process filling back interconnection line; Sometimes great percentage can be reached, the as far as possible little requirement of increment of the consistent as far as possible and interconnection line capacitance of the thickness of integrated circuit after the CMP process can not be satisfied well.
Fill behind the redundant metal the excessive problem of capacitance increase between interconnection line in order to solve integrated circuit; The present invention proposes the metal filled method of a kind of redundancy; The technical scheme of this method is to fill at needs to fill several redundant metals in the zone of redundant metal; Wherein, near the filling area of the redundant metal of interconnection line less than filling area away from the redundant metal of same interconnection line.Compared with prior art, adopt the redundant metal process of filling of the present invention, reduced the increase of electric capacity between integrated circuit interconnection line when realizing the integrated circuit diagram consistency of thickness.At the IC chip that adopts this method to make, can guarantee that when guaranteeing the chip flatness function of chip can not destroyed because of the introducing of redundant metal.
In addition, method of the present invention is filled the redundant metal that filling area varies in size in the zone of redundant metal at needs, has reduced redundant metal filled quantity.The existing filling needs in the redundant metal process to fill the bulk redundancy metal, makes that the mask data amount is excessive, increased computational burden.Compared with prior art, the computational burden of method of the present invention is less.
The idiographic flow of the metal filled method of redundancy of the present invention is seen Fig. 1, comprises step:
Step S1 provides integrated circuit diagram to be filled, and said integrated circuit diagram comprises at least one structured metal layer.
Integrated circuit diagram to be filled can comprise one or more structured metal layers, comprises the metal interconnecting wires between electronic component and the element in each structured metal layer.Integrated circuit diagram to be filled can be the domain that provides with the electric design automation file format, the domain that particularly provides with the GDS form.
Step S2 confirms that according to the figure of each said structured metal layer needs fill the zone of redundant metal, and said area distribution has interconnection line.
For the evenness on every layer of structured metal layer guaranteeing integrated circuit diagram surface after the CMP process, on the figure of every layer of structured metal layer of integrated circuit diagram to be filled, confirm to need to fill the zone of redundant metal.The zone of redundant metal to be filled is generally the lower zone of interconnection line density, or the analog result of simulation tool such as CMP simulation tool is metal dish, dielectric layer corrodes or surface height difference is bigger hot spot region etc. to occur.
The middle part, zone that the needs of determining are filled redundant metal can be distributed with interconnection line, also can be distributed with an interconnection line or a plurality of interconnection line on the edge of.
In the reality; Confirm that there is several different methods in the zone that needs to fill redundant metal; Can confirm according to the interconnection line density of integrated circuit diagram, also can confirm, perhaps can confirm according to the design rule of integrated circuit foundries according to the thickness difference of interconnection line after the CMP technology of integrated circuit diagram.
Step S3; Fill several redundant metals in said zone; In said several redundant metals; At least comprise one the first redundant metal and the second redundant metal, the filling area of each said first redundant metal is greater than the filling area of each said second redundant metal, and the said second redundant metal is between the said first redundant metal and said interconnection line.
In order to guarantee in the evenness on every layer of structured metal layer guaranteeing integrated circuit diagram surface after the CMP process that the capacitance increase between interconnection line is less; Fill at needs and to fill a plurality of redundant metals in the zone of redundant metal; Wherein, At the first bigger redundant metal of distance interconnection linear distance position filling area far away, at the second less redundant metal of the nearer position filling area of distance interconnection linear distance.
Introduce the metal filled method of redundancy of the present invention below in conjunction with accompanying drawing in detail with an embodiment:
At first, with the GDS form integrated circuit diagram to be filled is provided, this integrated circuit diagram comprises a structured metal layer.
The zone that the needs of confirming integrated circuit diagram to be filled are filled redundant metal is the equivalent thickness and the bigger zone of interconnection line deposit thickness difference of interconnection line; Can provide the equivalent thickness of interconnection line and the setting range of interconnection line deposit thickness difference in advance; Can be preferably the equivalent thickness of interconnection line and the interconnection line deposit thickness difference of integrated circuit diagram to be filled and fill redundant metal, confirm that interconnection line equivalent thickness detailed process is following greater than 10% zone:
At first, integrated circuit diagram to be filled is divided into grid, obtains the equivalent live width and the equivalent separation of interconnection line in each grid, wherein
The equivalence live width can adopt weighted-average method to calculate
Wherein, W
EffBe equivalent live width, W
iBe a certain interconnection line live width that comprises in the grid, A
iFor live width is W
iInterconnection line occupied area ratio in the interconnection line area of grid.
Equivalent separation can adopt computes following:
Wherein, S
EffBe the equivalent line spacing, ρ is the ratio that the interconnection line area occupies the gross area in the grid.
Secondly, measure and the erosion medium resistance amount with the metal dish that equivalent separation obtains said grid according to the equivalent live width of interconnection line in the CMP process parameter of integrated circuit diagram and the grid;
The CMP process parameter of integrated circuit diagram comprises the CMP process processing time, interconnection line metal removal rate, dielectric layer clearance etc.
Metal dish amount D
MCan adopt following calculating formula to calculate:
D
M＝D
ss(1-e
-t/τ)
Erosion medium resistance amount E
OXCan adopt following calculating formula to calculate:
E
OX＝Y
1t+Y
2D
ss(e
-t/τ-1)
Wherein,
d
max＝A×(W
eff)
α×(S
eff)
β
Wherein, t is the CMP process processing time, r
MBe interconnection line metal removal rate, r
OxBe dielectric layer clearance, d
MaxBe the maximum dish amount of interconnection line metal, A, α, β are fitting parameter.
At last, extract the interconnection line equivalent thickness of grid, the interconnection line equivalent thickness of grid equals deposit thickness and deducts the dish-shaped erosion medium resistance amount that deducts again of measuring of metal.The design object thickness of interconnection line when wherein, deposit thickness is the integrated circuit diagram manufacturing.
The method of said extracted grid interconnect line equivalent thickness has been considered the influence to metal interconnecting wires thickness of circuitous pattern in the integrated circuit diagram and underlying metal pattern; Also considered simultaneously to occur metal dish and dielectric layer and corroded influence, can obtain interconnection line equivalent thickness more accurately metal interconnecting wires thickness in the integrated circuit diagram.
Can draw like this integrated circuit diagram to be filled through CMP technology after the interconnection line equivalent thickness and the deposit thickness difference of two ways bigger.
Referring to Fig. 2; For integrated circuit diagram through the equivalent thickness of the interconnection line confirmed according to said method after the CMP process and a bigger zone of interconnection line deposit thickness difference of integrated circuit diagram to be filled; This regional edge comprises two interconnection lines 100, and the middle part in this zone i.e. space between interconnection line 200 (shown in the frame of broken lines) is the position of the redundant metal of filling.
In the present embodiment, fill the redundant metal of two groups of different area in zone shown in Figure 2, wherein; One group of redundant metal is a rectangle, and another group is for square, referring to Fig. 3; Wherein, First group of redundant metal 301 of 6 rectangles, the length of side of the redundant metal of each rectangle all is the wide 0.8 μ m of long 2.4 μ m, the length direction of each redundant metal is along the length direction of interconnection line 100; Second group of redundant metal 302 of 24 squares, the length of side of each square redundant metal all is 0.2 μ m, square redundant metal 302 can be 0.14 μ m to 0.35 μ m with the minimum distance of interconnection line 100.First group of redundant Metal Substrate originally is positioned at the centre of two interconnection lines; 12 redundant metals of square of second group are between first group redundant metal and interconnection line, and other 12 redundant metals of square of second group are between first group redundant metal and another interconnection line.
In the conventional redundant metal filled method, filling in the zone of redundant metal at the needs of integrated circuit diagram, fill the redundant metal of a plurality of squares, is 0.8 μ m like the length of side of each square redundant metal.Scheme of the present invention is the redundant metal less with the position filling area of interconnection line close together; In order to reduce redundant metal filled quantity; Reduce other operands; At the position filling area bigger redundant metal far away with interconnection line distance, for example the length of side be the square of 0.2 μ m redundant metal filled with the position of interconnection line close together, length be 2.4 μ m wide be the rectangle of 0.8 μ m redundant metal filled with interconnection line distance position far away.In order to check the influence of method of the present invention to the interconnection line capacitance, the applicant measures the interconnection line capacitance of the redundant metal that the zones of different filling area does not wait.Referring to Fig. 4, with the zone 210 of interconnection line 110 close together in fill the square redundant metal that the length of side equates, filling the length of side respectively is that 0.8 μ m and 0.2 μ m are square; After manufacturing process such as CMP, measure the electric capacity between the interconnection line 110, listed in the table 1 fill the redundant metal of different length of sides squares after; The erosion medium resistance amount that produces, metal dish amount and interconnection line capacitance; Wherein, except that filling the varying in size of redundant metal, other conditions are all identical.
Interconnection line capacitance when table 1. is filled the redundant metal of different length of sides squares
From table 1, can find out; Filling the less square redundant metal of the length of side with the position of interconnection line close together; Other conditions of making integrated circuit are all identical, and measuring and fill the length of side capacity ratio between interconnection line when being the square redundant metal of 0.2 μ m, to fill the length of side be that the square redundant metal of 0.8 μ m is little by about 35%.
Referring to Fig. 5, and interconnection line 120 between need to fill in the space 220 middle distance interconnection lines of the redundant metal zone far away and fill rectangle 320 redundant metals or square redundant metal, after manufacturing process such as CMP; Measure the electric capacity between the interconnection line 120; After having listed filling rectangle or square redundant metal in the table 2, the erosion medium resistance amount of generation, metal dish amount and interconnection line capacitance, wherein; Except that the shape difference of filling redundant metal, other conditions are all identical.
Interconnection line capacitance when table 2. is filled difformity redundancy metal
From table 2, can find out; With interconnection line distance position far away fill square redundant metal that the length of side is 0.8 μ m or length be 2.4 μ m wide be the rectangle of 0.8 μ m; Other conditions of making integrated circuit are all identical, and the square redundant metal that measures and fill length the capacity ratio filling length of side between interconnection line when to be that 2.4 μ m are wide be the redundant metal of the rectangle of 0.8 μ m and be 0.8 μ m is little by about 4%.
Test result in consolidated statement 1 and the table 2; The less square redundant metal of the length of side is filled in the position of selection of the present invention and interconnection line close together; Fill the redundant metal of the bigger rectangle of the length of side with interconnection line distance position far away; Can reduce the capacitance increase between interconnection line, can also reduce the quantity of filling redundant metal simultaneously, the operational data amount of reduction mask etc.
Present embodiment redundant metal filled in the zone that comprises 2 interconnection lines, a plurality of second is redundant metal filled in the first redundant metal both sides.The edge comprises that the needs of interconnection line fill the zone of redundant metal multiple situation is arranged in the reality, fills the edges of regions of redundant metal if desired and has only 1 interconnection line, and then the second redundant metal is between the first redundant metal and interconnection line.
Correspondingly, the present invention also provides a kind of integrated circuit layout structure, and said integrated circuit layout structure comprises at least one structured metal layer and several redundant metals, wherein,
Comprise the zone of the redundant metal of needs filling in the said structured metal layer, said zone comprises interconnection line;
Said several redundant metals are positioned at said zone; Comprise the first redundant metal and the second redundant metal in said several redundant metals; The filling area of each said first redundant metal is greater than the filling area of each said second redundant metal, and the said second redundant metal is between the said first redundant metal and said interconnection line.
Said structured metal layer comprises the metal interconnecting wires between electronic component and the element for realizing the basic structure of integrate circuit function.Said redundant metal be for reduce as far as possible structured metal layer in processes such as CMP each layer circuit surface evenness to the dependence of underlying metal pattern.
Preferably; Need the edge distribution in the zone of the redundant metal of filling that a plurality of interconnection lines are arranged; Comprise the second redundant metal that one said first redundant metal and a plurality of area equate at the middle part in said zone, all comprise the said second redundant metal between the said first redundant metal and each interconnection line.
Preferably; Need the edge distribution in the zone of the redundant metal of filling that a plurality of interconnection lines are arranged; Comprise the said second redundant metal that the said first redundant metal that a plurality of areas equate and a plurality of area equate at the middle part in said zone, all comprise the second redundant metal that said area equates between the said first redundant metal that each area equates and each interconnection line.
Preferably; Need the edge distribution in the zone of the redundant metal of filling that an interconnection line is arranged; Comprise the said second redundant metal that one said first redundant metal and a plurality of area equate at the middle part in said zone, the second redundant metal that said a plurality of areas equate is between the said first redundant metal and a said interconnection line.
Preferably, comprise rectangle first redundant metal and/or the square second redundant metal in the zone that needs are filled redundant metal.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention to any simple modification, equivalent variations and modification that above embodiment did, all still belongs to the scope of technical scheme protection of the present invention according to technical spirit of the present invention.
Claims (10)
1. the metal filled method of redundancy is characterized in that, comprises step:
Integrated circuit diagram to be filled is provided, and said integrated circuit diagram comprises at least one structured metal layer;
Confirm that according to the figure of each said structured metal layer needs fill the zone of redundant metal, said area distribution has interconnection line;
Fill several redundant metals in said zone; In said several redundant metals; Comprise the first redundant metal and the second redundant metal; The filling area of each said first redundant metal is greater than the filling area of each said second redundant metal, and the said second redundant metal is between the said first redundant metal and said interconnection line.
2. the metal filled method of redundancy according to claim 1; It is characterized in that; The edge distribution in said zone has a plurality of interconnection lines; Fill the second redundant metal that one said first redundant metal and a plurality of area equate at the middle part in said zone, all comprise the said second redundant metal between the said first redundant metal and each interconnection line.
3. the metal filled method of redundancy according to claim 1; It is characterized in that; The edge distribution in said zone has a plurality of interconnection lines; Fill the said second redundant metal that the said first redundant metal that a plurality of areas equate and a plurality of area equate at the middle part in said zone, all comprise the second redundant metal that said area equates between the said first redundant metal that each area equates and each interconnection line.
4. the metal filled method of redundancy according to claim 1; It is characterized in that; The edge distribution in said zone has an interconnection line; Fill the said second redundant metal that one said first redundant metal and a plurality of area equate at the middle part in said zone, the second redundant metal that said a plurality of areas equate is between the said first redundant metal and a said interconnection line.
5. according to the metal filled method of each described redundancy of claim 1 to 4, it is characterized in that, fill rectangle first redundant metal and/or the square second redundant metal in said zone.
6. according to the metal filled method of each described redundancy of claim 1 to 4; It is characterized in that said figure according to each said structured metal layer confirms that interconnection line equivalent thickness and deposit thickness difference are the zone that needs are filled redundant metal greater than the zone of set point.
7. an integrated circuit layout structure is characterized in that, comprises at least one structured metal layer and several redundant metals, wherein,
Comprise the zone of the redundant metal of needs filling in the said structured metal layer, said zone comprises interconnection line;
Said several redundant metals are positioned at said zone; Comprise the first redundant metal and the second redundant metal in said several redundant metals; The filling area of each said first redundant metal is greater than the filling area of each said second redundant metal, and the said second redundant metal is between the said first redundant metal and said interconnection line.
8. integrated circuit layout structure according to claim 7; It is characterized in that; The edge distribution in said zone has a plurality of interconnection lines; Comprise the second redundant metal that one said first redundant metal and a plurality of area equate at the middle part in said zone, all comprise the said second redundant metal between the said first redundant metal and each interconnection line.
9. integrated circuit layout structure according to claim 7; It is characterized in that; The edge distribution in said zone has a plurality of interconnection lines; Comprise the said second redundant metal that the said first redundant metal that a plurality of areas equate and a plurality of area equate at the middle part in said zone, all comprise the second redundant metal that said area equates between the said first redundant metal that each area equates and each interconnection line.
10. integrated circuit layout structure according to claim 7; It is characterized in that; The edge distribution in said zone has an interconnection line; Comprise the said second redundant metal that one said first redundant metal and a plurality of area equate at the middle part in said zone, the second redundant metal that said a plurality of areas equate is between the said first redundant metal and a said interconnection line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110460698.1A CN102543853B (en) | 2011-12-31 | 2011-12-31 | Redundancy metal fill method and integrated circuit layout structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110460698.1A CN102543853B (en) | 2011-12-31 | 2011-12-31 | Redundancy metal fill method and integrated circuit layout structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102543853A true CN102543853A (en) | 2012-07-04 |
| CN102543853B CN102543853B (en) | 2016-03-30 |
Family
ID=46350397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110460698.1A Active CN102543853B (en) | 2011-12-31 | 2011-12-31 | Redundancy metal fill method and integrated circuit layout structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102543853B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945302A (en) * | 2012-11-02 | 2013-02-27 | 上海华力微电子有限公司 | Method for dividing high-filling-rate redundant graph |
| CN103441096A (en) * | 2013-08-02 | 2013-12-11 | 上海华力微电子有限公司 | Filling method of redundant graphs |
| US8645879B2 (en) | 2012-02-28 | 2014-02-04 | Shanghai Huali Microelectronics Corporation | Algorithm of Cu interconnect dummy inserting |
| CN103559368A (en) * | 2013-11-18 | 2014-02-05 | 中国科学院微电子研究所 | Chemical mechanical polishing (CMP) analogy method and removal ratio computing method during CMP analogy |
| CN104376186A (en) * | 2014-12-02 | 2015-02-25 | 中国科学院微电子研究所 | Filling method and system for redundant metal |
| CN105740526A (en) * | 2016-01-26 | 2016-07-06 | 中国科学院微电子研究所 | Redundancy metal filling region layout processing method and system |
| WO2022165670A1 (en) * | 2021-02-03 | 2022-08-11 | 香港中文大学（深圳） | Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium |
| CN115000060A (en) * | 2022-07-19 | 2022-09-02 | 合肥晶合集成电路股份有限公司 | Semiconductor device layout structure and forming method thereof |
| CN116432590A (en) * | 2023-06-13 | 2023-07-14 | 合肥晶合集成电路股份有限公司 | Semiconductor device layout structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070288879A1 (en) * | 2006-05-17 | 2007-12-13 | Nec Electronics Corporation | Semiconductor apparatus design method and execution program therefor |
-
2011
- 2011-12-31 CN CN201110460698.1A patent/CN102543853B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070288879A1 (en) * | 2006-05-17 | 2007-12-13 | Nec Electronics Corporation | Semiconductor apparatus design method and execution program therefor |
Non-Patent Citations (1)
| Title |
|---|
| ZHOU JUNXIONG: "Dummy fill effect on CMP planarity", 《JOURNAL OF SEMICONDUCTORS》 * |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8645879B2 (en) | 2012-02-28 | 2014-02-04 | Shanghai Huali Microelectronics Corporation | Algorithm of Cu interconnect dummy inserting |
| CN102945302A (en) * | 2012-11-02 | 2013-02-27 | 上海华力微电子有限公司 | Method for dividing high-filling-rate redundant graph |
| CN103441096A (en) * | 2013-08-02 | 2013-12-11 | 上海华力微电子有限公司 | Filling method of redundant graphs |
| CN103441096B (en) * | 2013-08-02 | 2015-11-25 | 上海华力微电子有限公司 | A kind of redundant pattern fill method |
| CN103559368A (en) * | 2013-11-18 | 2014-02-05 | 中国科学院微电子研究所 | Chemical mechanical polishing (CMP) analogy method and removal ratio computing method during CMP analogy |
| CN103559368B (en) * | 2013-11-18 | 2016-08-17 | 中国科学院微电子研究所 | Chemically mechanical polishing analogy method and clearance computational methods thereof |
| CN104376186B (en) * | 2014-12-02 | 2018-01-30 | 中国科学院微电子研究所 | The fill method and its system of a kind of redundancy metal |
| CN104376186A (en) * | 2014-12-02 | 2015-02-25 | 中国科学院微电子研究所 | Filling method and system for redundant metal |
| CN105740526A (en) * | 2016-01-26 | 2016-07-06 | 中国科学院微电子研究所 | Redundancy metal filling region layout processing method and system |
| CN105740526B (en) * | 2016-01-26 | 2018-11-02 | 中国科学院微电子研究所 | A kind of processing method and system of redundancy metal filling region domain |
| WO2022165670A1 (en) * | 2021-02-03 | 2022-08-11 | 香港中文大学（深圳） | Chip manufacturing method, redundant metal filling method, chip and computer readable storage medium |
| CN115000060A (en) * | 2022-07-19 | 2022-09-02 | 合肥晶合集成电路股份有限公司 | Semiconductor device layout structure and forming method thereof |
| CN116432590A (en) * | 2023-06-13 | 2023-07-14 | 合肥晶合集成电路股份有限公司 | Semiconductor device layout structure |
| CN116432590B (en) * | 2023-06-13 | 2023-08-18 | 合肥晶合集成电路股份有限公司 | Semiconductor device layout structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102543853B (en) | 2016-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102543853A (en) | Dummy metal filling method and integrated circuit layout structure | |
| CN102521468B (en) | Method for extracting parasitic parameters of interconnection lines and device | |
| CN102117348B (en) | Preprocessing method using redundancy metal filling for realizing layout density uniformity | |
| US7235424B2 (en) | Method and apparatus for enhanced CMP planarization using surrounded dummy design | |
| CN102522354B (en) | Method and device for extracting square resistances of interconnection lines | |
| CN102427046B (en) | Electro-chemical deposition result determination method | |
| CN103855044B (en) | A kind of method adding redundant pattern | |
| CN102663147B (en) | Insertion algorithm for copper interconnecting dummy metal figures | |
| CN102495925B (en) | Method and system for achieving redundant metal filled mould board | |
| CN103559368B (en) | Chemically mechanical polishing analogy method and clearance computational methods thereof | |
| CN112131774B (en) | Mixed-order finite element method and device for integrated circuit triangular prism mesh subdivision | |
| US20170293711A1 (en) | Chemical mechanical polishing simulation methods and simulation devices thereof | |
| CN102024083B (en) | Method for extracting capacitance of interconnection structures containing redundant metal | |
| CN112149336B (en) | Method and device for quickly generating three-dimensional integrated circuit electromagnetic simulation high-quality grid | |
| CN105632956A (en) | Method and system for evaluating surface appearance of chip after chemical mechanical polishing | |
| CN111814422A (en) | Interpolation matrix construction method and device of integrated circuit electromagnetic simulation multiple grid method | |
| CN102930159B (en) | A kind of redundancy metal fill method and device | |
| CN102456080A (en) | Dummy fill insertion method for integrated circuit layout | |
| CN115312498A (en) | Semiconductor device and method of forming the same | |
| CN204408747U (en) | A kind of have the pcb board burying resistance | |
| CN101079078B (en) | Method of designing semiconductor device | |
| CN103116663B (en) | Fill method and the redundancy metal fill pattern look-up table method for building up of redundancy metal | |
| US9435643B2 (en) | Presumably defective portion decision apparatus, presumably defective portion decision method, fabrication method for semiconductor device and program | |
| CN109711006A (en) | A kind of redundant pattern adding method | |
| CN102508953B (en) | Method and system for calculating mean time to failure (MTTF) of interconnected line |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |