CN102540240B - Pulse amplitude analyzing circuit and pulse amplitude analyzer - Google Patents
Pulse amplitude analyzing circuit and pulse amplitude analyzer Download PDFInfo
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- CN102540240B CN102540240B CN201210008706.3A CN201210008706A CN102540240B CN 102540240 B CN102540240 B CN 102540240B CN 201210008706 A CN201210008706 A CN 201210008706A CN 102540240 B CN102540240 B CN 102540240B
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Abstract
The invention is applicable to the field of signal detection, and provides a pulse amplitude analyzing circuit and a pulse amplitude analyzer. The pulse amplitude analyzing circuit comprises a charging unit, a signal discriminating unit, a control unit and a resetting unit. By using the pulse amplitude analyzing circuit and the pulse amplitude analyzer, through counting nuclear pulse signals through the signal discriminating unit, recording the peak value information of the nuclear pulse signals, controlling discharge by the control unit and outputting single-channel output signals self-adapting to the widths of the nuclear pulse signals, the carrying of the physical quantities with the widths of the nuclear pulse signals in the single-channel output signals is achieved; the information extraction quantity of the pulse amplitude analyzer is increased; and the application of the pulse amplitude analyzer is extended.
Description
Technical field
The invention belongs to input field, relate in particular to a kind of pulse amplitude analysis circuit and pulse height analyzer.
Background technology
Nuclear physics signal is a series of random pulse signals, each pulse represents a physical event, as while carrying out X-ray detection X, often detects a ray and will produce a core pulse, the temporal information that the width of pulse comprises ray, the amplitude of pulse comprises the energy information of ray.
Current pulse height analyzer is screened core pulse signal, conventionally the instrument that is standardized digital signal by core shift pulse signal, generally, single track output signal is the digital signal of standard, its width is identical, can only be used for core step-by-step counting, cannot carry the physical quantity that pulse width embodies.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of pulse amplitude analysis circuit, is intended to solve existing pulse height analyzer and cannot carries the physical quantity that pulse width embodies, the problem that information extraction amount is low.
The embodiment of the present invention is achieved in that a kind of pulse amplitude analysis circuit, is connected with threshold value generation unit, and described threshold value generation unit has at least one threshold value output terminal, and described circuit comprises:
Charhing unit, the input end of described charhing unit receives core pulse signal, for utilizing described core pulse signal to charge, to record the peak information of described core pulse signal;
Signal screening unit, described signal screening unit has at least one threshold value input end, the reference input of described signal screening unit is connected with the output terminal of described charhing unit, the signal input part of described signal screening unit receives core pulse signal, the connection corresponding to the threshold value output terminal of threshold value generation unit of the threshold value input end of described signal screening unit, for extracting the peak information of described core pulse signal, output amplitude discriminator signal and peak value discriminator signal;
Control module, the first input end of described control module is connected with the first output terminal of described signal screening unit, the second input end of described control module is connected with the second output terminal of described signal screening unit, described control module has multiple output terminals, for according to described amplitude discriminator signal and described peak value discriminator signal, export respectively the first discharge control signal and the second discharge control signal and the single track output signal that is adaptive to described core pulse signal width;
Reset unit, the voltage input end of described reset unit is connected with the output terminal of charhing unit, the first control end of described reset unit is connected with the first output terminal of described control module, the second control end of described reset unit is connected with the second output terminal of described control module, the output terminal of described reset unit is connected with the reset terminal of described control module, be used for according to described the first discharge control signal and described the second discharge control signal controlled discharge, output reset signal, resets described control module.
Another object of the embodiment of the present invention is to provide the pulse height analyzer that adopts above-mentioned pulse amplitude analysis circuit.
In embodiments of the present invention, by signal screening unit, core pulse signal is counted, is recorded the peak information of core pulse signal, and by control module controlled discharge, output adaptive is in the single track output signal of core pulse signal width, realized the physical quantity of carrying core pulse signal width in single track output signal, increase the information extraction amount of pulse height analyzer, expanded the application of pulse height analyzer.
Accompanying drawing explanation
The structural drawing of the pulse amplitude analysis circuit that Fig. 1 provides for one embodiment of the invention;
The exemplary circuit structural drawing of the integration type pulse amplitude analysis circuit that Fig. 2 provides for one embodiment of the invention;
The sequential chart of the integration type pulse amplitude analysis circuit that Fig. 3 provides for one embodiment of the invention;
The exemplary circuit figure of the differential expression pulse amplitude analysis circuit that Fig. 4 provides for one embodiment of the invention;
The graph of a relation of upper-level threshold amplitude, lower threshold amplitude and the noise threshold of the differential expression pulse amplitude analysis circuit that Fig. 5 provides for one embodiment of the invention;
The sequential chart of the differential expression pulse amplitude analysis circuit that Fig. 6 provides for one embodiment of the invention;
The preferred exemplary circuit structure diagram of the differential expression pulse amplitude analysis circuit that Fig. 7 provides for the embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
The embodiment of the present invention changes discharge time by the resistance that regulates slide rheostat, the reset of delay to bistable circuit, make the width adaptive change of output signal maintenance and input nucleus pulse signal, realize the physical quantity of carrying core pulse signal width in single track output signal, increased the information extraction amount of pulse height analyzer.
Fig. 1 illustrates the structure of the pulse amplitude analysis circuit that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
This pulse amplitude analysis circuit 1 is connected with threshold value generation unit 2, can be in various pulse height analyzer, and this threshold value generation unit 2 has at least one threshold value output terminal.
The pulse amplitude analysis circuit 1 providing as one embodiment of the invention comprises:
Charhing unit 11, the input end of this charhing unit 11 receives core pulse signal, for utilizing core pulse signal to charge, output charging voltage;
In embodiments of the present invention, by signal screening unit, core pulse signal is counted, is recorded the peak information of core pulse signal, and by control module controlled discharge, output adaptive is in the single track output signal of core pulse signal width, realized the physical quantity of carrying core pulse signal width in single track output signal, increase the information extraction amount of pulse height analyzer, expanded the application of pulse height analyzer.
Below in conjunction with specific embodiment, realization of the present invention is elaborated.
Fig. 2 illustrates the exemplary circuit structure of the integration type pulse amplitude analysis circuit that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
As one embodiment of the invention, in this integration type pulse amplitude analysis circuit 1, charhing unit 11 comprises:
Diode D1 and capacitor C 1;
The anode of diode D1 is the input end of charhing unit 11, and the negative electrode of diode D1 is connected with one end of capacitor C 1, the other end ground connection of capacitor C 1, and the link of diode D1 and capacitor C 1 is the output terminal of charhing unit 11.
The first discriminator 121, the positive input of this first discriminator 121 is the signal input part of signal screening unit 12, the reverse input end of the first discriminator 121 is that the first threshold input end Inthre1 of signal screening unit 12 is connected with the amplitude threshold output terminal of threshold value generation unit 2, for counting when the amplitude of core pulse signal is greater than threshold signal, output amplitude discriminator signal;
The second discriminator 122, the reverse input end of this second discriminator 122 is the signal input part of signal screening unit 12, the positive input of the second discriminator 13 is the reference input of signal screening unit 12, when being greater than the amplitude of core pulse signal when charging voltage, and output peak value discriminator signal.
The first bistable circuit 131, the input end of this first bistable circuit 131 is the first input end of control module 13, the reset terminal of the first bistable circuit 131 is the reset terminal of control module 13, for when receiving amplitude discriminator signal, output the first status signal and reverse the first status signal;
The second bistable circuit 132, the input end of this second bistable circuit 132 is the second input end of control module 13, the reset terminal of the second bistable circuit 132 is the reset terminal of control module 13, for when receiving peak value discriminator signal, output the second status signal and reverse the second status signal;
First with door an AND1, this first with door AND1 first input end be connected with the inverse output terminal of the first bistable circuit 131, first is connected with the forward output terminal of the second bistable circuit 132 with the second input end of door AND1, first with door AND1 output terminal be the first output terminal of control module 13, for reverse the first status signal and the second status signal are carried out to logic judgement, output the first discharge control signal;
Second with door an AND2, this second with door AND2 first input end be connected with the forward output terminal of the first bistable circuit 131, second is connected with the second input end of door AND1 with first with the second input end of door AND2, second with door AND2 output terminal be the second output terminal of control module 13, for the first status signal and the second status signal are carried out to logic judgement, output the second discharge control signal and the single track output signal that is adaptive to core pulse signal width.
Reset control circuit 141, the input end of this reset control circuit 141 is the voltage input end of reset unit 14, the first control end of reset control circuit 141 is the first control end of reset unit 14, the second control end of reset control circuit 141 is the second control end of reset unit 14, be used for according to the control of the first discharge control signal and the second discharge control signal, charging circuit 11 is discharged, output reseting controling signal;
The 3rd discriminator 142, the positive input of the 3rd discriminator 142 is connected with the input end of reset control circuit 141, the reverse input end of the 3rd discriminator 142 is connected with the discharge threshold output terminal of threshold value generation unit 2, the output terminal of the 3rd discriminator 142 is the output terminal of reset unit 14, for when reseting controling signal is during lower than discharge threshold, export reset signal.
As one embodiment of the invention, reset control circuit 141 comprises:
The first analog switch S1, the second analog switch S2 and slide rheostat R1;
One end of the first analog switch S1 is the input end of reset control circuit 141, the other end ground connection of the first analog switch S1, the control end of the first analog switch S1 is the first control end of reset control circuit 141, one end of the second analog switch S2 is connected with one end of the first analog switch S1, the other end of the second analog switch S2 is by slide rheostat R1 ground connection, the control end of the second analog switch S2 is the second control end of reset control circuit 141, the sliding end ground connection of slide rheostat R1.
As one embodiment of the present invention, the first analog switch S1, the second analog switch S2 all can adopt the switching tubes such as power field effect pipe, triode to realize.
In embodiments of the present invention, in a core pulse signal cycle, core pulse signal carries out amplitude discriminator by the first discriminator 121, when the amplitude of this core pulse signal is greater than the discriminator of the first discriminator 121, the first discriminator 121 output amplitude discriminator signals, when the amplitude of this core pulse signal is less than the discriminator of the first discriminator 121, not output amplitude discriminator signal of the first discriminator 121, this core pulse signal is left in the basket.
Core pulse signal charges by charhing unit 11 simultaneously between the pulse rising stage, due to diode D1 forward conduction, oppositely cut-off, make the output terminal of charhing unit 11 between the pulse decrement phase of core pulse signal, still can keep the voltage of this core pulse signal peak value, the second discriminator 122 by the voltage ratio of this crest voltage and core pulse signal, when crest voltage is greater than the voltage of core pulse signal, between the pulse decrement phase of core pulse signal, export peak value discriminator signal.
When the first bistable circuit 131 receives amplitude discriminator signal, output the first status signal and reverse the first status signal; When the second bistable circuit 132 receives peak value discriminator signal, output the second status signal.First carries out logic judgement with a door AND2 to the first status signal, reverse the first status signal and the second status signal with door AND1 and second, and exports and have a standard single track output signal that is adaptive to input nucleus pulse signal width with door AND2 by second.
When core pulse signal is changed to peak value of pulse, and this peak value of pulse is greater than the discriminator of the first discriminator 121, when the first status signal and the second status signal are high level, the second analog switch conducting in the second discharge control signal control reset control circuit 141 of output, and by slide rheostat R1, charhing unit 11 is discharged, the output end voltage of charhing unit 11 is slowly reduced, and this velocity of discharge depends on the setting to slide rheostat R1 resistance;
When this pulse signal drops to below the discriminator of the first discriminator 121 from peak value, be that reverse the first status signal and the second status signal are while being high level, export the first analog switch conducting in the first discharge control signal control reset control circuit 141, moment discharges to charhing unit 11, in the time of below the discharge threshold voltage of lower voltage to the three discriminators 142 of charhing unit 11 output terminals, the 3rd discriminator 142 is to the reseting controling signal of the first bistable circuit 131 and the second bistable circuit 132 output low levels, make the first bistable circuit 131 and the second bistable circuit 132 reset to start to enter next core pulse signal cycle.
As one embodiment of the invention, the discharge threshold voltage of the 3rd discriminator 142 can be set to the magnitude of voltage a little more than 0 volt.
In embodiments of the present invention, by regulating the resistance of slide rheostat R1, make at core pulse signal amplitude decrement phase close with discharge time, thereby the width of realizing single track output signal is adaptive to the width of core pulse signal.
Fig. 3 illustrates the sequential of the integration type pulse amplitude analysis circuit that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
In embodiments of the present invention, in t0 to the t1 period, do not receive core pulse signal, charhing unit 11 cannot charge, its output end voltage is 0 volt, and because the discharge threshold voltage of the 3rd discriminator 142 is a little more than 0 volt, the output terminal of the 3rd discriminator 142 is low level, the first bistable circuit 131, the second bistable circuit 132 reset, all output low level;
In t1 to the t2 period, core pulse signal charges to charhing unit 11, the positive input voltage of the 3rd discriminator 142 is higher than reverse input end voltage, the 3rd discriminator 142 output switching activities, stop the first bistable circuit 131, the second bistable circuit 132 resets, because the highest amplitude of this core pulse signal does not reach the discriminator of the first discriminator 121, the positive input of the second discriminator 122 is the voltage that the voltage after core pulse signal charges to charhing unit 11 is also not more than the second discriminator 122 reverse input ends, therefore other signals do not change, single track output signal is low level,
In t2 to the t3 period, the highest amplitude of core pulse signal does not reach the discriminator of the first discriminator 121 yet, the output signal of the first discriminator 121 is constant, the reverse input end voltage of the second discriminator 122 declines with core pulse amplitude, and the positive input voltage of the second discriminator 122 remains unchanged because diode D1 oppositely ends, therefore the output of the second discriminator 122 becomes high level, the forward output terminal output high level of the second bistable circuit 132, first exports high level with door AND1, the first analog switch S1 moment discharged to charhing unit 11, the 3rd discriminator 18 outputs become low level to the first bistable circuit 14, the second bistable circuit 15 resets again, single track output signal is low level,
In t3 to the t4 period, the 3rd discriminator 13 resets to the first bistable circuit 14, the second bistable circuit 15, and single track output signal is low level;
In t4 to the t5 period, the highest amplitude of core pulse signal does not reach the discriminator of the first discriminator 121, and single track output signal is low level;
In t5 to the t6 period, the highest amplitude of core pulse signal reaches the discriminator of the first discriminator 121, the first discriminator 121 is exported high level, but the positive input voltage of the second discriminator 122 is not more than reverse input end voltage, therefore the second discriminator 122 output low levels, single track output signal still remains low level;
In t6 to the t7 period, the highest amplitude of core pulse signal reaches the discriminator of the first discriminator 121, the first discriminator 121 is exported high level, the second discriminator 122 is exported high level after reaching core pulse signal peak value, the first bistable circuit 131, the forward output terminal of the second bistable circuit 132 is also exported high level, second exports high level with door AND2, first with a door AND1 output low level, the second analog switch S2 conducting controlled discharge, but because the second analog switch S2 discharges by slide rheostat R1, its velocity of discharge can change by the resistance that regulates slide rheostat R1, the resistance of this slide rheostat R1 is larger, the velocity of discharge is slower, now, the saltus step of single track output signal is to high level,
In t7 to the t8 period, the highest amplitude of core pulse signal is lower than the discriminator of the first discriminator 121, the first discriminator 121 output low levels, but now because causing the 3rd discriminator 142, the velocity of discharge can not to the first bistable circuit 131, reset immediately, therefore the first bistable circuit 131 still keeps output high level, the positive input voltage of the second discriminator 122 is still greater than reverse input end Voltage-output high level, single track output signal is high level, when the output end voltage of charhing unit 11 is brought down below the now amplitude of core pulse signal, but during higher than the discharge threshold voltage of the 3rd discriminator 142, the second discriminator 122 becomes low level, but owing to there is no reset signal, the second bistable circuit 15 is still exported high level signal, until the output end voltage of charhing unit 11 is while being brought down below discharge threshold voltage, the reset signal of the 3rd discriminator 142 output low levels, the first bistable circuit 131 and the second bistable circuit 132 are resetted, output low level, single track output signal becomes low level.
As one embodiment of the invention, slide rheostat R1 can be adjusted to suitable resistance, make at core pulse signal amplitude decrement phase close with discharge time, thereby the width of realizing single track output signal is adaptive to the width of core pulse signal.
In embodiments of the present invention, by the resistance that regulates slide rheostat, change discharge time, and then the reset of delay to bistable circuit, make the width adaptive change of output signal maintenance and input nucleus pulse signal, thereby realized the physical quantity of carrying core pulse signal width in single track output signal, make pulse amplitude analysis in the function of counting, can also extract the physical quantity of core pulse signal width, increased information extraction amount, improved examination efficiency, expanded the application of pulse height analyzer, and this circuit structure is simple, cost is low.
Fig. 4 illustrates the exemplary circuit structure of the differential expression pulse amplitude analysis circuit that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
As one embodiment of the invention, charhing unit 11 comprises:
Diode D3 and capacitor C 4;
The anode of diode D3 is the input end of charhing unit 11, and the negative electrode of diode D3 is connected with one end of capacitor C 4, the other end ground connection of capacitor C 4, and the link of diode D3 and capacitor C 4 is the output terminal of charhing unit 11.
Upper-level threshold discriminator 123, the positive input of this upper-level threshold discriminator 123 is the signal input part of signal screening unit 12, the reverse input end of upper-level threshold discriminator 123 is that the first threshold input end Inthre1 of signal screening unit 12 is connected with the upper-level threshold output terminal of threshold value generation unit 2, for the amplitude of core pulse signal and upper-level threshold amplitude are compared;
Lower threshold discriminator 124, the positive input of this lower threshold discriminator 124 is the signal input part of signal screening unit 12, the reverse input end of lower threshold discriminator 124 is that the Second Threshold input end Inthre2 of signal screening unit 12 and the lower threshold output terminal of threshold value generation unit 2 are connected, for the amplitude of core pulse signal and lower threshold amplitude are compared, when the amplitude of core pulse signal is less than the upper-level threshold amplitude of upper-level threshold discriminator 122, and while being greater than the lower threshold amplitude of lower threshold discriminator 132, count output amplitude discriminator signal;
Cross top discriminator 125, this reverse input end of crossing top discriminator 125 is the signal input part of signal screening unit 12, the positive input of crossing top discriminator 125 is the reference input of signal screening unit 12, when being greater than the amplitude of core pulse signal when charging voltage, and output peak value discriminator signal;
XOR gate XOR, the first input end of this XOR gate XOR is connected with the output terminal of upper-level threshold discriminator 123, and the second input end of XOR gate XOR is connected with the output terminal of lower threshold discriminator 124;
Not gate NOT, the input end of this not gate NOT is connected with the output terminal of XOR gate XOR;
The 3rd with door an AND3, the 3rd is connected with the output terminal of first input end Sheffer stroke gate NOT of door AND3, the 3rd is connected with the output terminal of crossing top discriminator 125 with the second input end of door AND3, the 3rd and the output terminal of an AND3 be the first output terminal of signal screening unit 12;
The 4th with door an AND4, the 4th is connected with the input end of first input end Sheffer stroke gate NOT of door AND4, the 4th is connected with the second input end of door AND3 with the 3rd with the second input end of door AND4, the 4th and the output terminal of AND4 be the second output terminal of signal screening unit 12.
As one embodiment of the present invention, signal screening unit 12 can also comprise:
Noise discriminator 126, the positive input of this noise discriminator 126 is the signal input part of signal screening unit 12, the reverse input end of noise discriminator 126 is that the 3rd threshold value input end Inthre3 of signal screening unit 12 is connected with the noise threshold output terminal of threshold value generation unit 2, the output terminal of noise discriminator 126 is connected with the reset terminal of control module 13, for being greater than after noise threshold amplitude when the amplitude of core pulse signal, output reset signal, resets control module 13.
In embodiments of the present invention, signal screening unit 12 can also comprise: capacitor C 2, capacitor C 3, resistance R 2, resistance R 3 and diode D2, one end of capacitor C 2 is connected with the output terminal of noise discriminator 126, the other end of capacitor C 2 is by resistance R 2 ground connection, the other end while of capacitor C 2 and the anodic bonding of diode D2, the negative electrode of diode is connected with the reset terminal of control module 13, for the output of noise isolation discriminator 126, prevents from disturbing; One end of capacitor C 3 is connected with the output terminal of crossing top discriminator 125, and the other end of capacitor C 3 is by resistance R 3 ground connection, and the other end of capacitor C 3 is connected with the second input end of door AND4 with the 4th simultaneously, for controlling the transmission of upper-level threshold discriminator 123 output signals.
The 3rd bistable circuit 133, the input end of the 3rd bistable circuit 133 is the first input end of control module 13, the reset terminal of the 3rd bistable circuit 133 is the reset terminal of control module 13, the forward output terminal of the 3rd bistable circuit 133 is the first output terminal of control module 13, for exporting the first discharge control signal;
The 4th bistable circuit 134, the input end of the 4th bistable circuit 134 is the second input end of control module 13, the reset terminal of the 4th bistable circuit 134 is the reset terminal of control module 13, the forward output terminal of the 4th bistable circuit 134 is the second output terminal of control module 13, for exporting the first discharge control signal;
The 5th bistable circuit 135, the input end of the 5th bistable circuit 135 is the second input end of control module 13, the reset terminal of the 5th bistable circuit 135 is the reset terminal of control module 13, the forward output terminal of the 5th bistable circuit 135 is the 3rd output terminal of control module 13, for output adaptive in the single track output signal of core pulse signal width.
The input end of reset control circuit 141 is the voltage input end of reset unit 14, the first control end of reset control circuit 141 is the first control end of reset unit 14, the second control end of reset control circuit 141 is the second control end of reset unit 14, the reset level test side of reset control circuit 141 is connected with the reverse input end of the 3rd discriminator 142, the positive input of the 3rd discriminator 142 is the voltage input end of reset unit 14 simultaneously, and the output terminal of the 3rd discriminator 142 is the output terminal of reset unit 14.
As one embodiment of the invention, reset control circuit 141 comprises:
The 3rd analog switch S3, the 4th analog switch S4, resistance R 4, slide rheostat R5, slide rheostat R6;
One end of the 3rd analog switch S3 is that the input end of reset control circuit 141 is connected with one end of slide rheostat R5, the other end ground connection of the 3rd analog switch S3, the control end of the 3rd analog switch S3 is the first control end of reset control circuit 141, the other end of slide rheostat R5 is connected with sliding end, one end of the 4th analog switch S4 is connected with the other end of slide rheostat R5, the other end ground connection of the 4th analog switch S4, the control end of the 4th analog switch S4 is the second control end of reset control circuit 141, one end of resistance R 4 is the input end of reset control circuit 141 simultaneously, the other end of resistance R 4 is connected with one end of slide rheostat R6, the other end ground connection of slide rheostat R6, the sliding end of slide rheostat R6 is the reset level test side of reset control circuit 141.
As one embodiment of the present invention, reset unit 14 can also comprise: capacitor C 5, resistance R 7 and diode D4;
One end of capacitor C 5 is connected with the output terminal of the 3rd discriminator 142, the other end of capacitor C 5 is by resistance R 7 ground connection, the other end while of capacitor C 5 and the anodic bonding of diode D4, the negative electrode of diode D4 is the output terminal of reset unit 14, for isolating the output of the 3rd discriminator 142, prevent noise isolation discriminator 126 and the 3rd discriminator 142 two-way output phase mutual interference.
As one embodiment of the invention, this pulse amplitude analysis circuit 1 can also comprise:
Impact damper 20, the input end of this impact damper 20 receives core pulse signal, and the output terminal of impact damper 20 is connected with the signal input part of signal screening unit 12, for isolating this pulse amplitude analysis circuit 1 and signal source, alleviates the load to signal source.
In embodiments of the present invention, by upper-level threshold discriminator 123 and lower threshold discriminator 124, the amplitude of core pulse signal is compared, by XOR gate, XOR judges amplitude, core pulse signal between upper-level threshold amplitude and lower threshold amplitude is counted, amplitude is not ignored at the core pulse signal of this scope, Fig. 5 shows upper-level threshold amplitude, the relation of lower threshold amplitude and noise threshold: threshold amplitude > noise threshold under upper-level threshold amplitude >, when the amplitude of core pulse signal is counted during in dash area, and by amplitude discriminator signal and designature thereof and cross the peak value discriminator signal that top discriminator 125 exports and carry out exporting to control module 13 after logical operation, this core pulse signal exceedes after noise threshold, noise discriminator 126 is exported reset signal, control module 13 is resetted, control module 13 is started working, the noise threshold of noise discriminator 126 can be made as 10mv, control module 13 directly discharges or by resistance, capacitor C 4 is discharged capacitor C 4 according to the digital signal judgement after logical operation.When the amplitude of input nucleus pulse signal is not in upper, between lower discriminator, AND3 input " 1 ", the 3rd bistable circuit 133 is exported the first discharge control signal control the 3rd analog switch S3 conducting and directly capacitor C 4 is discharged, now the 5th bistable circuit 135 is not exported single track output signal, when core pulse signal is crossed behind top, cross top discriminator 125 and be output as " 1 ", and the amplitude of working as input nucleus pulse signal is in upper, between lower discriminator, AND4 input " 1 ", the 4th bistable circuit 134 is exported the second discharge control signal control the 4th analog switch S4 conducting, by resistance R 4, slide rheostat R5 and slide rheostat R6 discharge to capacitor C 4, regulate the resistance of slide rheostat can change discharge time, and then the reset of delay to bistable circuit, make the width adaptive change of output signal maintenance and input nucleus pulse signal, now the 5th bistable circuit 135 is exported width single track output signal proportional to core pulse signal width, in the time of below the discharge threshold voltage of lower voltage to the three discriminators 142 of charhing unit 11 output terminals (discharge threshold of the 3rd discriminator 142 can be made as 10mv), the 3rd discriminator 142 is to the 3rd bistable circuit 133, the reseting controling signal of the 4th bistable circuit 134 and the 5th bistable circuit 135 output low levels, control and reset to start to enter next core pulse signal cycle.
In embodiments of the present invention, crossing top discriminator 125 resets to the original state of control module 13 by signal leading edge, the 3rd discriminator 142 is resetted and clears data to carry out the judgement of next core pulse signal control module 13 by signal trailing edge, wherein diode D2 and diode D4 are for fear of crossing top discriminator 125 and the 3rd discriminator 142 output docking, avoiding producing reset signal conflict.
Timing reference Fig. 6 of this differential expression pulse amplitude analysis circuit 1, wherein S
a, S
b, S
c, S
dfor the signal at node a, b, c, d place, U
cfor the current potential of charhing unit 11 output terminals, shown the charge status of capacitor C 4, S
resetfor reset signal, S
outfor being adaptive to the single track output signal of core pulse signal width, S
con1be the first control signal, S
con2be the second control signal, as can be seen from Figure 6, when the amplitude of core pulse signal is between upper and lower threshold value, the single track output signal S that output and core pulse signal width adapt
out, when the amplitude of core pulse signal is greater than upper threshold value or is less than lower threshold value, control module 13 is not exported single track output signal.
As one embodiment of the present invention, this pulse amplitude analysis circuit 1 can also comprise a single track double throw switch K, one end of this single track double throw switch K is connected with the first input end of door AND4 with the 4th, the first closing end of single track double throw switch K is connected with the output terminal of XOR gate XOR, the second closing end of single track double throw switch K is connected with the output terminal of lower threshold discriminator 124, when single track double throw switch K is when the first closing end is closed, this pulse amplitude analysis circuit 1 is differential expression structure, when single track double throw switch K is when the second closing end is closed, this pulse amplitude analysis circuit 1 is integration type structure.
Fig. 7 illustrates the preferred exemplary circuit structure of the differential expression pulse amplitude analysis circuit that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
As one embodiment of the invention, control module 13 can also comprise:
The 6th bistable circuit 136, the input end of the 6th bistable circuit 136 is the first input end of control module 13, the reset terminal of the 6th bistable circuit 136 is the reset terminal of control module 13, the forward output terminal of the 6th bistable circuit 136 is the first output terminal of control module 13, for exporting the first discharge control signal;
The 7th bistable circuit 137, the input end of the 7th bistable circuit 137 is the second input end of control module 13, the reset terminal of the 7th bistable circuit 137 is the reset terminal of control module 13, the forward output terminal of the 7th bistable circuit 137 is the second output terminal of control module 13, for exporting the first discharge control signal and the single track output signal that is adaptive to core pulse signal width.
As one embodiment of the invention, reset control circuit 141 can also comprise:
The first K switch 1, second switch K2, slide rheostat R8, resistance R 9, constant current source 1411 and constant pressure source 1412;
One end of the first K switch 1 is that the input end of reset unit 14 is connected with one end of second switch K2, the other end ground connection of the first K switch 1, the control end of the first K switch 1 is the first control end of reset control circuit 141, the other end of second switch K2 is by constant current source 1411 ground connection, the control end of second switch K2 is the second control end of reset control circuit 141, one end ground connection of slide rheostat R8, the other end of slide rheostat R8 is connected with constant pressure source 1412 by resistance R 9, and the sliding end of slide rheostat R8 is the reset level test side of reset control circuit 141.
In embodiments of the present invention, the width of pulse refers to that pulse height is greater than the width of noise threshold part, exceedes noise threshold start to calculate from pulse height.
As one embodiment of the invention, first the amplitude of pulse is carried out to Sampling hold (being the effect of precision rectifer and energy storage) with electric capacity C4, then in pulse to deciding the pulse amplitude values preserving whether useful by judgement " pulse height whether between upper and lower discriminator " again after peaking.If judge " pulse height is between upper and lower discriminator ", allow capacitor C 4 discharge by second switch K2, controlled its discharge time by constant current source 1411; If judgement " pulse height is not between upper and lower discriminator ", allows capacitor C 4 directly by the first K switch 1 rapid discharge, abandon the pulse height information of preserving.Although because the amplitude of signal is not of uniform size, their shape is consistent, the size of amplitude and width have goodish correlativity, so can calculate by amplitude the width of signal.
In embodiments of the present invention, this pulse amplitude analysis circuit 1 carrys out preservation amplitude size by capacitor C 4, allow again capacitor C 4 discharge amplitude information is converted to width information (ratio of conversion is determined by constant current source) by linearity, thereby obtain the variable output signal of pulse width.
The sliding end of resistance R 9 and slide rheostat R8 is screened voltage for the 3rd discriminator 142 provides the termination that can regulate of a capacitor discharge.When capacitor C 4 is discharged into voltage in capacitor C 4 and is less than noise threshold by constant current source 1411, can the first K switch 1 or second switch K2 be opened by the output of the 3rd discriminator 142, stop electric discharge, and make to export the 6th bistable circuit 136, the 7th bistable circuit 137 resets, and prepares work next time.
As one embodiment of the invention, the effect of noise discriminator 126 is when signal amplitude is greater than noise threshold, exports one " 0 "--the signal of > " 1 ", represents " having had signal ".This output forms a very short spike pulse after the differential of capacitor C 2 and resistance R 2, and the 6th bistable circuit 136, the 7th bistable circuit 137 are resetted, and prepares to start working.Capacitor C 5 and resistance R 7 are also the effects that forms reset short pulse.Owing to there being two reset signals to be connected together, may phase mutual interference (as an output high level, the situation of an output low level), so use diode D2 and diode D4 to isolate respectively.
Owing to passing through the existence of precision rectifer C4, signal is crossed before top, and the positive input voltage of crossing top discriminator 125 is less than reverse input end, crosses top discriminator 125 and is output as " 0 "; Signal is crossed behind top, is the crest voltage of signal in capacitor C 4, and the positive input voltage of crossing top discriminator 125 is greater than reverse input end, crosses top discriminator 125 and is output as " 1 ".Its output will be opened with door AND3 with door AND4 after the differential of capacitor C 3 and resistance R 3, allow distance signal pass through.If the amplitude of input nucleus pulse signal is between upper and lower discriminator, AND4 input " 1 ", the 7th bistable circuit 137 is exported " 1 ", make second switch K2 closure, the linear electric discharge of capacitor C 4, AND3 input " 0 " simultaneously, the 6th bistable circuit 136 is exported " 0 ", the first K switch 1 is opened, capacitor C 4 can not discharged by the first K switch 1.If the amplitude of input nucleus pulse signal is not between upper and lower discriminator, AND3 input " 1 ", the 6th bistable circuit 136 is exported " 1 ", makes the first K switch 1 closure, and capacitor C 4 is by the first K switch 1 rapid discharge.When the 7th bistable circuit 137 is exported " 1 ", i.e. output signal.When capacitor C 4 arrives below noise voltage threshold value (being determined by resistance R 9 and slide rheostat R8) by electric discharge by the time, the 3rd discriminator 142 output reversions (" 0 "--> " 1 "), its output resets the 6th bistable circuit 136, the 7th bistable circuit 137 through capacitor C 5 and diode D4, the first K switch 1 and second switch K2 all open, the output of the 7th bistable circuit 137 is also back to " 0 ", the width of the corresponding input pulse of width of output pulse.
In embodiments of the present invention, by the resistance that regulates slide rheostat, change discharge time, and then the reset of delay to bistable circuit, make the width adaptive change of output signal maintenance and input nucleus pulse signal, thereby realized the physical quantity of carrying core pulse signal width in single track output signal, make pulse amplitude analysis in the function of counting, can also extract the physical quantity of core pulse signal width, increased information extraction amount, improved examination efficiency, expanded the application of pulse height analyzer, and this circuit structure is simple, cost is low.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (13)
1. a pulse amplitude analysis circuit, be connected with threshold value generation unit, described threshold value generation unit has at least one threshold value output terminal, and described pulse amplitude analysis circuit comprises charhing unit, signal screening unit, control module and reset unit, it is characterized in that:
The input end of described charhing unit receives core pulse signal, for utilizing described core pulse signal to charge, to record the peak information of described core pulse signal;
Described signal screening unit has at least one threshold value input end, the reference input of described signal screening unit is connected with the output terminal of described charhing unit, the signal input part of described signal screening unit receives core pulse signal, the connection corresponding to the threshold value output terminal of threshold value generation unit of the threshold value input end of described signal screening unit, for extracting the peak information of described core pulse signal, output amplitude discriminator signal and peak value discriminator signal;
The first input end of described control module is connected with the first output terminal of described signal screening unit, the second input end of described control module is connected with the second output terminal of described signal screening unit, described control module has multiple output terminals, for according to described amplitude discriminator signal and described peak value discriminator signal, export respectively the first discharge control signal and the second discharge control signal and the single track output signal that is adaptive to described core pulse signal width;
The voltage input end of described reset unit is connected with the output terminal of charhing unit; the first control end of described reset unit is connected with the first output terminal of described control module; the second control end of described reset unit is connected with the second output terminal of described control module; the output terminal of described reset unit is connected with the reset terminal of described control module; be used for according to described the first discharge control signal and described the second discharge control signal controlled discharge; output reset signal, resets described control module;
Described charhing unit comprises:
Diode and electric capacity;
The anode of described diode is the input end of described charhing unit, and the negative electrode of described diode is connected with one end of described electric capacity, the other end ground connection of described electric capacity, the output terminal that the link of described diode and described electric capacity is described charhing unit.
2. circuit as claimed in claim 1, is characterized in that, described signal screening unit comprises:
The first discriminator, the positive input of described the first discriminator is the signal input part of described signal screening unit, the reverse input end of described the first discriminator is that the first threshold input end of described signal screening unit and the amplitude threshold output terminal of described threshold value generation unit are connected, for counting when the amplitude of described core pulse signal is greater than threshold signal, output amplitude discriminator signal;
The second discriminator, the reverse input end of described the second discriminator is the signal input part of described signal screening unit, the positive input of described the second discriminator is the reference input of described signal screening unit, for when charging voltage is greater than the amplitude of core pulse signal, output peak value discriminator signal.
3. circuit as claimed in claim 1, is characterized in that, described signal screening unit comprises:
Upper-level threshold discriminator, the positive input of described upper-level threshold discriminator is the signal input part of described signal screening unit, the reverse input end of described upper-level threshold discriminator is that the first threshold input end of described signal screening unit and the upper-level threshold output terminal of described threshold value generation unit are connected, for the amplitude of described core pulse signal and upper-level threshold amplitude are compared;
Lower threshold discriminator, the positive input of described lower threshold discriminator is the signal input part of described signal screening unit, the reverse input end of described lower threshold discriminator is that the Second Threshold input end of described signal screening unit and the lower threshold output terminal of described threshold value generation unit are connected, for the amplitude of described core pulse signal and lower threshold amplitude are compared, when the amplitude of described core pulse signal is less than the upper-level threshold amplitude of described upper-level threshold discriminator, and while being greater than the lower threshold amplitude of described lower threshold discriminator, count output amplitude discriminator signal;
Cross top discriminator, the described reverse input end of crossing top discriminator is the signal input part of described signal screening unit, the described positive input of crossing top discriminator is the reference input of described signal screening unit, for when charging voltage is greater than the amplitude of described core pulse signal, output peak value discriminator signal;
XOR gate, the first input end of described XOR gate is connected with the output terminal of described upper-level threshold discriminator, and the second input end of described XOR gate is connected with the output terminal of described lower threshold discriminator;
Not gate, the input end of described not gate is connected with the output terminal of described XOR gate;
The 3rd with door, the described the 3rd is connected with the output terminal of described not gate with the first input end of door, the described the 3rd is connected with the described output terminal of crossing top discriminator with the second input end of door, the described the 3rd and output terminal be the first output terminal of described signal screening unit;
The 4th with door, the described the 4th is connected with the input end of described not gate with the first input end of door, the described the 4th with door the second input end with the described the 3rd with door the second input end be connected, the described the 4th and output terminal be the second output terminal of described signal screening unit.
4. circuit as claimed in claim 3, is characterized in that, described signal screening unit also comprises:
Noise discriminator, the positive input of described noise discriminator is the signal input part of described signal screening unit, the reverse input end of described noise discriminator is that the 3rd threshold value input end of described signal screening unit is connected with the noise threshold output terminal of described threshold value generation unit, the output terminal of described noise discriminator is connected with the reset terminal of described control module, for being greater than after noise threshold amplitude when the noise signal amplitude of described core pulse signal, output reset signal, resets control module.
5. circuit as claimed in claim 2, is characterized in that, described control module comprises:
The first bistable circuit, the input end of described the first bistable circuit is the first input end of described control module, the reset terminal of described the first bistable circuit is the reset terminal of described control module, for when receiving described amplitude discriminator signal, output the first status signal and reverse the first status signal;
The second bistable circuit, the input end of described the second bistable circuit is the second input end of described control module, the reset terminal of described the second bistable circuit is the reset terminal of described control module, for when receiving described peak value discriminator signal, output the second status signal and reverse the second status signal;
First with door, described first is connected with the inverse output terminal of described the first bistable circuit with the first input end of door, described first is connected with the forward output terminal of described the second bistable circuit with the second input end of door, described first with the output terminal of door first output terminal that is described control module, for described reverse the first status signal and described the second status signal are carried out to logic judgement, output the first discharge control signal;
Second with door, described second is connected with the forward output terminal of described the first bistable circuit with the first input end of door, described second is connected with the second input end of door with described first with the second input end of door, described second with the output terminal of door second output terminal that is described control module, for described the first status signal and described the second status signal are carried out to logic judgement, output the second discharge control signal and the single track output signal that is adaptive to core pulse signal width.
6. the circuit as described in claim 3 or 4, is characterized in that, described control module comprises:
The 3rd bistable circuit, the input end of described the 3rd bistable circuit is the first input end of described control module, the reset terminal of described the 3rd bistable circuit is the reset terminal of described control module, the first output terminal that the forward output terminal of described the 3rd bistable circuit is described control module;
The 4th bistable circuit, the input end of described the 4th bistable circuit is the second input end of described control module, the reset terminal of described the 4th bistable circuit is the reset terminal of described control module, the second output terminal that the forward output terminal of described the 4th bistable circuit is described control module;
The 5th bistable circuit, the input end of described the 5th bistable circuit is the second input end of described control module, the reset terminal of described the 5th bistable circuit is the reset terminal of described control module, the 3rd output terminal that the forward output terminal of described the 5th bistable circuit is described control module.
7. the circuit as described in claim 3 or 4, is characterized in that, described control module comprises:
The 6th bistable circuit, the input end of described the 6th bistable circuit is the first input end of described control module, the reset terminal of described the 6th bistable circuit is the reset terminal of described control module, the first output terminal that the forward output terminal of described the 6th bistable circuit is described control module;
The 7th bistable circuit, the input end of described the 7th bistable circuit is the second input end of described control module, the reset terminal of described the 7th bistable circuit is the reset terminal of described control module, the second output terminal that the forward output terminal of described the 7th bistable circuit is described control module.
8. circuit as claimed in claim 1, is characterized in that, described reset unit comprises:
Reset control circuit, the input end of described reset control circuit is the voltage input end of described reset unit, the first control end that the first control end of described reset control circuit is described reset unit, the second control end that the second control end of described reset control circuit is described reset unit, be used for according to the control of described the first discharge control signal and described the second discharge control signal, charhing unit is discharged, output reseting controling signal;
The 3rd discriminator, described the 3rd positive input of discriminator and the input end of described reset control circuit are connected, the reverse input end of described the 3rd discriminator is connected with the discharge threshold output terminal of described threshold value generation unit, the output terminal of described the 3rd discriminator is the output terminal of described reset unit, for when described reseting controling signal is during lower than discharge threshold, export reset signal.
9. circuit as claimed in claim 8, is characterized in that, described reset control circuit comprises:
The first analog switch, the second analog switch and slide rheostat R1;
One end of described the first analog switch is the input end of described reset control circuit, the other end ground connection of described the first analog switch, the control end of described the first analog switch is the first control end of described reset control circuit, one end of described the second analog switch is connected with one end of described the first analog switch, the other end of described the second analog switch is by described slide rheostat R1 ground connection, the control end of described the second analog switch is the second control end of described reset control circuit, the sliding end ground connection of described slide rheostat R1.
10. circuit as claimed in claim 1, is characterized in that, described reset unit comprises:
Reset control circuit and the 3rd discriminator;
The input end of described reset control circuit is the voltage input end of described reset unit, the first control end that the first control end of described reset control circuit is described reset unit, the second control end that the second control end of described reset control circuit is described reset unit, the reset level test side of described reset control circuit is connected with the reverse input end of described the 3rd discriminator, the positive input of described the 3rd discriminator is the voltage input end of described reset unit simultaneously, the output terminal that the output terminal of described the 3rd discriminator is described reset unit.
11. circuit as claimed in claim 10, is characterized in that, described reset control circuit comprises:
The 3rd analog switch, the 4th analog switch, resistance R 4, slide rheostat R5, slide rheostat R6;
One end of described the 3rd analog switch is that the input end of described reset control circuit is connected with one end of described slide rheostat R5, the other end ground connection of described the 3rd analog switch, the control end of described the 3rd analog switch is the first control end of described reset control circuit, the other end of described slide rheostat R5 is connected with the sliding end of described slide rheostat R5, one end of described the 4th analog switch is connected with the other end of described slide rheostat R5, the other end ground connection of described the 4th analog switch, the control end of described the 4th analog switch is the second control end of described reset control circuit, one end of described resistance R 4 is the input end of described reset control circuit simultaneously, the other end of described resistance R 4 is connected with one end of described slide rheostat R6, the other end ground connection of described slide rheostat R6, the sliding end of described slide rheostat R6 is the reset level test side of described reset control circuit.
12. circuit as claimed in claim 10, is characterized in that, described reset control circuit comprises:
The first switch, second switch, slide rheostat R8, resistance R 9, constant current source and constant pressure source;
One end of described the first switch is that the voltage input end of described reset unit and one end of described second switch are connected, the other end ground connection of described the first switch, the control end of described the first switch is the first control end of described reset control circuit, the other end of described second switch is by described constant current source ground connection, the control end of described second switch is the second control end of described reset control circuit, one end ground connection of described slide rheostat R8, the other end of described slide rheostat R8 is connected with described constant pressure source by described resistance R 9, the sliding end of described slide rheostat R8 is the reset level test side of described reset control circuit.
13. 1 kinds of pulse height analyzers, is characterized in that, the pulse amplitude analysis circuit of described analyzer is the circuit described in claim 1 to 12 any one.
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| CN104155678A (en) * | 2014-07-28 | 2014-11-19 | 南华大学 | Single channel pulse height analyzer realized by applying peak position detecting method |
| CN106096714B (en) * | 2016-06-15 | 2018-12-28 | 湖南工业大学 | Stacking counts sensing device |
| CZ307559B6 (en) * | 2017-02-10 | 2018-12-05 | Univerzita Palackého v Olomouci | A method of finding a useful signal in the noise |
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| JP3094437B2 (en) * | 1990-10-30 | 2000-10-03 | 株式会社島津製作所 | X-ray spectrometer |
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| CN102004260A (en) * | 2009-09-02 | 2011-04-06 | 成都理工大学 | Method for discriminating pulse width |
| CN201569744U (en) * | 2009-09-02 | 2010-09-01 | 成都理工大学 | Multi-channel analyzer (MCA) with pulse width discrimination function |
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