CN102508800A - Transmission method and transmission system for two-dimension data block - Google Patents
Transmission method and transmission system for two-dimension data block Download PDFInfo
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Abstract
The invention relates a transmission method and a transmission method for a two-dimensional data block. The method is realized in the following steps: firstly, generating parameters for describing the two-dimensional data block, then obtaining a sequence address for transmitting the two-dimensional data block through calculating based on the parameters, and finally transmitting the two-dimensional data block according to the sequence address. With the adoption of the transmission method and the transmission system, continuous transmission of the two-dimensional data block is realized; and the transmission method and the transmission system can be widely applied to the fields of video encoding and decoding, three-dimensional image processing and the like.
Description
Technical field
The present invention relates to the DMA field, relate in particular to the transmission method and the system of two-dimensional blocks of data.
Background technology
Two-dimensional blocks of data is the set of the discrete data block in address.In two-dimensional blocks of data, the distribution of the address of data is continuous in the individual data piece, and it is discontinuous that the address between adjacent two data blocks distributes.Fig. 1 is existing address consecutive data block and two-dimensional blocks of data relation contrast synoptic diagram; Wherein, left figure is the address consecutive data block, and right figure is a two-dimensional blocks of data.
In existing processor system, the data exchange ways between its inner each parts has following two kinds usually:
(1) mode of register access or interruption.Have few control information and label information between each parts, such data can be carried out exchanges data through the mode of register access or interruption.
(2) CPU (processor) immediate data moves the perhaps mode of DMA (direct memory access).Data block at a large amount of continuation addresses need can directly move data or through DMA (direct memory access) equipment data moved under situation about moving between parts through CPU (processor).
For above-mentioned two kinds of data exchange ways, adopt traditional design just can reach the demand of system.Yet in coding and decoding video and three-dimensional picture processing, two-dimensional blocks of data is used by a large amount of.For example, the triangular apex data during the macro block data in the coding and decoding video, three-dimensional picture are handled, data texturing are usually all with discontinuous 2-D data block mode storage.Therefore, if adopt traditional design to transmit two-dimensional blocks of data, following point will appear:
(1) the two-dimensional blocks of data transmission will cause bus efficiency low
Bus can be transmitted the address continuous data block through the mode of burst provides higher performance.Yet for the discrete data block (being two-dimensional blocks of data) in address, bus transfer can constantly be interrupted by the address of midfeather.Therefore, adopt traditional design transmission two-dimensional blocks of data to make that the efficient of bus is extremely low.
(2) the two-dimensional blocks of data transmission will increase power consumption
Bus only needs the transmission first address during continuous data usually in the transport address.The upset of address bus is less, so power consumption is lower.Yet the characteristic of two-dimensional blocks of data has determined the transmission of two-dimensional blocks of data to transmit first address again at discontinuous point, so address bus upset increased frequency, and power consumption strengthens.
(3) transmission of two-dimensional blocks of data will strengthen bus delay
When two-dimensional blocks of data was transmitted, a block address just need be carried out the transmission of new data block first address again whenever, and bus propagation delay strengthens.
(4) transmission of two-dimensional blocks of data causes transfer efficiency low
As far as most of memory devices (like SDRAM, DDR etc.), the transmission of two-dimensional blocks of data has lower transfer efficiency.Operation can obtain big bandwidth to this type reservoir part to continuous data.Yet this type reservoir part can't be brought into play the advantage of its high bandwidth when the transmission that relates to two-dimensional blocks of data, because the interval of two-dimensional blocks of data can cause being interrupted of reservoir operation (read operation/write operation).Therefore adopt conventional art that two-dimensional blocks of data is transmitted, with respect to the transmission continuous data, transfer efficiency significantly reduces.
To sum up, if adopt traditional design directly to transmit two-dimensional blocks of data, transfer efficiency is low, and the transmission power consumption is high, and bus delay is big, and the two-dimensional blocks of data transmission bandwidth is lower, and this also becomes the design bottleneck of coding and decoding video and stereo image processing system.
Summary of the invention
The present invention proposes a kind of 2-D data block transmission method and system that overcomes the above problems.
In first aspect, the invention provides a kind of transmission method of two-dimensional blocks of data.This method at first generates the parameter of describing said two-dimensional blocks of data.Obtain transmitting the sequence address of this two-dimensional blocks of data then based on said parameter.Transmit said two-dimensional blocks of data based on said sequence address at last.
In second aspect, the invention provides a kind of transmission system of two-dimensional blocks of data.This system comprises processor, direct memory access equipment, source device, destination device.This processor generates the parameter of describing two-dimensional blocks of data.This direct memory access equipment receives said parameter, and obtains the parameter that belongs to the parameter of source device and belong to destination device.This source device receives the said parameter that belongs to source device, goes out the sequence address of the required transmission 2-D data of source device according to this calculation of parameter, and from this address reading of data, again with this data transmission to said dma device.This destination device receives the said parameter that belongs to destination device, goes out the sequence address of the required reception 2-D data of destination device according to this calculation of parameter, and receives data according to this address.
In the third aspect, the invention provides a kind of transmission system of two-dimensional blocks of data.This system comprises processor, source device, destination device.This processor generates the parameter of describing two-dimensional blocks of data, and obtains the parameter that belongs to the parameter of source device and belong to destination device.This source device receives the said parameter that belongs to source device, goes out the sequence address of the required transmission 2-D data of source device according to this calculation of parameter, and from this address reading of data.This destination device receives the said parameter that belongs to destination device, goes out the sequence address of the required reception 2-D data of destination device according to this calculation of parameter, and receives data according to this address.
In fourth aspect, the invention provides a kind of transmission system of two-dimensional blocks of data.This system comprises direct memory access equipment, source device, destination device.This direct memory access equipment generates the parameter of describing two-dimensional blocks of data, and obtains the parameter that belongs to the parameter of source device and belong to destination device.This source device receives the said parameter that belongs to source device, goes out the sequence address of the required transmission 2-D data of source device according to this calculation of parameter, and from this address reading of data, again with this data transmission to said dma device.This destination device receives the said parameter that belongs to destination device, goes out the sequence address of the required reception 2-D data of destination device according to this calculation of parameter, and receives data according to this address.
Aspect the 5th, the invention provides a kind of transmission system of two-dimensional blocks of data.This system comprises processor, direct memory access equipment, source device, destination device.This processor generates the parameter of describing two-dimensional blocks of data.This direct memory access equipment receives said parameter; And the parameter that obtains belonging to the parameter of source device and belong to destination device; Obtain the sequence address of the required transmission two-dimensional blocks of data of source device according to this calculation of parameter that belongs to source device, obtain the sequence address of the required reception 2-D data of destination device according to this calculation of parameter that belongs to destination device.This source device receives the sequence address of the required transmission 2-D data of said source device, and from this address reading of data, again with this data transmission to said dma device.This destination device receives the sequence address of the required transmission 2-D data of said destination device, and receives data according to this address.
Aspect the 6th, the invention provides a kind of transmission system of two-dimensional blocks of data.This system comprises direct memory access equipment, source device, destination device.This direct memory access equipment generates the parameter of describing two-dimensional blocks of data, and obtains the parameter that belongs to the parameter of source device and belong to destination device; And go out the sequence address of the required transmission data of source device according to this calculation of parameter that belongs to source device, go out the sequence address of the required reception data of destination device according to this calculation of parameter that belongs to destination device.This source device receives the sequence address from the required transmission data of the source device of said dma device, and from this address reading of data, again these data are sent to said dma device.This destination device receives the sequence address from the required reception data of the destination device of said dma device, and receives data according to this address.
Description of drawings
Fig. 1 is that existing address connects data block and two-dimensional blocks of data relation contrast synoptic diagram;
Fig. 2 is the two-dimensional blocks of data synoptic diagram of one embodiment of the invention;
Fig. 3 is the 2-D data block transmission system block diagram of the present invention the 1st embodiment;
Fig. 4 is the 2-D data block transmission method process flow diagram of the present invention the 1st embodiment;
Fig. 5 is the 2-D data block transmission system block diagram of the present invention the 2nd embodiment;
Fig. 6 is the 2-D data block transmission method process flow diagram of the present invention the 2nd embodiment;
Fig. 7 is the 2-D data block transmission system block diagram of the present invention the 3rd embodiment;
Fig. 8 is the 2-D data block transmission method process flow diagram of the present invention the 3rd embodiment;
Fig. 9 is the 2-D data block transmission system block diagram of the present invention the 4th embodiment;
Figure 10 is the 2-D data block transmission method process flow diagram of the present invention the 4th embodiment;
Figure 11 is the 2-D data block transmission system block diagram of the present invention the 5th embodiment;
Figure 12 is the 2-D data block transmission method process flow diagram of the present invention the 5th embodiment;
Figure 13 is dma device and source device, the destination device prefectching operation chart of one embodiment of the invention.
Embodiment
Through accompanying drawing and embodiment, technical scheme of the present invention is done further detailed description below.
The present invention adopts parameter mode that two-dimensional blocks of data is described; And obtain the sequence address of two-dimensional blocks of data based on this calculation of parameter; Be the address of each individual data piece in the two-dimensional blocks of data, according to this address transfer two-dimensional blocks of data, thereby realize two-dimensional blocks of data do not interrupt transmission continuously.
Fig. 2 is the two-dimensional blocks of data synoptic diagram of one embodiment of the invention.As shown in the figure, two-dimensional blocks of data comprises 2 data blocks, need to prove, the 2-D data number of blocks is not limited to 2.Among Fig. 2, it is one section continuous storage space that starting point, length are limited block length that the 1st data block is stored in the start address.Distance between the start address of the start address of the 2nd data block and the 1st data block is the piece span; Distance between the end addresses of the start address of the 2nd data block and the 1st data block is the block gap.Individual data piece number in the two-dimensional blocks of data is characterized by total block data.
In the example, through eight parametric description two-dimensional blocks of data in the following table 1.These eight parameters comprise source start address, source block length, source piece span, source total block data, purpose start address, purpose block length, purpose piece span, purpose total block data.
| Source start address SA 1: the address that two-dimensional blocks of data begins in source device. |
| Source block length SL 1: the length of each data block of two-dimensional blocks of data. |
| Source piece span ST 1: the difference of N data block of two-dimensional blocks of data and N+1 data block start address. |
| Source total block data SN 1: the total block data of two-dimensional blocks of data. |
| Purpose start address DA 1: the address that two-dimensional blocks of data begins in destination device. |
| Purpose block length DL 1: the length of each data block of two-dimensional blocks of data. |
| Purpose piece span DT 1: the difference of N data block of two-dimensional blocks of data and N+1 data block start address. |
| Purpose total block data DN 1: the total block data of two-dimensional blocks of data. |
Table 1
According to the parameter in the table 1, can calculate the sequence address (referring to table 2) of two-dimensional blocks of data in source device.
| The piece of two-dimensional blocks of data number | The source start address | The end address, |
| 0 | SA 1 | SA 1+SL 1-1 |
| 1 | SA 1+ST 1 | SA 1+SL 1+ST 1-1 |
| N | SA 1+N*ST 1 | SA 1+SL 1+N*ST 1-1 |
| SN 1-1 | SA 1+(SN 1-1)*ST 1 | SA 1+SL 1+(SN 1-1)*ST 1-1 |
Table 2
According to the parametric description in the table 1, can calculate the sequence address (referring to table 3) of two-dimensional blocks of data in destination device.
| The piece of two-dimensional blocks of data number | Start address | The |
| 0 | DA 1 | DA 1+DL 1-1 |
| 1 | DA 1+DT 1 | DA 1+DL 1+DT 1-1 |
| N | DA 1+N*DT 1 | DA 1+DL 1+N*DT 1-1 |
| DN 1-1 | DA 1+(DN 1-1)*DT 1 | DA 1+DL 1+(DN 1-1)*DT 1-1 |
Table 3
Need to prove, generally, source block length SL
1Equal purpose block length DL
1, source piece sum SN
1Equal purpose piece sum DN
1Therefore, only need pass through six parametric description two-dimensional blocks of data.These six parameters comprise source start address, source block length (also being the purpose block length), source piece span, source total block data (also being purpose piece sum), purpose start address, purpose piece span.
In another example, through eight parametric description two-dimensional blocks of data in the table 4.This table 4 is that with table 1 difference table 4 comprises block gap, source ST
2, and table 1 comprises source piece span ST
1Table 4 comprises purpose block gap DT
2, and table 1 comprises purpose piece span DT
1Other parameters are identical.That is to say that the parameter of describing this two-dimensional blocks of data comprises source start address, source block length, block gap, source, source total block data, purpose start address, purpose block length, purpose block gap, purpose total block data.
Table 4
According to the parametric description in the table 4, can calculate the sequence address (referring to table 5) of two-dimensional blocks of data in source device.
| The piece of two-dimensional blocks of data number | Start address | The |
| 0 | SA 2 | SA 2+SL 2-1 |
| 1 | SA 2+SL 2+ST 2 | SA 2+2*SL 2+ST 2-1 |
| N | SA 2+N*(SL 2+ST 2) | SA 2+(N+1)*SL 2+N*ST 2-1 |
| SN 2-1 | SA 2+(SN 2-1)*(SL 2+ST 2) | SA 2+SN 2*SL 2+(SN 2-1)*ST 2-1 |
Table 5
According to the parametric description in the table 4, can calculate the sequence address (referring to table 6) of two-dimensional blocks of data in destination device.
| The piece of two-dimensional blocks of data number | Start address | The |
| 0 | DA 2 | DA 2+DL 2-1 |
| 1 | DA 2+DL 2+DT 2 | DA 2+2*DL 2+DT 2-1 |
| N | DA 2+N*(DL 2+DT 2) | DA 2+(N+1)*DL 2+N*DT 2-1 |
| DN 2-1 | DA 2+(DN 2-1)*(DL 2+DT 2) | DA 2+DN 2*DL 2+(DN 2-1)*DT 2-1 |
Table 6
Need to prove, generally, source block length SL
2Equal purpose block length DL
2, source total block data SN
2Equal purpose total block data DN
2In such cases, only need two-dimensional blocks of data be described, i.e. source start address, source block length (being the purpose block length), block gap, source, source total block data (being purpose piece sum), purpose start address, purpose block gap through six parameters.
Fig. 3 is the 2-D data block transmission system synoptic diagram of the present invention the 1st embodiment.This transmission system comprises CPU (processor), DMA (direct memory access) equipment, source device, destination device.This 2-D data block transmission system can be integrated on the chip, also can realize through circuit board (like the PCB version) mode.
Among Fig. 3, CPU produces the parameter (concrete parameter is referring to table 1, table 4) of describing two-dimensional blocks of data, and gives dma device with this parameter configuration.CPU will no longer intervene in data transmission procedure after this.In the example, CPU writes parameter in the register of DAM equipment.In another example, CPU writes parameter in the external memory storage of dma device.
In the example, the parameter that CPU produced deposits in to storer according to the discernible form of dma device, for example put in the storer with allocation list (referring to below table 7) mode, and the location storage of this allocation list in this storer is in a register A.CPU disposes the value among the A to dma device with the mode of writing the DMA register then, and starts dma device through the mode of writing the DMA register; So that after dma device started, dma device can read this allocation list (referring to table 7) from the relevant position of this storer; And then make dma device can parameter relevant with source device in this allocation list (source start address, source block length, source piece span, source total block data) be sent to source device, and parameter relevant with destination device in this allocation list (purpose start address, purpose block length, purpose piece span, purpose total block data) is sent to destination device.
| Source piece start address |
| The source block length |
| Source piece span |
| The source total block data |
| The purpose start address |
| The purpose block length |
| Purpose piece span |
| The purpose total block data |
Table 7
Among Fig. 3, dma device is used for the parameter that obtains is handled, and with the parameter that obtains belonging to the parameter of source device and belonging to destination device, and relevant parameter is disposed respectively to source device and destination device, and the concrete configuration mode can be referring to preceding text.
Source device goes out the sequence address calculating of sequence address (concrete referring to table 2, table 5) of the required transmission data of source device according to its calculation of parameter that obtains, and from this address reading of data, again these data are sent to dma device.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
Dma device sends destination device with two-dimensional blocks of data after receiving the two-dimensional blocks of data from source device.
Destination device goes out the sequence address (concrete sequence address referring to table 3, table 6) of the required reception data of destination device according to its calculation of parameter that obtains, and receives according to this sequence address and to preserve from the data of dma device and with the data that this receives.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
During work, dma device starts the transmission of the two-dimensional blocks of data of source device to destination device after the order of for example receiving CPU, and notification source equipment sends two-dimensional blocks of data, notice destination device reception two-dimensional blocks of data.After source device receives corresponding notice, send two-dimensional blocks of data to dma device according to its sequence address that obtains.After destination device receives corresponding notice, receive two-dimensional blocks of data according to its sequence address that obtains.After the two-dimensional blocks of data total block data of transmission reached source total block data SN or purpose total block data DN, dma device stopped the transmission of two-dimensional blocks of data, and dma device can adopt and register tagging is set or sends interrupt mode and inform that this data transfer of CPU finishes.CPU also can be known this DTD through inquiry or response interrupt mode.
Fig. 4 is the 2-D data block transmission method process flow diagram of the present invention the 1st embodiment.
In step 410, CPU produces the parameter of describing two-dimensional blocks of data, and gives dma device with this parameter configuration.
In step 420, dma device is handled the parameter that it obtains, and the parameter configuration that will belong to source device is given source device, and the parameter configuration that will belong to destination device is given destination device, and starts the transmission of the two-dimensional blocks of data of source device to destination device.
In the example, dma device is based on the order of CPU and start the transmission of the two-dimensional blocks of data of source device to destination device.
In the example, the parameter relevant with source device is written in the register of source device through the register interface of source device, and the parameter relevant with destination device is written in the register of destination device through the register interface of destination device.In another example, the parameter relevant with source device is written in the external memory storage of source device, and the parameter relevant with destination device is written in the external memory storage of destination device.
In step 430; Source device receives the data transfer command from dma device; The calculation of parameter that obtains according to this source device goes out the sequence address (concrete sequence address is referring to table 2, table 5) that the source device needs transmit two-dimensional blocks of data, and read data is given dma device from this address.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
In step 431, dma device is filled or is removed two-dimensional blocks of data based on demand or operation such as counting, and the two-dimensional blocks of data after will handling again sends.This step is an optional step.Dma device also can not taked operations such as aforesaid filling or removing, but only two-dimensional blocks of data is sent.
In step 440; Destination device receives the data transfer command from dma device; Go out the sequence address (concrete sequence address is referring to table 3, table 6) that the destination device needs receive two-dimensional blocks of data according to its calculation of parameter that obtains, and preserve from the data of dma device and with it according to this sequence address reception.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
In step 450, after the individual data piece total block data of the two-dimensional blocks of data of having transmitted reached source total block data SN or purpose total block data DN, dma device sent the notice that stops the two-dimensional blocks of data transmission to source device, destination device.
In an example; Dma device knows whether the individual data number of blocks reaches source total block data SN or purpose total block data DN in the two-dimensional blocks of data of transmission; Whether reach source total block data SN or purpose total block data DN like individual data number of blocks in the two-dimensional blocks of data of knowing transmission through counting mode, thereby whether the output of learning this two-dimensional blocks of data is accomplished.
In step 460, the dma device employing is provided with register tagging or sends interrupt mode and inform that the transmission of this two-dimensional blocks of data of CPU finishes, and CPU is known this two-dimensional blocks of data end of transmission (EOT) through inquiry or response interrupt mode.
Fig. 5 is the 2-D data block transmission system block diagram of the present invention the 2nd embodiment.This transmission system comprises CPU (processor), DMA (direct memory access) equipment, source device and destination device.This 2-D data block transmission system can be integrated on the chip, also can realize through circuit board (like the PCB version) mode.
The difference of this Fig. 5 system and Fig. 3 system is, in Fig. 5 system, by CPU to source device and destination device configuration parameter; And in Fig. 3 system, then by dma device to source device and destination device configuration parameter, detail below.
Among Fig. 5; CPU produces the parameter (concrete parameter is referring to table 1, table 4) of describing two-dimensional blocks of data; And the parameter configuration that will belong to source device is given source device; The parameter configuration that will belong to destination device is given destination device, and gives dma device with the one or more configurations in the generation parameter, and the concrete configuration mode is referring to the configuration mode described in aforementioned the 1st embodiment.For example, CPU disposes source total block data and purpose total block data to dma device; And for example, CPU gives dma device with all parameter configuration that it produced.
In the example, CPU writes relevant parameter respectively in source device, destination device, the dma device register separately.In another example, CPU writes relevant parameter respectively in source device, destination device, the dma device external memory storage separately.
Dma device starts the transmission of the two-dimensional blocks of data of source device to destination device, and reaches source total block data SN at the two-dimensional blocks of data total block data that is transmitted
1Or purpose total block data DN
1The time stop the transmission of 2-D data.In the example, dma device is based on the order of CPU and start the data transmission of source device to destination device.
Source device goes out the sequence address calculating of sequence address (concrete referring to table 2, table 5) of the required transmission data of source device according to its calculation of parameter that obtains, and from this address reading of data, again these data are sent to dma device.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
Dma device after receiving the two-dimensional blocks of data from source device sends two-dimensional blocks of data.
Destination device goes out the sequence address (concrete sequence address referring to table 3, table 6) of the required reception data block of destination device according to its calculation of parameter that obtains, and receives according to this sequence address and to preserve from the data of dma device and with the data that this receives.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
During work, dma device can start the transmission of the two-dimensional blocks of data of source device to destination device based on the order of CPU, and notification source equipment sends two-dimensional blocks of data, notice destination device reception two-dimensional blocks of data; After source device receives corresponding notice, send two-dimensional blocks of data to dma device according to its sequence address that obtains; After destination device receives corresponding notice, receive two-dimensional blocks of data according to its sequence address that obtains; After the data block transmitted total block data reached source total block data SN or purpose total block data DN, dma device stopped the transmission of two-dimensional blocks of data.Dma device can adopt and register tagging is set or sends interrupt mode and inform that this data transfer of CPU finishes.CPU also can be known this DTD through inquiry or response interrupt mode.
Fig. 6 is the 2-D data block transmission method process flow diagram of the present invention the 2nd embodiment.
In step 610, CPU produce to describe the parameter of two-dimensional blocks of data, and the parameter configuration that will belong to source device gives source device, and the parameter configuration that will belong to destination device is given destination device, and with the one or more configurations in the generation parameter to dma device.For example, CPU is with source total block data SN
1And purpose total block data DN
1Dma device is given in configuration; And for example, CPU gives dma device with all parameter configuration that it produced.
In the example, CPU writes relevant parameter respectively in source device, destination device, the dma device register separately.In another example, CPU writes relevant parameter respectively in source device, destination device, the dma device external memory storage separately.
In step 620, dma device starts the transmission of the two-dimensional blocks of data of source device to destination device.In the example, dma device is based on the order of CPU and start the data transmission of source device to destination device.
In step 630, source device receives the data transfer command from dma device, go out the sequence address (concrete sequence address is referring to table 2, table 5) that the source device needs transmit two-dimensional blocks of data according to its calculation of parameter that obtains, and read data is given dma device from this address.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
In step 631, dma device is filled two-dimensional blocks of data according to demand or operation such as removing, and the two-dimensional blocks of data after will handling again sends.This step is an optional step.Dma device also can not taked operations such as aforesaid filling or removing, but only two-dimensional blocks of data is sent.
In step 640; Destination device receives the data transfer command from dma device; Go out the sequence address (concrete sequence address is referring to table 3, table 6) that the destination device needs receive two-dimensional blocks of data according to its calculation of parameter that obtains, and preserve from the data of dma device and with it according to this sequence address reception.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
In step 650, after the data block transmitted total block data reached source total block data SN or purpose total block data DN, dma device sent the notice that stops the two-dimensional blocks of data transmission to source device, destination device.At this moment, source device stops to transmit two-dimensional blocks of data, and destination device stops the reception to two-dimensional blocks of data.
In step 660, the dma device employing is provided with register tagging or sends interrupt mode and inform that the transmission of this two-dimensional blocks of data of CPU finishes, and CPU is known this two-dimensional blocks of data end of transmission (EOT) through inquiry or response interrupt mode.
Fig. 7 is the 2-D data block transmission system synoptic diagram of the present invention the 3rd embodiment, and this transmission system comprises that notice generates parameter equipment, DMA (direct memory access) equipment, source device, destination device.This 2-D data block transmission system can be integrated on the chip, also can realize through circuit board (like the PCB version) mode.
This Fig. 7 system and the difference of Fig. 3 system are, in Fig. 7 system, produce the parameter of describing two-dimensional blocks of data by dma device, in Fig. 3 system, produce the parameter of describing two-dimensional blocks of data by CPU, detail below.
Among Fig. 7, this notice generates the notice that parameter equipment is used for sending to dma device the transmission two-dimensional blocks of data.In the example, it is processor CPU that this notice generates parameter equipment.
This dma device produces the parameter (concrete parameter is referring to table 1, table 4) of describing two-dimensional blocks of data; And this parameter handled the parameter that belongs to the parameter of source device and belong to destination device to obtain; And give source device with this parameter configuration that belongs to source device; Give destination device with this parameter configuration that belongs to destination device, the concrete configuration mode is referring to the configuration mode described in aforementioned the 1st embodiment.
In the example, dma device writes relevant parameter respectively in source device, the destination device register separately.In another example, dma device writes relevant parameter respectively in source device, the destination device external memory storage separately.
This source device goes out the sequence address calculating of sequence address (concrete referring to table 2, table 5) of the required transmission data of source device according to its calculation of parameter that obtains, and from this address reading of data, again these data are sent to dma device.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
Dma device after receiving the two-dimensional blocks of data from source device sends two-dimensional blocks of data.
This destination device goes out the sequence address (concrete sequence address referring to table 3, table 6) of the required reception data of destination device according to its calculation of parameter that obtains, and receives according to this sequence address and to preserve from the data of dma device and with the data that this receives.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
During work, dma device starts the transmission of the two-dimensional blocks of data of source device to destination device, and notification source equipment sends two-dimensional blocks of data, notice destination device reception two-dimensional blocks of data; After source device receives corresponding notice, send two-dimensional blocks of data to dma device according to its sequence address that obtains; After destination device receives corresponding notice, receive two-dimensional blocks of data according to its sequence address that obtains; After the data block transmitted total block data reached source total block data SN or purpose total block data DN, dma device stopped the transmission of two-dimensional blocks of data, and the dma device employing is provided with register tagging or the transmission interrupt mode informs that this data transfer of CPU finishes; CPU is known this DTD through inquiry or response interrupt mode.
Fig. 8 is the 2-D data block transmission method process flow diagram of the present invention the 3rd embodiment.
In step 810, this notice generates parameter equipment sends notice from the transmission two-dimensional blocks of data to dma device.In the example, it is processor CPU that this notice generates parameter equipment.
In step 820; Dma device produces the parameter of describing two-dimensional blocks of data, and this parameter is handled, and the parameter configuration that will belong to source device is given source device; The parameter configuration that will belong to destination device is given destination device, and starts the transmission of the two-dimensional blocks of data of source device to destination device.
In the example, the parameter that dma device will belong to source device is written in the register of source device, and the parameter that will belong to destination device is written in the register of destination device.In another example, the parameter that dma device will belong to source device is written in the external memory storage of source device, and the parameter that will belong to destination device is written in the external memory storage of destination device.
In step 830; Source device receives the data transfer command from dma device; The calculation of parameter that obtains according to source device goes out the sequence address that the source device needs transmit two-dimensional blocks of data, and concrete sequence address is referring to table 2, table 5, and read data is given dma device from this address.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
In step 831, dma device is filled two-dimensional blocks of data according to demand or operation such as removing, and the two-dimensional blocks of data after will handling again sends.This step is an optional step.Dma device also can not taked operations such as aforesaid filling or removing, but only two-dimensional blocks of data is sent.
In step 840; Destination device receives the data transfer command from dma device; The calculation of parameter that obtains according to destination device goes out the sequence address that the destination device needs receive two-dimensional blocks of data; Concrete sequence address is referring to table 3, table 6, and receives according to this sequence address and to preserve from the data of dma device and with it.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
In step 850, after the data block transmitted total block data reached source total block data SN or purpose total block data DN, dma device sent the notice that stops the two-dimensional blocks of data transmission to source device, destination device.
In step 860, the dma device employing is provided with register tagging or sends interrupt mode and inform that the transmission of this two-dimensional blocks of data of CPU finishes, and CPU is known this two-dimensional blocks of data end of transmission (EOT) through inquiry or response interrupt mode.
Fig. 9 is the 2-D data block transmission system synoptic diagram of the present invention the 4th embodiment, and this transmission system comprises CPU (processor), DMA (direct memory access) equipment, source device, destination device.This 2-D data block transmission system can be integrated on the chip, also can realize through circuit board (like the PCB version) mode.
The difference of this Fig. 9 system and Fig. 3 system is, in Fig. 9 system, by the sequence address of dma device calculation sources equipment and destination device, and the address is sent to source device and destination device respectively; And in Fig. 3 system, then calculating it by source device need transmit the sequence address of data, calculates it by destination device and need receive the sequence address of data, details below.
Among Fig. 9, CPU produce to describe the parameter of two-dimensional blocks of data, and concrete parameter is referring to table 1, table 4, and gives dma device with this parameter configuration, and CPU will no longer intervene in data transmission procedure.
In the example, the parameter that CPU produced deposits in to storer according to the discernible form of dma device, for example put in the storer with allocation list (referring to last table 7) mode, and the location storage of this allocation list in this storer is in a register A.CPU disposes the value among the A to dma device with the mode of writing the DMA register then, and starts dma device through writing the DMA register mode; So that start the back at dma device it can read this allocation list from the relevant position of this storer.And then make dma device after the data transmission that starts between source device, the destination device; Two-dimensional blocks of data can be transmitted with forms data block mode block-by-block successively; And when first transmission of data blocks; Dma device can be sent to source device with source piece relevant parameter (parameters such as current source device data block address, current source device data block length), and purpose piece relevant parameter (parameters such as current destination device data block address, current destination device data block length) is sent to destination device.If source device has the concurrent operations ability, dma device then is sent to source device with parameters such as next data block address of source device, next data block lengths simultaneously, is the operation of preparing of next source piece in advance with notification source equipment; Data in next data block etc. are prepared in for example calculated address.If destination device has the concurrent operations ability, dma device then is sent to destination device with parameters such as next data block address of destination device, next data block lengths simultaneously, is the operation of preparing of next purpose piece in advance with the notice destination device; For example calculated address, buffer zone is prepared in the ordering arbitration in advance, activates storer etc.
Among Fig. 9; Dma device is used to obtain the parameter that belongs to the parameter of source device and belong to destination device; And belong to the sequence address that the source device calculation of parameter goes out the required transmission data of source device (calculating of concrete sequence address is referring to table 2, table 5), and this sequence address is sent to source device according to this; And belong to the sequence address that the destination device calculation of parameter goes out the required reception data of destination device (concrete sequence address is referring to table 3, table 6), and this sequence address is sent to destination device according to this.
In the example, dma device writes relevant parameter respectively in source device, the destination device register separately.In another example, dma device writes relevant parameter respectively in source device, the destination device external memory storage separately.
Source device receives the sequence address from these source device transmission data of dma device, and from this address reading of data, again these data are sent to dma device.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
Dma device after receiving the two-dimensional blocks of data from source device sends two-dimensional blocks of data.
Destination device receives the sequence address from this destination device of dma device, and preserves from the data of dma device and with the data that this receives according to this sequence address reception.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
In the work; Dma device starts the transmission (starting the transmission of the two-dimensional blocks of data of source device to destination device like dma device based on the order of CPU) of the two-dimensional blocks of data of source device to destination device; And notification source equipment sends two-dimensional blocks of data, notice destination device reception two-dimensional blocks of data; After source device receives corresponding notice, send two-dimensional blocks of data to this dma device based on the corresponding sequence address; After destination device receives corresponding notice, receive two-dimensional blocks of data based on the corresponding sequence address; After the two-dimensional blocks of data total block data of transmission reached source total block data SN or purpose total block data DN, dma device stopped the transmission of two-dimensional blocks of data, and the dma device employing is provided with register tagging or the transmission interrupt mode informs that this data transfer of CPU finishes; CPU is known this DTD through inquiry or response interrupt mode.
Figure 10 is the 2-D data block transmission method process flow diagram of the present invention the 4th embodiment.
In step 1010, CPU produces the parameter of describing two-dimensional blocks of data, and gives dma device with this parameter configuration.
In step 1020; Dma device is handled this parameter; With the parameter that obtains belonging to the parameter of source device and belonging to destination device; And go out the sequence address calculating of sequence address (concrete referring to table 2, table 5) of the required transmission data of source device according to this source device calculation of parameter, again this sequence address is sent to source device; And go out the sequence address (concrete sequence address referring to table 3, table 6) of the required reception data of destination device according to this destination device calculation of parameter, again this sequence address is sent to destination device; Start the transmission of the two-dimensional blocks of data of source device to destination device then.
In the example, dma device is based on the order of CPU and start the transmission of the two-dimensional blocks of data of source device to destination device.
In the example, source device is written to the sequence address of its transmission data in the register of source device, and destination device is written to the sequence address of its transmission data in the register of destination device.In another example, source device is written to the sequence address of its transmission data in the external memory storage of source device, and destination device is written to the sequence address of its transmission data in the external memory storage of destination device.
In step 1030, source device receives the sequence address from the source device transmission data of dma device, and read data is given dma device from this address.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
In step 1031, dma device is filled two-dimensional blocks of data according to demand or operation such as removing, and the two-dimensional blocks of data after will handling again sends.This step is an optional step.Dma device also can not taked operations such as aforesaid filling or removing, but only two-dimensional blocks of data is sent.
In step 1040, destination device receives the sequence address from the required reception data of this destination device of dma device, and preserves according to these sequence address reception data and with it.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
In step 1050, after the two-dimensional blocks of data total block data of transmission reached source total block data SN or purpose total block data DN, dma device sent the notice that stops the two-dimensional blocks of data transmission to source device, destination device.
In step 1060, the dma device employing is provided with register tagging or sends interrupt mode and inform that the transmission of this two-dimensional blocks of data of CPU finishes, and CPU is known this two-dimensional blocks of data end of transmission (EOT) through inquiry or response interrupt mode.
Figure 11 is the 2-D data block transmission system synoptic diagram of the present invention the 5th embodiment, and this transmission system comprises that notice generates parameter equipment, DMA (direct memory access) equipment, source device, destination device.This 2-D data block transmission system can be integrated on the chip, also can realize through circuit board (like the PCB version) mode.
The difference of this Figure 11 system and Fig. 7 system is, in Figure 11 system, by the sequence address of dma device calculation sources equipment and destination device, and the address is sent to source device and destination device respectively; And in Fig. 7 system, then calculating it by source device need transmit the sequence address of data, and it need receive the sequence address of data by destination device calculating, details below.
Among Figure 11, this notice generates the notice that parameter equipment is used for sending to dma device the transmission two-dimensional blocks of data.In the example, it is processor CPU that this notice generates parameter equipment.
This dma device produces the parameter (concrete parameter is referring to table 1, table 4) of describing two-dimensional blocks of data,, again this parameter is handled the parameter that belongs to the parameter of source device and belong to destination device to obtain; And go out the sequence address of the required transmission data of source device, and this sequence address is sent to source device according to this calculation of parameter that belongs to source device; Go out the sequence address of the required reception data of destination device according to this calculation of parameter that belongs to destination device, and this sequence address is sent to destination device.
In the example, dma device writes the corresponding sequence address respectively in source device, the destination device register separately.In another example, dma device writes the corresponding sequence address respectively in source device, the destination device external memory storage separately.
This source device receives the sequence address from these source device transmission data of dma device, and from this address reading of data, again these data are sent to dma device.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
This destination device receives the sequence address from these destination device transmission data of dma device, and also these data that receive is preserved from the data of dma device according to this sequence address reception.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
During work; Dma device starts the transmission (starting the transmission of the two-dimensional blocks of data of source device to destination device like dma device based on the order of CPU) of the two-dimensional blocks of data of source device to destination device; And notification source equipment sends two-dimensional blocks of data, notice destination device reception two-dimensional blocks of data; After source device receives corresponding notice, send two-dimensional blocks of data to dma device based on the corresponding sequence address; After destination device receives corresponding notice, receive two-dimensional blocks of data based on the corresponding sequence address; After the two-dimensional blocks of data total block data of transmission reached source total block data SN or purpose total block data DN, dma device stopped the transmission of two-dimensional blocks of data, and the dma device employing is provided with register tagging or the transmission interrupt mode informs that this data transfer of CPU finishes; CPU is known this DTD through inquiry or response interrupt mode.
Figure 12 is the 2-D data block transmission method process flow diagram of the present invention the 5th embodiment.
In step 1210, this notice generates parameter equipment sends notice from the transmission two-dimensional blocks of data to dma device.In the example, it is processor CPU that this notice generates parameter equipment.
In step 1220, dma device produces the parameter (concrete parameter is participated in table 1, table 4) of describing two-dimensional blocks of data, and this parameter is handled the parameter that belongs to the parameter of source device and belong to destination device to obtain; And go out the sequence address of the required transmission data of source device, and this sequence address is sent to source device according to this calculation of parameter that belongs to source device; Go out the sequence address of the required reception data of destination device according to this calculation of parameter that belongs to destination device, and this sequence address is sent to destination device; Start the transmission of the two-dimensional blocks of data of source device to destination device then.
In the example, dma device is written to the sequence address of source device in the register of source device, and the sequence address of destination device is written in the register of destination device.In another example, dma device is written to the sequence address of source device in the external memory storage of source device, and the sequence address of destination device is written in the external memory storage of destination device.
In step 1230, source device receives the sequence address (concrete sequence address is referring to table 2, table 5) that need transmit two-dimensional blocks of data from this source device of dma device, and read data is given dma device from this address.Therefore, source device can interruptedly not transfer to dma device with two-dimensional blocks of data continuously according to this sequence address.
In step 1231, dma device is filled two-dimensional blocks of data according to demand or operation such as removing, and the two-dimensional blocks of data after will handling again sends.This step is an optional step.Dma device also can not taked operations such as aforesaid filling or removing, but only two-dimensional blocks of data is sent.
In step 1240, destination device receives the sequence address (concrete sequence address is referring to table 3, table 6) from these destination device transmission data of dma device, and preserves from the data of dma device and with it according to this sequence address reception.Therefore, destination device can interruptedly not receive the two-dimensional blocks of data from dma device continuously based on this sequence address, and then realizes that two-dimensional blocks of data do not interrupt transmission continuously from source device to destination device.
In step 1250, after the two-dimensional blocks of data total block data of transmission reached source total block data SN or purpose total block data DN, dma device sent the notice that stops the two-dimensional blocks of data transmission to source device, destination device.
In step 1260, the dma device employing is provided with register tagging or sends interrupt mode and inform that the transmission of this two-dimensional blocks of data of CPU finishes, and CPU is known this two-dimensional blocks of data end of transmission (EOT) through inquiry or response interrupt mode.
Can pass through the prefectching mode of operation between dma device and source device, the destination device, further guarantee the continuous interrupted transmission of two-dimensional blocks of data.
Figure 13 is dma device and source device, the destination device prefectching operation chart of one embodiment of the invention.Dma device is connected with bus between source device, the destination device and comprises transmission channel and the passage of looking ahead.Specifically, dma device is connected with the bus of source device and comprises transmission channel 1, the passage 1 of looking ahead, and dma device be connected with the bus of destination device comprise transmission channel 2, the passage 2 of looking ahead.
Transmission channel is responsible for sending the address and the data of this transmission.The passage of looking ahead is responsible for sending transport address next time, and source device is carried out the transmission data or destination device is carried out the preparation that receives data so that prenotice.The parameter that the passage of looking ahead sends to source device, destination device can also comprise the parameters such as length of transmission data block next time.And transmission channel walks abreast with the passage of looking ahead, and the N-1 time transmission operated and the N time prefetch operation can overlap on sequential, sees table 8.
Table 8
In the table 7; No matter be transmission operation, prefetch operation or the dma device of dma device and source device and transmission operation, the prefetch operation of destination device; The address of next data of in the transmission current data, looking ahead; Promptly the prefetching process of the transmission course of N-1 piece and N piece is overlapped, and transmission operation is carried out with prefetch operation side by side, thus guaranteed two-dimensional blocks of data do not interrupt transmission continuously.
Need to prove; Though dma device directly sends two-dimensional blocks of data after receiving the two-dimensional blocks of data from source device in the description of preamble; But; Dma device can fill or remove two-dimensional blocks of data or operation such as counting according to demand, and the two-dimensional blocks of data after will handling again sends.Such as, as source block length SL
1＞purpose block length DL
1The time, dma device will be deleted to purpose block length DL from the 2-D data block length of source device
1Size.As source block length SL
1＜purpose block length DL
1The time, dma device will be filled to purpose block length DL from the two-dimensional blocks of data of source device
1Size.
In addition, dma device can adopt the fixed address mode between source device and destination device, to carry out data transmission, and need not transfer address on bus.The mode of this employing fixed address has reduced the upset of address bus, and then reduces bus low power.
The all or part of step that one of ordinary skill in the art will appreciate that realization said method embodiment can be accomplished through the relevant hardware of programmed instruction; Aforesaid program can be stored in the computer read/write memory medium; This program the step that comprises said method embodiment when carrying out.Wherein, aforementioned storage medium comprises various media that can be program code stored such as ROM, RAM, magnetic disc or CD etc.
It should be noted last that; Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Although the present invention is specified with reference to preferred embodiment; Those of ordinary skill in the art should be appreciated that and can make amendment or be equal to replacement technical scheme of the present invention, and do not break away from the spirit and the scope of technical scheme of the present invention.
Claims (23)
1. the transmission method of a two-dimensional blocks of data is characterized in that, comprising:
Generate the parameter of describing said two-dimensional blocks of data;
Obtain transmitting the sequence address of this two-dimensional blocks of data based on said parameter;
Transmit said two-dimensional blocks of data according to said sequence address.
2. the transmission method of a kind of two-dimensional blocks of data as claimed in claim 1 is characterized in that, said parameter comprises source start address, source block length, source piece span, source total block data, purpose start address, purpose piece span.
3. the transmission method of a kind of two-dimensional blocks of data as claimed in claim 1 is characterized in that, said parameter comprises source start address, source piece span, purpose start address, purpose piece span, purpose block length, purpose total block data.
4. the transmission method of a kind of two-dimensional blocks of data as claimed in claim 1 is characterized in that, said parameter comprises source start address, source block length, block gap, source, source total block data, purpose start address, purpose block gap.
5. the transmission method of a kind of two-dimensional blocks of data as claimed in claim 1 is characterized in that, said parameter comprises source start address, block gap, source, purpose start address, purpose block length, purpose block gap, purpose total block data.
6. the transmission method of a kind of two-dimensional blocks of data as claimed in claim 1 is characterized in that, adopts the fixed bus address mode to transmit said two-dimensional blocks of data.
7. the transmission method of a kind of two-dimensional blocks of data as claimed in claim 1 is characterized in that, the step of said transmission two-dimensional blocks of data comprises, the step of next data block address of in transmission data block, looking ahead.
8. the transmission system of a two-dimensional blocks of data is characterized in that, comprising:
Processor generates the parameter of describing two-dimensional blocks of data;
The direct memory access dma device receives said parameter, and obtains the parameter that belongs to the parameter of source device and belong to destination device;
Source device receives the said parameter that belongs to source device, goes out the sequence address of the required transmission 2-D data of source device according to this calculation of parameter, and from this address reading of data, again with this data transmission to said dma device;
Destination device receives the said parameter that belongs to destination device, goes out the sequence address of the required reception 2-D data of destination device according to this calculation of parameter, and receives data according to this address.
9. the transmission system of a two-dimensional blocks of data is characterized in that, comprising:
Processor generate to be described the parameter of two-dimensional blocks of data, and obtains the parameter that belongs to the parameter of source device and belong to destination device;
Source device receives the said parameter that belongs to source device, goes out the sequence address of the required transmission 2-D data of source device according to this calculation of parameter, and from this address reading of data;
Destination device receives the said parameter that belongs to destination device, goes out the sequence address of the required reception 2-D data of destination device according to this calculation of parameter, and receives data according to this address.
10. the transmission system of a two-dimensional blocks of data is characterized in that, comprising:
The direct memory access dma device generate to be described the parameter of two-dimensional blocks of data, and obtains the parameter that belongs to the parameter of source device and belong to destination device;
Source device receives the said parameter that belongs to source device, goes out the sequence address of the required transmission 2-D data of source device according to this calculation of parameter, and from this address reading of data, again with this data transmission to said dma device;
Destination device receives the said parameter that belongs to destination device, goes out the sequence address of the required reception 2-D data of destination device according to this calculation of parameter, and receives data according to this address.
11. the transmission system like claim 8,9, one of 10 described a kind of two-dimensional blocks of data is characterized in that, this system adopts fixed bus address mode to transmit said two-dimensional blocks of data.
12. the transmission system of a two-dimensional blocks of data is characterized in that, comprising:
Processor generates the parameter of describing two-dimensional blocks of data;
The direct memory access dma device; Receive said parameter; And the parameter that obtains belonging to the parameter of source device and belong to destination device; Obtain the sequence address of the required transmission two-dimensional blocks of data of source device according to this calculation of parameter that belongs to source device, obtain the sequence address of the required reception 2-D data of destination device according to this calculation of parameter that belongs to destination device;
Source device receives the sequence address of the required transmission 2-D data of said source device, and from this address reading of data, again with this data transmission to said dma device;
Destination device receives the sequence address of the required transmission 2-D data of said destination device, and receives data according to this address.
13. the transmission system of a two-dimensional blocks of data is characterized in that, comprising:
The direct memory access dma device generate to be described the parameter of two-dimensional blocks of data, and obtains the parameter that belongs to the parameter of source device and belong to destination device; And go out the sequence address of the required transmission data of source device according to this calculation of parameter that belongs to source device, go out the sequence address of the required reception data of destination device according to this calculation of parameter that belongs to destination device;
Source device receives the sequence address from the required transmission data of the source device of said dma device, and from this address reading of data, again these data are sent to said dma device;
Destination device receives the sequence address from the required reception data of the destination device of said dma device, and receives data according to this address.
14. the transmission system like claim 10 or 13 described a kind of two-dimensional blocks of data is characterized in that, this system comprises that also notice generates parameter equipment, and this equipment is used for sending to said dma device the notice of transmission two-dimensional blocks of data.
15. the transmission system of a kind of two-dimensional blocks of data as claimed in claim 14 is characterized in that, it is processor that said notice generates parameter equipment.
16. the transmission system like claim 8,10,12, one of 13 described a kind of two-dimensional blocks of data is characterized in that said direct memory access dma device also is used to start the transmission of two-dimensional blocks of data; And/or the transmission of termination two-dimensional blocks of data.
17. the transmission system like claim 8,9,10,12, one of 13 described a kind of two-dimensional blocks of data is characterized in that said parameter comprises source start address, source block length, source piece span, source total block data, purpose start address, purpose piece span.
18. the transmission system like claim 8,9,10,12, one of 13 described a kind of two-dimensional blocks of data is characterized in that said parameter comprises source start address, source piece span, purpose start address, purpose piece span, purpose block length, purpose total block data.
19. the transmission system like claim 8,9,10,12, one of 13 described a kind of two-dimensional blocks of data is characterized in that said parameter comprises source start address, source block length, block gap, source, source total block data, purpose start address, purpose block gap.
20. the transmission system like claim 8,9,10,12, one of 13 described a kind of two-dimensional blocks of data is characterized in that said parameter comprises source start address, source block length, block gap, source, source total block data, purpose start address, purpose block gap.
21. the transmission system like claim 13 or 14 described a kind of two-dimensional blocks of data is characterized in that, the address of next data of looking ahead in the time of said dma device and source device transmission data; And/or the address of next data of looking ahead said dma device and destination device transmission data the time.
22. transmission system like claim 13 or 14 described a kind of two-dimensional blocks of data; It is characterized in that; Said dma device is connected with bus between source device, the destination device and comprises transmission channel and the passage of looking ahead, and this transmission channel and this passage of looking ahead walk abreast.
23. transmission system like one of claim 9-14 described a kind of two-dimensional blocks of data; It is characterized in that; Dma device receive from the two-dimensional blocks of data of source device to two-dimensional blocks of data fill, removing or counting operation, the two-dimensional blocks of data after will handling again sends.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103207847A (en) * | 2013-04-27 | 2013-07-17 | 杭州士兰微电子股份有限公司 | DMA (direct memory access) controller and direct memory access control method |
| CN107678987A (en) * | 2017-10-10 | 2018-02-09 | 郑州云海信息技术有限公司 | The method, apparatus and equipment of a kind of DMA transfer |
| CN108804356A (en) * | 2017-04-26 | 2018-11-13 | 上海寒武纪信息科技有限公司 | Data transmission device and method |
| CN108885596A (en) * | 2017-12-29 | 2018-11-23 | 深圳市大疆创新科技有限公司 | Data processing method, equipment, dma controller and computer readable storage medium |
| WO2019104639A1 (en) * | 2017-11-30 | 2019-06-06 | 深圳市大疆创新科技有限公司 | Calculation unit, calculation system and control method for calculation unit |
| CN109992542A (en) * | 2017-12-29 | 2019-07-09 | 深圳云天励飞技术有限公司 | A kind of data method for carrying, Related product and computer storage medium |
| CN109992541A (en) * | 2017-12-29 | 2019-07-09 | 深圳云天励飞技术有限公司 | A kind of data method for carrying, Related product and computer storage medium |
| WO2022011614A1 (en) * | 2020-07-15 | 2022-01-20 | 深圳市大疆创新科技有限公司 | Dma controller, electronic device, chip, mobile platform and data migration method |
| CN115080453A (en) * | 2022-07-20 | 2022-09-20 | 井芯微电子技术(天津)有限公司 | Address calculation array management method and system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030126185A1 (en) * | 2001-12-27 | 2003-07-03 | Yasufumi Itoh | Data driven information processor and data processing method for processing plurality of data while accessing memory |
| CN1510924A (en) * | 1998-12-15 | 2004-07-07 | 松下电器产业株式会社 | Image processor |
| CN101196860A (en) * | 2006-12-08 | 2008-06-11 | 深圳艾科创新微电子有限公司 | Optimized two-dimension DMA transmission method especially for access to image block |
-
2011
- 2011-09-30 CN CN2011103016455A patent/CN102508800A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1510924A (en) * | 1998-12-15 | 2004-07-07 | 松下电器产业株式会社 | Image processor |
| US20030126185A1 (en) * | 2001-12-27 | 2003-07-03 | Yasufumi Itoh | Data driven information processor and data processing method for processing plurality of data while accessing memory |
| CN101196860A (en) * | 2006-12-08 | 2008-06-11 | 深圳艾科创新微电子有限公司 | Optimized two-dimension DMA transmission method especially for access to image block |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103207847A (en) * | 2013-04-27 | 2013-07-17 | 杭州士兰微电子股份有限公司 | DMA (direct memory access) controller and direct memory access control method |
| CN103207847B (en) * | 2013-04-27 | 2015-07-22 | 杭州士兰微电子股份有限公司 | DMA (direct memory access) controller and direct memory access control method |
| CN108804356A (en) * | 2017-04-26 | 2018-11-13 | 上海寒武纪信息科技有限公司 | Data transmission device and method |
| CN107678987A (en) * | 2017-10-10 | 2018-02-09 | 郑州云海信息技术有限公司 | The method, apparatus and equipment of a kind of DMA transfer |
| CN107678987B (en) * | 2017-10-10 | 2021-06-29 | 郑州云海信息技术有限公司 | DMA transmission method, device and equipment |
| WO2019104639A1 (en) * | 2017-11-30 | 2019-06-06 | 深圳市大疆创新科技有限公司 | Calculation unit, calculation system and control method for calculation unit |
| CN108885596A (en) * | 2017-12-29 | 2018-11-23 | 深圳市大疆创新科技有限公司 | Data processing method, equipment, dma controller and computer readable storage medium |
| CN109992542A (en) * | 2017-12-29 | 2019-07-09 | 深圳云天励飞技术有限公司 | A kind of data method for carrying, Related product and computer storage medium |
| CN109992541A (en) * | 2017-12-29 | 2019-07-09 | 深圳云天励飞技术有限公司 | A kind of data method for carrying, Related product and computer storage medium |
| CN109992541B (en) * | 2017-12-29 | 2021-09-14 | 深圳云天励飞技术有限公司 | Data carrying method, computing device and computer storage medium |
| WO2022011614A1 (en) * | 2020-07-15 | 2022-01-20 | 深圳市大疆创新科技有限公司 | Dma controller, electronic device, chip, mobile platform and data migration method |
| CN115080453A (en) * | 2022-07-20 | 2022-09-20 | 井芯微电子技术(天津)有限公司 | Address calculation array management method and system |
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