CN102502605A - Electrically-induced reduction method for degraded graphene oxide - Google Patents
Electrically-induced reduction method for degraded graphene oxide Download PDFInfo
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- CN102502605A CN102502605A CN2011103511804A CN201110351180A CN102502605A CN 102502605 A CN102502605 A CN 102502605A CN 2011103511804 A CN2011103511804 A CN 2011103511804A CN 201110351180 A CN201110351180 A CN 201110351180A CN 102502605 A CN102502605 A CN 102502605A
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Abstract
The invention belongs to the technical field of manufacturing for carbon-based integrated circuit, and particularly relates to a reduction method for degraded graphene oxide. The reduction method for degraded graphene oxide disclosed by the invention comprises the following steps of: performing controllable reduction on a graphene oxide on a conductive substrate by a contact probe electrically-induced reduction method; and controlling the ingredients of the reduced graphene oxide by controlling the voltage applied by the probe of a conductive atomic force microscopy, thereby controlling the resistivity of the reduced graphene oxide. The method for reducing a graphene oxide by a conductive contact probe is a novel method for reducing a graphene oxide, and the method can be directly applied to preparation for planar device with nanoscale, thereby greatly simplifying the complexity of preparation for the device. Additionally, the method can also be used as basic machining process for grapheme-based electronic device.
Description
Technical field
The invention belongs to carbon back ic manufacturing technology field, be specifically related to a kind of method of reducing of graphene oxide.Be particularly related to a kind of use conducting atomic force microscopy (C-AFM) and prepare the method with nanometer etching Graphene.
Background technology
In field of semiconductor manufacture, along with the raising of integrated level, the dwindling of live width; The material foundation of current unicircuit---silicon reaches its materials processed limit---10 nano-scale linewidths gradually, and si-substrate integrated circuit can't be broken through its physics limitation and comprises the current delivery loss after 11 nanometers; Quantum effect; Therefore as if heat effect etc. are difficult to produce stable performance, product that integrated level is higher, and semiconductor industry has run into the bottleneck that can't go beyond.
Yet in 2004, the discovery of a kind of novel semiconductor material---Graphene (Graphene) let people see hope.The cellular two dimensional crystal that Graphene (Graphene) is made up of individual layer hexagonal cellular carbon atom is the one deck in the graphite.Shown in Figure 1 is the substruction synoptic diagram of Graphene.Graphene has zero forbidden band characteristic, and energy band structure is just as a uppercase X, and simultaneously, Graphene also has more than the high carrier mobility of silicon, so it is a kind of semiconductor material of excellent performance.Based on its unique two-dirnentional structure and physical property, Graphene is considered to be expected to continue in the unicircuit of future generation the important materials of Moore's Law.
The characteristic of Graphene high electron mobility is used in the high-frequency element it the earliest, and still, zero band gap properties but becomes the big obstacle that Graphene is applied in logical device.Discover; Graphene oxide after the reduction (rGO, reduced Graphene Oxide) energy gap to size between 0.5 eV between 0 eV, its electronic mobility adulterated conductive polymers that still can match in excellence or beauty can occur than Graphene; Be 33,000 times of adulterated amorphous silicon hydride.A kind of as in the method for reducing; Use the electricity of C-AFM to induce method of reducing that graphene oxide is reduced; Can accomplish to be a kind of effective and novel method, will further promote the carbon back development of integrated circuits the control of the nanoscale of reduzate and the control of reducing degree.
Summary of the invention
The objective of the invention is to propose a kind of reductive method that is applicable to graphene oxide, the method for reducing of this graphene oxide can obtain overall application in the carbon back large-scale integrated circuit manufacturing after surmounting silicon materials future.
The method of reducing of the graphene oxide that the present invention proposes also claims that the formation of graphene oxide and electricity induce the reduction working method, and concrete steps comprise:
Utilize chemical gaseous phase depositing process on the highly doped silicon chip substrate that provides, to form graphene layer;
Said graphene layer through oxide treatment, is formed graphene oxide;
Utilize the nano-scale conduction contact probe of voltage controlled to make the graphene oxide of insulativity be reduced to the Graphene of electroconductibility, perhaps the mixture of Graphene and graphene oxide.
Further, described oxide treatment is to adopt reactive ion etching and remote plasma oxidation, and selects semi-conductor etching degumming equipment commonly used to carry out oxidation.Use conducting atomic force microscopy to accomplish electricity and induce reduction; Said nano-scale conduction contact probe is the conducting probe (typical as 20 nanometer PtIr layers) that scribbles 15--30 nanometer PtIr layer, and the pressure reduction that is added between graphene oxide and the probe should be more than 3V.In addition, the residing substrate of graphene oxide is highly doped silicon chip (like the adulterated silicon chip of high density p type), always is in low potential, in room temperature environment, requires to keep relative air humidity preferably to be higher than 25%.
Graphene oxide can be regarded as and adsorbs a large amount of oxonium ion functional groups by Graphene and form; Attributes such as the electricity, optics of Graphene can be modulated by regulatory function group; Graphene oxide can be converted into the Graphene of electroconductibility, the perhaps mixture of Graphene and graphene oxide by relative insulativity under certain added electric field condition simultaneously.
The present invention adopts the contact probe electricity to induce method of reducing that the graphene oxide on the conductive substrates is reduced, and can accomplish effective control of reduction figure and reducing degree is similar to the thermal probe method of reducing.At room temperature in the air ambient; Can there be water membrane in the graphene oxide surface; Voltage difference between conducting probe and the sample can make the water molecules electrolysis, and the hydrogen ion of generation can be attracted by the graphene oxide of low potential and participate in the middle of the reduction process of graphene oxide.Control graphene oxide and the different pressure reduction between the conducting probe can be controlled the reducing degree of graphene oxide, and the control conducting probe can be controlled the figure that reduction obtains in the trend on graphene oxide surface.Therefore, this technology formation and electricity that can be called as graphene oxide induced method of reducing.
Adopt the contact probe electricity to induce reduction method that the graphene oxide on the conductive substrates is carried out controlled reduction, thereby control the resistivity of the composition control reduzate of reduction graphene oxide through control probe voltage.Utilize monatomic size conduction contact probe that graphene oxide is reduced the method for the reduction graphene oxide that is a kind of novelty, it can directly be applied in the middle of the planar device preparation of nanoscale, has simplified the complicacy of this kind device preparation greatly.This method also can be used as the basic complete processing of graphene-based electron device.
Description of drawings
Fig. 1 is the basic structural representation of Graphene.
Fig. 2 to Fig. 3 is the forming process synoptic diagram of graphene oxide provided by the invention.
Fig. 4 and Fig. 5 are respectively the synoptic diagram of the graphene oxide after the reduction provided by the invention.
Fig. 6 is the device diagram of method of reducing of the present invention.
Embodiment
It is more stable and reliable that use conducting atomic force microscopy incoming call proposed by the invention is induced the method for reduction graphene oxide, can be taken as the reduction work that a kind of conventional means is accomplished graphene oxide.The following stated be to adopt use conducting atomic force microscopy incoming call proposed by the invention to induce the embodiment of reduction graphene oxide.
In the drawings, explanation for ease, circuit and structure size are not represented physical size.Although the actual scale that reflects instrument and circuit that these figure can not entirely accurate, the substruction of pull up circuit in the middle of roughly principle of work of their instruments that still is complete reflection and the reduction process.
At first, doping forms highly doped substrate on the silicon substrate that cleaned 101.Wherein, adulterated method is ion implantation, and the impurity element of injection is a boron, and concentration is about 1 * 10
19Cm
-3To 1 * 10
21Cm
-3On substrate 101, form a layer graphene 102 through chemical vapour deposition (LPCVD) method then, as shown in Figure 2.Wherein, The concrete grammar that forms Graphene is: (wherein the gas flow ratio scope of methane/argon gas is about 1:2 to 1:5 through feeding rare gas elementes such as methane and argon gas; The total gas couette scope of methane and argon gas is about 280sccm to 480sccm, and its size depends on the size of the film of required formation), be heated to 1000 ℃ after; Reduce to room temperature more rapidly, like this can be on silicon oxide layer 102 Graphene of formation of deposits 6-10 layer.
Next, graphene layer 102 is carried out oxide treatment form graphene oxide layer 200, as shown in Figure 3.Wherein, said method for oxidation is to adopt reactive ion etching (RIE) and remote plasma oxidation, and this method for oxidation is prone to and the CMOS process compatible, and can realize large-scale production graphene oxide layer.Can select semi-conductor etching degumming equipment commonly used to carry out oxidation when Graphene is carried out oxidation, directly graphene layer not carried out the ion contact.Particularly; In the processing condition of oxidation; The gas flow ratio scope that power is about the oxygen/argon of 600 W to 1000W, feeding is 1:1 to 1:3, and the flow size of oxygen/argon depends on that film forms size, and the scope of the total flux of oxygen and argon gas is about 200sccm to 400sccm.
Next, use C-AFM that graphene oxide 200 is carried out electricity and induce reduction.Reduction process does; In room temperature environment, keep relative air humidity between 40% to 60%, in AFM (AFM), select conducting atomic force microscopy module (C-AFM Module); Use contact mode (Contact Mode); To between 10 V, the control probe is at sample 200 surface scans, through about 3 minutes to 5 minutes at 4 V for the voltage difference of control probe and sample; One deck 10 nanometers are to 80 nanometer thickness, and the area size is that micron-scale level graphite olefinic oxide layer 300 will be by thorough reduction.Through detecting, under 5V voltage, 0 pA before certain any size of current can never be reduced on the sample has increased to about 300 pA after the reduction to 2 pA.Here be noted that same panel region, under the constant situation of pressure reduction, resistivity reduces along with the increase of sweep time, but is not unlimited reduction.Graphene oxide 300 after the resulting reduction has just had characteristic of semiconductor, and its resistivity and can be with and can and be reduced degree modulation through the graphene oxide number of plies can satisfy the different application demand on a large scale.
It should be noted that; The conduction contact probe can form certain physical abuse to sample surfaces; And the set(ting)value of the socle girder amount of bow under the adjusting contact mode (Deflection Setpoint) can be accomplished reduction under the situation that as far as possible reduces damage; And the scanning of long-time (＞10 minutes) also can cause damage to sample, so in implementation process, take to control the socle girder amount of bow and the surface sweeping time is reduced the physical abuse of probe to sample as far as possible.
As stated, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the specific examples described in the specification sheets.
Claims (7)
1. the electricity of the graphene oxide of degenerating is induced method of reducing, it is characterized in that concrete steps are:
Utilize chemical gaseous phase depositing process on the highly doped silicon chip substrate that provides, to form graphene layer;
Said graphene layer is formed graphene oxide through oxide treatment;
Utilize the nano-scale conduction contact probe of voltage controlled to make the graphene oxide of insulativity be reduced to the Graphene of electroconductibility, perhaps the mixture of Graphene and graphene oxide.
2. method of reducing according to claim 1 is characterized in that described oxide treatment is to adopt reactive ion etching or remote plasma oxidation, and selects semi-conductor etching degumming equipment commonly used to carry out oxidation.
3. method of reducing according to claim 1 is characterized in that using conducting atomic force microscopy to accomplish electricity and induces reduction, and employed conduction contact probe has 15--30 nanometer thickness PtIr coating.
4. method of reducing according to claim 1 it is characterized in that the current potential of graphene oxide in the middle of reduction process is lower than the current potential of probe all the time, and potential difference is more than 3V.
5. method of reducing according to claim 1, what it is characterized in that the substrate use is the adulterated silicon chip of high density p type.
6. method of reducing according to claim 1 is characterized in that in the middle of reduction process the room temperature environment relative air humidity is higher than 25%.
7. method of reducing according to claim 2; It is characterized in that the processing condition of selecting semi-conductor etching degumming equipment commonly used to carry out oxidation are: power 600 W to 1000W; The gas flow ratio scope of aerating oxygen/argon gas is 1:1 to 1:3, and the scope of the total flux of oxygen and argon gas is 200sccm to 400sccm.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103935956A (en) * | 2014-04-15 | 2014-07-23 | 江苏大学 | Graphene nanoribbon boundary trimming method based on tip-enhanced Raman spectroscopy |
| CN104217931A (en) * | 2013-05-29 | 2014-12-17 | 国家纳米科学中心 | Graphene doping method and doped graphene |
| CN105000552A (en) * | 2015-07-24 | 2015-10-28 | 浙江大学 | Preparation method for graphene oxide |
| CN105152165A (en) * | 2015-09-01 | 2015-12-16 | 复旦大学 | Method of directly synthesizing large-area graphene oxide based on plasma-enhanced chemical vapor deposition |
| CN107768254A (en) * | 2017-10-17 | 2018-03-06 | 江苏大学 | A kind of reduced graphene electrode MoS2The preparation method of field-effect transistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101844760A (en) * | 2010-04-29 | 2010-09-29 | 中国科学院化学研究所 | Preparation method and application of redox graphene |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101844760A (en) * | 2010-04-29 | 2010-09-29 | 中国科学院化学研究所 | Preparation method and application of redox graphene |
Non-Patent Citations (1)
| Title |
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| MING ZHOU ET AL: "Controlled synthesis of large aera and patterned electrochemically reduced graphene oxide films", 《CHEM.EUR.J.》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217931A (en) * | 2013-05-29 | 2014-12-17 | 国家纳米科学中心 | Graphene doping method and doped graphene |
| CN103935956A (en) * | 2014-04-15 | 2014-07-23 | 江苏大学 | Graphene nanoribbon boundary trimming method based on tip-enhanced Raman spectroscopy |
| CN103935956B (en) * | 2014-04-15 | 2016-03-02 | 江苏大学 | A kind of graphene nanobelt border method of modifying based on Tip-Enhanced Raman Spectroscopy |
| CN105000552A (en) * | 2015-07-24 | 2015-10-28 | 浙江大学 | Preparation method for graphene oxide |
| CN105152165A (en) * | 2015-09-01 | 2015-12-16 | 复旦大学 | Method of directly synthesizing large-area graphene oxide based on plasma-enhanced chemical vapor deposition |
| CN107768254A (en) * | 2017-10-17 | 2018-03-06 | 江苏大学 | A kind of reduced graphene electrode MoS2The preparation method of field-effect transistor |
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Application publication date: 20120620 |