CN102495346B - Generally applicable optimization method for test output pins of integrated circuit chip - Google Patents
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Abstract
A generally applicable optimization method for test output pins of an integrated circuit chip relates to an optimization method for test output pins of a system level chip and solves the problem that the existing test method for the integrated circuit chip does not take the influence on structures of a testing circuit caused by a tested circuit into account, accordingly the testing circuit is led to be complicate in structure, and the hardware cost of the testing circuit is high. The method is achieved by the following steps: firstly, adopting two identical reference circuits and inducing fault into one circuit; secondly, exerting the same testing stimulation into the two reference circuits; thirdly, observing the testing response and respectively storing response data; fourthly, analyzing the obtained testing response data; and fifthly, optimizing the output pins according to requirements of known fault coverage rate. The generally applicable optimization method for test output pins of the integrated circuit chip has the advantages of having simple testing circuit structure and being low in cost of hardware and can be widely applied to various combination circuits and used for optimizing output pins of timing sequence circuits after improvement.
Description
Technical field
The present invention relates to system level chip detecting output pin optimization method.
Background technology
Past four, Moore's Law was followed in the development of integrated circuit always during the decade, and the scale of integrated circuit was twice expansion every 18 months, had entered now the deep-submicron stage.Along with scale and the integrated level of integrated circuit improve constantly, the manufacturing cost of chip is also along with reduction, but the raising of chip complexity makes the difficulty of test of chip increasing, and cost is also more and more higher.Therefore how to reduce the problem that the testing complex degree of chip has also just become people to be concerned about very much.
Chia-Shun Lai and Chin-Long Wey have proposed a kind of large output function module to be divided into several less output function modules for self-checking circuit verifier, then with several little verifiers, replace the method for original larger verifier, this method has reduced the requirement to self-checking circuit verifier when circuit performance not being impacted, and has reduced the hardware cost of self-checking circuit verifier; The people such as Sudhakar M.Reddy and Irith Pomeranz have proposed a kind of new built-in self-test (BIST:Built-In Self-Test) pseudorandom test and excitation generator, this actuation generator utilizes Markov resource to design with position technique for fixing, experimental result shows in the situation that not affecting fault coverage, this method can reduce test circuit complexity to a great extent, and the hardware cost of test circuit is significantly reduced.But how said method all only considers the structure of retrofit testing circuit itself, and does not consider the impact that tested circuit produces test circuit structure.
Summary of the invention
The impact that the present invention does not consider that in order to solve existing IC chip test method tested circuit produces test circuit structure, and then cause test circuit structure complexity, the problem that test circuit hardware cost is high, and the IC chip test output pin optimization method with general applicability proposing.
The IC chip test output pin optimization method with general applicability, it is realized by following steps:
Step 1: get two identical reference circuits in the reference circuit storehouse of international standard circuit collection, and inject respectively therein three kinds of faults that pre-set in a reference circuit, described in the fault that pre-sets comprise and fix 0 type, fix 1 type and three fault types of upset;
Step 2: two reference circuits described in step 1 are applied to identical test and excitation, and described two reference circuits are a non-fault circuit and an injection faulty circuit;
Step 3: observe the test response of described two reference circuits and preserve respectively response data;
Step 4: after three kinds of faults are all injected, the test response data obtaining is analyzed; And require the output pin of circuit-under-test to be optimized according to the known fault coverage setting in advance.
The present invention needs monitored output pin number by reducing circuit-under-test in actual test, and test circuit structure is simplified, and hardware cost reduces.The method of the invention is directly optimized combinational circuit, and experimental result shows that the number of output pin when the fault coverage that reaches 90% can be reduced to below 50% of former sum; Experiment by the c3540 in ISCAS circuit and c1908 circuit is known, when fault coverage is 90%, two kinds of circuit need monitored number of pins can be reduced to below 50% of former output pin sum, particularly in c3540 circuit, even can be reduced to below 25% of former output pin sum.The method of the invention can be widely used in various combinational circuits and also can carry out output pin optimization to sequential circuit by improving.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that the method for the invention step 1 is injected failure mode.
Embodiment
Embodiment one: have the IC chip test output pin optimization method of general applicability described in present embodiment, it is realized by following steps:
Step 1: get two identical reference circuits in the reference circuit storehouse of international standard circuit collection, and inject respectively therein three kinds of faults that pre-set in a reference circuit, described in the fault that pre-sets comprise and fix 0 type, fix 1 type and three fault types of upset;
Step 2: two reference circuits described in step 1 are applied to identical test and excitation, and described two reference circuits are a non-fault circuit and an injection faulty circuit;
Step 3: observe the test response of described two reference circuits and preserve respectively response data;
Step 4: after three kinds of faults are all injected, the test response data obtaining is analyzed; And according to the requirement of the known fault coverage rate setting in advance, the output pin of circuit-under-test is optimized.
Embodiment two: in conjunction with Fig. 1, present embodiment is described, present embodiment and embodiment one difference are to inject in step 1 fault and adopt alternative MUX to replace the injection mode of the intermediate connection between higher level's door and subordinate's door of reference circuit.Other parameter is identical with embodiment one.
Embodiment three: present embodiment and embodiment one or two differences are that the test and excitation described in step 2 adopts Mintest test set.Other parameter is identical with embodiment one or two.
Embodiment four: present embodiment and embodiment three differences are that the process of observing the test response of described two reference circuits in step 3 and preserving respectively response data is realized by following steps:
Step 3 one: two input ends that the every pair of corresponding output pin in two reference circuits are connected to a comparer;
Step 3 two: the each comparator output terminal in step 3 one all connects a storer separately;
Step 3 three: each comparer judges that whether two input signal is identical, as identical, this comparer output 0, and in storer, deposit 0 in; As difference, this comparer output 1, and in storer, deposit 1 in.
Other parameter is identical with embodiment three.
Embodiment five: present embodiment and embodiment one, two or four differences are after three kinds of faults are all injected, the test response data obtaining to be analyzed described in step 4, and the process output pin of circuit-under-test being optimized according to the requirement of the known fault coverage rate setting in advance, by following steps, realized:
Step 4 one: take the fault injected as row, output pin is set and injects the relation table between fault as row using the output pin of circuit-under-test;
Step 4 two: solve fault coverage, described fault coverage solution formula is as follows:
In formula, parameter Total faults representative is in all faults of injecting, and parameter Detectable faults is the fault that the normal operation of circuit is impacted; Some fault can not impact or not calculative fault the normal operation of circuit, and the fault coverage that is above-mentioned fault of parameter F ault coverage statement; Parameter S elected-Detectable faults represents the fault that the normal operation of circuit is impacted and is detected; Parameter S elected coverage is calculative fault;
1 quantity in the storer that inspection is connected with each output pin, maximum output pin corresponding to storer of quantity of choosing storage 1 selected pin 1 as first, described first has selected pin 1 for detecting the pin of maximum faults, the i.e. the highest pin of fault coverage;
Step 4 three: more remaining output pin is screened, the principle of screening is to detect the maximum first pin that has selected 1 non-detectable fault of pin; By obtaining output pin after screening, as second, selected pin 2;
Step 4 four: whether the described first number of faults of having selected pin 1 and second to select pin 2 to detect reaches predefined number of faults, first selected pin 1 and second to select the fault coverage of pin 2 whether to meet the requirement that presets fault coverage, if do not met, according to second, selected the screening principle of pin 2 to continue to select the 3rd to select pin 3, the described the 3rd has selected pin 3 to comprise maximum first and selected pin 1 and second to select the pin of pin 2 non-detectable faults by detecting, and whether the fault that judgement has selected pin to detect again meets the requirement of fault coverage, if do not met, continue to select the 4th to select pin 4 to n to select pin n according to above-mentioned screening principle, until the fault that the pin having selected can detect meets the requirement that presets fault coverage, stop screening and exiting,
Step 4 five: only need can meet predefined fault coverage to selecting pin to detect, complete the optimization to integrated circuit (IC) chip output pin.
Principle of the present invention: in all output pins of circuit-under-test, there is larger difference in the fault-detecting ability of each pin, the number of faults that the more and some other pin of number of faults that some pin can detect can detect is considerably less, so we just can be by being optimized and obtaining the pin that those fault-detecting abilities are stronger the output pin of circuit-under-test.Pin stronger these detection failure abilities is needed to monitored pin in reality, and this greatly reduces with regard to the number of pins that makes the required monitoring of test circuit.The reduction of the required monitoring number of pins of test circuit can make the complexity of test circuit and scale also reduce accordingly, and the hardware cost of final test circuit also just reduces along with the complexity of test circuit and the reduction of scale.
Having proposed OP method (the OPtimization of output pins) is herein optimized the output pin of circuit-under-test.When the monitored output pin number of circuit-under-test reduces, the fault coverage of whole circuit also has certain reduction, and institute in this way will reach balance exactly between hardware cost and fault coverage.By analysis hereinafter, can find that, when fault coverage is reduced to 90%, the hardware cost of test circuit will reduce more than 50%.In order to realize the optimization to circuit-under-test output pin, constructed the simulation frame of system herein, and proposed a kind of method for implanting fast and effectively and optimum data processing method simultaneously.The method of the invention is injected fixed and two kinds of faults of upset, and stuck-at fault is mainly to imitate the permanent fault causing due to physical imperfection in circuit, and upset is mainly the transient fault imitating in circuit.
Used herein to fault filling method be that an alternative MUX of the intermediate connection between higher level's door U1 and the door U2 of subordinate is replaced, as shown in Figure 1; Intermediate connection between higher level's door U1 and the door U2 of subordinate is replaced by a multichannel Chooser; In side circuit, need to inject a large amount of faults, for example in ISCAS reference circuit c3540, there are 1669 lines (1647 intermediate connection and 22 output pins), each line all needs to replace by above-mentioned MUX, if every line is replaced to MUX by manual method, not only needs long time but also is easy to make a mistake.The present invention proposes a kind of method of automatic replacement, ISCAS reference circuit is replaced with to MUX by these lines automatically software program is in service;
The every pair of corresponding output pin in two reference circuits is connected to two input ends of a comparer; Each comparer all connects a storer separately; Judgement, for the output response of two reference circuits described in each test and excitation, as identical, deposits 0 in storer; As difference, in storer, deposit 1 in.Take the fault injected as row, output pin is set using the output pin of circuit-under-test as row and injects the relation table between fault; Relation table is a two-dimensional matrix, and it has reflected the relation between all faults and each output pin injecting.The structure of relation table has utilized the storer in fault simulation experiment, using the data that store in each storer as row, and using each fault as row, table one is only schematic diagram of method described in the application, in table one, comprised altogether that 9 are injected fault and 6 output pins, described 6 output pins we in advance according to being defined as successively pin 1 to pin 6 from upper left to bottom right horizontally-arranged, be the Pin1 to Pin6 in table.As above said, 1 in table represents that this fault can be monitored, and 0 represents that this fault cannot be detected.For example, the second row second in table is classified 0 as and is shown that pin 2 can not detect the second failure of injection, and the second row the 3rd is classified 1 as and shown that pin 2 can be by the fault detect of the 3rd injection out.
Table one
| F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | |
| Pin1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| Pin2 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| Pin3 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
| Pin4 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Pin5 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Pin6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
In traditional fault coverage method for solving, exist so some pins, their detection failure abilities own are stronger, but most or all can be detected by the stronger pin of those detectabilities the fault that they can detect again, for example pin 2 in table one.Therefore, for try to achieve fault coverage optimum solution we need to and inject the relation table of fault to output pin and be optimized, optimize later result as shown in following table.
Table two: the table forming after optimizing for the first time
| F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | |
| Pin1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| Pin2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Pin3 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Pin4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Pin5 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Pin6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
Table three: through optimizing for the second time the table of formation
| F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | |
| Pin1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| Pin2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Pin3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Pin4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Pin5 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Pin6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
Table four: last optimum results
| F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | |
| Pin1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| Pin2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Pin3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Pin4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Pin5 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Pin6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
In table four, first has selected pin 1 to inject the detection case of fault to each is saved, because first selected pin 1 can detect maximum faults, no matter is to adopt any optimized algorithm, and first to have selected pin 1 be all the output pin that must be selected.The step of optimized algorithm is as follows: (1), choose pin and can detect the pin of maximum faults.The pin 1 of for example table one, injected altogether 9 faults, and pin 1 can detect wherein 6, has 3 faults not detect in table, and these 3 faults are respectively F2, F5 and F8, and the fault coverage that now can reach is 66.67%.(2), pin 1 is selected after choosing again and can be detected the pin that comprises maximum pin 1 non-detectable faults, and checks whether the fault coverage that can reach while selecting this two pins meets the demands.For example in Table 1, in 3 non-detectable faults of pin 1, pin 2,3,6 can detect respectively wherein 1, and pin 4 can not detect wherein any one and pin 5 can detect wherein 2, so should select pin 5 as monitored pin.Selecting after pin 5, the fault that pin 1 and pin 5 can be detected merges, and now finds to monitor pin 1 and pin 5 can detect 8 faults simultaneously, only has F8 to detect, and the fault coverage now reaching is 88.89%.The fault coverage whether fault coverage that inspection now can reach meets the demands, if meet the requirement of fault coverage, selects pin 1 and pin 5 as pin monitored in reality.(3), if can not meet the requirement of fault coverage in (2) step, continue to select to detect and comprise the pins that selected at most the non-detectable fault of pin, and whether inspection now meets the requirement of fault coverage, as met, exit and select these selecteed pins, if do not met this, repeat (3).For example in pin 1 and the non-detectable fault of pin 5, only have pin 6 to detect in Table 1, whether the fault coverage that inspection can reach while choosing this 3 pins meets the demands, if met, select pin 1,5,6, if do not met, repeat to choose until meet the condition of fault coverage.
To the checking of optimization method of the present invention: be N (number of 0 < N < output pin) if need the output pin number of monitoring, so just all combinations of choosing N pin from whole output pins are all listed, and then selected that wherein to make fault coverage be the combination of maximum one.Because the method for exhaustion has been considered each combined situation for concrete N value, so the method for exhaustion can be in the hope of optimum solution.
Due to each value of N (number of 0 < N < output pin) is verified need oversize time and also when output pin number is more present equipment do not support this verification method yet, so the present invention will verify N=5, N=8, N=10, tetra-kinds of situations of N=15, result as shown in Table 5.
Table five
The fault coverage method for solving that the present invention proposes when the pin number N=5 choosing, N=8, N=10, N=15 can reach the fault coverage identical with the method for exhaustion, therefore the method that the present invention proposes is optimum, especially, when N=5, the method that the present invention proposes is identical with the selected pin of the method for exhaustion.When the number of pins of choosing is more, the method that the present invention proposes and the method for exhaustion to choose in result some pin different, reason is the pin weak for some detectabilities, has multiple different combination can detect identical number of faults.For example selecting in Table 1 the combination of pin 1 and pin 2 is identical with the fault coverage of selecting the combination of pin 1 and pin 3 to reach.Therefore reach identical fault coverage and can have multiple different combination.In sum, the fault coverage method for solving that the present invention proposes makes output pin optimization efficiency the highest.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For this person of an ordinary skill in the technical field, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to the definite scope of patent protection of claims that the present invention submits to.
Claims (3)
1. there is the IC chip test output pin optimization method of general applicability, it is characterized in that it is realized by following steps:
Step 1: get two identical reference circuits in the reference circuit storehouse of international standard circuit collection, and inject respectively therein three kinds of faults that pre-set in a reference circuit, described in the fault that pre-sets comprise and fix 0 type, fix 1 type and three fault types of upset;
Step 2: two reference circuits described in step 1 are applied to identical test and excitation, and described two reference circuits are a non-fault circuit and an injection faulty circuit;
Step 3: observe the test response of described two reference circuits and preserve respectively response data;
Step 3 is realized by following steps:
Step 3 one: two input ends that the every pair of corresponding output pin in two reference circuits are connected to a comparer;
Step 3 two: the each comparator output terminal in step 3 one all connects a storer separately;
Step 3 three: each comparer judges that whether two input signal is identical, as identical, this comparer output 0, and in storer, deposit 0 in; As difference, this comparer output 1, and in storer, deposit 1 in;
Step 4: after three kinds of faults are all injected, the test response data obtaining is analyzed; And according to the requirement of the known fault coverage rate setting in advance, the output pin of two reference circuits is optimized;
Step 4 is realized by following steps:
Step 4 one: take the fault injected as row, output pin is set and injects the relation table between fault as row using the output pin of two reference circuits;
Step 4 two: solve fault coverage, described fault coverage solution formula is as follows:
In formula, parameter Detectable faults is the fault that the normal operation of circuit is impacted, and parameter S elected-Detectable faults represents the fault that the normal operation of circuit is impacted and is detected; Parameter S elected coverage is calculative fault coverage;
1 quantity in the storer that inspection is connected with each output pin, maximum output pin corresponding to storer of quantity of choosing storage 1 selected pin 1 as first, described first has selected pin 1 for detecting the pin of maximum faults, the i.e. the highest pin of fault coverage;
Step 4 three: more remaining output pin is screened, the principle of screening is to detect maximum and the first pin that has selected 1 non-detectable fault of pin; By obtaining output pin after screening, as second, selected pin 2;
Step 4 four: whether the described first number of faults of having selected pin 1 and second to select pin 2 to detect reaches predefined number of faults, first selected pin 1 and second to select the fault coverage of pin 2 whether to meet the requirement that presets fault coverage, if do not met, according to second, selected the screening principle of pin 2 to continue to select the 3rd to select pin 3, the described the 3rd selected pin 3 for can detect comprise maximum, and first has selected pin 1 and second to select the pin of 2 non-detectable faults of pin, and judgement has selected the fault coverage of pin whether to meet the requirement that presets fault coverage again, if do not met, continue to select the 4th to select pin 4 to n to select pin n according to above-mentioned screening principle, until the fault coverage of the pin having selected meets the requirement that presets fault coverage, stop screening and exiting,
Step 4 five: only need can meet predefined fault coverage to selecting pin to detect, complete the optimization to integrated circuit (IC) chip output pin.
2. the IC chip test output pin optimization method with general applicability according to claim 1, is characterized in that injecting in step 1 fault and adopts alternative MUX to replace the injection mode of the intermediate connection between higher level's door and subordinate's door of reference circuit.
3. the IC chip test output pin optimization method with general applicability according to claim 1 and 2, is characterized in that the test and excitation described in step 2 adopts Mintest test set.
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