CN102487023A - Salient point and forming method thereof - Google Patents
Salient point and forming method thereof Download PDFInfo
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- CN102487023A CN102487023A CN2010105694330A CN201010569433A CN102487023A CN 102487023 A CN102487023 A CN 102487023A CN 2010105694330 A CN2010105694330 A CN 2010105694330A CN 201010569433 A CN201010569433 A CN 201010569433A CN 102487023 A CN102487023 A CN 102487023A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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Abstract
The invention discloses a salient point and a forming method thereof, wherein the forming method comprises the following steps of: providing a semiconductor substrate, forming a metal padding layer and a passivation layer on the semiconductor substrate, and embedding the metal padding layer into the passivation layer; flattening the passivation layer till the metal padding layer is exposed, wherein the passivation layer is flush with the surface of the metal padding layer; forming a metal lead on the metal padding layer by adopting a metal-wire welding process; and carrying out backflow to form the salient point. According to the salient point and the forming method of the salient point, the short-circuit phenomenon when in follow-up working is effectively prevented and the electric performance of the semiconductor device is improved.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor device, relate in particular to salient point and forming method thereof.
Background technology
Along with the continuous development of integrated circuit technique, electronic product more and more develops to miniaturization, intellectuality, high-performance and high reliability direction.And the integrated circuit encapsulation not only directly affects integrated circuit, electronic module and even machine performance, but also is restricting miniaturization, low cost and the reliability of whole electronic system.Progressively dwindle in the IC wafer size, under the situation that integrated level improves constantly, electronics industry has proposed increasingly high requirement to the integrated circuit encapsulation technology.
Flip-chip (flip chip) technology is the soldered ball that forms through at chip surface; The chip upset is formed with base plate to be connected; Thereby reduce package dimension; Satisfy the high-performance (like high speed, high frequency, littler pin) of electronic product, the requirement of little profile, make product have good electric property and heat transfer property.
Salient point (bump) manufacturing technology is a key technology in the flip-chip.Salient point of the prior art normally scolder through certain process deposits on chip metal bed course, through the metal soldered ball that uniform temperature reflux to form, application number is that the one Chinese patent application file of 200510025198.X provides this technology.Prior art can also adopt the mode of metal wire welding (wire bond) to form salient point; Concrete technology: as shown in Figure 1; On Semiconductor substrate 100, form the first metal layer, said the first metal layer is that Al, Cu or their alloy constitute, and said the first metal layer is for adopting the preparation of physical vapor deposition (PVD) method; Adopt existing photoetching and the graphical the first metal layer of etching technique then, form metal bed course 104.
Then, on Semiconductor substrate 100 and metal bed course 204, form passivation layer 102, said passivation layer 202 can be high molecular polymers such as silica, silicon nitride or benzocyclobutene (BCB), polytetrafluoroethylene, polyimides; Adopt existing photoetching and developing technique then, on passivation layer 102, form opening, said opening exposes metal bed course 104.
With reference to Fig. 2, adopt the metal wire welding procedure on metal bed course 104, to stamp plain conductor 106; Backflow stanniferous plain conductor 106 forms salient point.
Yet can produce situation as shown in Figure 3 in the process of employing metal wire welding procedure formation plain conductor 106; Because the deviation during routing makes plain conductor 106 fail to place fully on the metal bed course 104; Can be on the metal bed course 104 by many parts, few part then is offset on the passivation layer 102.In the routing process, have the process of compacting, cause the passivation layer 102 on the metal bed course 104 can be, and then the phenomenon that is short-circuited during follow-up work by pressure break, influence the electrical property of semiconductor device.
Summary of the invention
The problem that the present invention solves provides a kind of salient point and forming method thereof, prevents passivation layer by pressure break, produces short circuit phenomenon.
For addressing the above problem, the formation method of a kind of salient point of the present invention comprises: Semiconductor substrate is provided, is formed with metal bed course and passivation layer on the said Semiconductor substrate, said metal bed course is embedded in the passivation layer; The planarization passivation layer is to exposing the metal bed course, and said passivation layer flushes with the metal gasket laminar surface; Adopt the metal wire welding procedure on the metal bed course, to form plain conductor; The reflow metal lead forms salient point.
Optional, the technology of said planarization passivation layer is chemical mechanical milling method or mechanical milling method.
Optional, the material of said stanniferous plain conductor is for dissolve leypewter, high slicker solder lead alloy, sn-ag alloy or SAC alloy altogether.
Optional, the temperature of backflow stanniferous plain conductor is 220 ℃～350 ℃.
Optional, on said metal bed course, form plain conductor and also comprise before: on the metal bed course, form inculating crystal layer.
Optional, the material of said inculating crystal layer is a copper.
Optional, be formed with one deck passivation layer and one deck metal gasket layer at least at least on the said Semiconductor substrate successively, the flush of the metal bed course of said each layer passivation layer and equivalent layer.
The present invention also provides a kind of salient point, comprising: Semiconductor substrate; Be positioned at metal bed course and passivation layer on the Semiconductor substrate, said metal bed course flushes with passivation layer surface; Be positioned at the salient point on the metal bed course.
Optional, the material of said stanniferous plain conductor is for dissolve leypewter, high slicker solder lead alloy, sn-ag alloy or SAC alloy altogether.
Optional, also include inculating crystal layer between said metal bed course and the salient point.
Optional, the material of said inculating crystal layer is a copper.
Compared with prior art, the present invention has the following advantages: passivation layer is planarized to the flush with the metal bed course.Avoided since passivation layer partly be positioned on the metal bed course situation; When following adopted metal wire welding procedure is stamped plain conductor on the metal bed course; Passivation layer can be by pressure break, and the phenomenon that is short-circuited when effectively having prevented follow-up work has improved the electrical property of semiconductor device.
Further adopt chemical mechanical milling method planarization passivation layer; Can when on the metal bed course, stamping plain conductor, produce skew with smoothization of passivation layer to flushing with the metal gasket laminar surface with the metal wire welding procedure; Make plain conductor partly drop on the passivation layer; Can the passivation layer pressure break not avoided the generation of short circuit phenomenon yet, improve the electrical property and the reliability of semiconductor device.
Description of drawings
Fig. 1 to Fig. 2 is the sketch map of existing technology bump making process;
The salient point that the existing technology of Fig. 3 is made produces the design sketch of defective;
Fig. 4 is the embodiment flow chart of bump making process of the present invention;
Fig. 5, Fig. 6, Fig. 7 a, Fig. 7 b, Fig. 8 a, Fig. 8 b are the first embodiment sketch mapes of bump making process of the present invention;
Fig. 9～Figure 13 is the second embodiment sketch map of bump making process of the present invention.
Embodiment
The inventor finds because prior art is normally used etching mode etching passivation layer; Make it to expose the metal bed course; If the words etching passivation layer is extremely surperficial and that the metal bed course flushes fully; Can be because being difficult to grasp make between passivation layer and the metal bed course and leaving the space of etching parameters, metal material flow to down face mask layer through the space, the generation short circuit phenomenon in the time of can making follow-up formation salient point; Therefore, adopt etching technics etching passivation layer, can stay the part passivation layer in the corner of metal bed course later, in order to protection metal bed course in etching.But, when adopting the metal wire welding procedure to form salient point, make plain conductor fail to place fully on the metal bed course if produce deviation during routing, wherein many parts are on the metal bed course, and few part then is offset on the passivation layer; Owing to during at routing, have the process of compacting in the metal wire welding procedure, cause the passivation layer on the metal bed course can be, and then the phenomenon that is short-circuited during follow-up work by pressure break, influence the electrical property of semiconductor device.
The present invention is directed to the problems referred to above, the inventor has provided the method for following bump making process through research; Idiographic flow is as shown in Figure 4, and execution in step S11 provides Semiconductor substrate; Be formed with metal bed course and passivation layer on the said Semiconductor substrate, said metal bed course is embedded in the passivation layer; Execution in step S12, the planarization passivation layer is to exposing the metal bed course, and said passivation layer flushes with the metal gasket laminar surface; Execution in step S13 adopts the metal wire welding procedure on the metal bed course, to form plain conductor; Execution in step S14, the reflow metal lead forms salient point.
Salient point based on above-mentioned execution mode forms comprises: Semiconductor substrate; Be positioned at metal bed course and passivation layer on the Semiconductor substrate, said metal screen layer flushes with passivation layer surface; Be positioned at the salient point on the metal screen layer.
The present invention is planarized to the flush with the metal bed course with passivation layer.Avoided because passivation layer partly is positioned at the situation on the metal bed course; When following adopted metal wire welding procedure is stamped plain conductor on the metal bed course; Passivation layer can be by pressure break, and the phenomenon that is short-circuited when effectively having prevented follow-up work has improved the electrical property of semiconductor device.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
First embodiment
Fig. 5, Fig. 6, Fig. 7 a, Fig. 7 b, Fig. 8 a, Fig. 8 b are the first embodiment sketch mapes of bump making process of the present invention.With reference to shown in Figure 5, Semiconductor substrate 200 is provided, said Semiconductor substrate 200 is for having the Semiconductor substrate of semiconductor device, in order to simplify diagrammatic sketch, here only with blank Semiconductor substrate signal.On Semiconductor substrate 200, form metal bed course 204; Concrete formation technology is following: at first on Semiconductor substrate 200, form the first metal layer; Said the first metal layer is that Al, Cu or their alloy constitute, and the thickness range of said the first metal layer is 400nm～800nm, and said the first metal layer is for adopting the preparation of physical vapor deposition (PVD) method; Adopt existing photoetching and the graphical the first metal layer of etching technique then, form metal bed course 204.Then, on Semiconductor substrate 200, form the passivation layer 202 that covers metal bed course 204.
In the present embodiment, the method that forms said passivation layer 202 is a chemical vapour deposition technique.Said passivation layer 202 can be high molecular polymers such as silica, silicon nitride or benzocyclobutene (BCB), polytetrafluoroethylene, polyimides.Said passivation layer 202 is positioned at the thickness of the thickness of metal bed course 204 both sides more than or equal to metal bed course 204.
As shown in Figure 6, said passivation layer 202 is carried out flatening process, until exposing metal bed course 204, make the surface of metal bed course 204 and the flush of the passivation layer 202 after the grinding, metal bed course 204 is embedded between the passivation layer 202.
In the present embodiment, said flatening process is chemical mechanical milling method or mechanical milling method.
Behind the planarization passivation layer; As an instance; Shown in Fig. 7 a, adopt metal wire welding (wirebond) method on metal bed course 204, to form plain conductor 206, said plain conductor 206 can be one; Also can be two, three ... N (N is a natural number), concrete quantity be according to the size and the decision of the spacing between salient point of the salient point of the thickness of plain conductor 206, follow-up formation.With diameter is that 30 microns plain conductor is an example, and the diameter that the metal wire welding forms plain conductor 206 is about 60 μ m～75 μ m, highly is 50 μ m～60 μ m.The volume of two stanniferous plain conductors 206 then doubles.Three stanniferous plain conductor 206 stacks, volume then becomes three times.
In the present embodiment, the material of plain conductor 206 is for dissolve leypewter, high slicker solder lead alloy, sn-ag alloy or SAC alloy etc. altogether.
With reference to figure 8a, on plain conductor 206, be coated with scaling powder; Then, Semiconductor substrate 200 is put into reflow ovens, the plain conductor on the metal bed course 204 206 is incubated backflow, form salient point 216a.
In the present embodiment, reflux temperature is 220 ℃～350 ℃.
As another instance, shown in Fig. 7 b, on metal bed course 204, form the photoresist layer (not shown) with spin-coating method; Photoresist layer is made public, behind the developing process, on photoresist layer, forms opening, and the position of said opening is corresponding with the position of metal bed course 204.With the photoresist layer is mask, and with forming inculating crystal layer 205 on the metal bed course 204 of galvanoplastic in opening, said inculating crystal layer 205 constitutes for Cu, Ni or its, and the thickness range of said inculating crystal layer 205 is 1 μ m～8 μ m.Then, remove photoresist layer, adopt metal wire welding (wire bond) method on inculating crystal layer 205, to form plain conductor 206.
Except that above-mentioned situation; Before forming inculating crystal layer 205; Can also on metal bed course 204 and passivation layer 202, form metal screen layer, said metal screen layer is the combination of heat resistant metal layer and metal copper layer, and wherein the material of heat resistant metal layer is titanium, titanizing tungsten or chromium; The effect of said metal screen layer is to keep good adhesion with metal bed course 204, and effectively stops the phase counterdiffusion of follow-up convex point material with metal bed course 204.
And after forming inculating crystal layer 205, form before the salient point, using and forming thickness on the inculating crystal layer 205 of galvanoplastic in the photoresist opening is the ubm layer of 2 μ m～40 μ m; The material of said ubm layer is copper or copper and nickel combination.
With reference to figure 8b, on plain conductor 206, be coated with scaling powder; Then, Semiconductor substrate 200 is put into reflow ovens, the plain conductor on the metal bed course 204 206 is incubated backflow, form salient point 206a.
In the present embodiment, passivation layer 202 is planarized to the flush with metal bed course 204.Avoided because passivation layer 204 parts are positioned at the situation on the metal bed course 202; When following adopted metal wire welding procedure is stamped plain conductor on metal bed course 204 or inculating crystal layer 205; Passivation layer 202 can be by pressure break; The phenomenon that is short-circuited when effectively having prevented follow-up work has improved the electrical property of semiconductor device.
Salient point based on the foregoing description forms comprises: Semiconductor substrate 200; Be positioned at metal bed course 204 and passivation layer 202 on the Semiconductor substrate 200, said metal bed course 204 is embedded in the passivation layer 202, and metal bed course 204 and passivation layer 202 flush; Salient point 206a is positioned on the metal bed course 204.
Except that the foregoing description, the salient point of said formation also comprises: metal screen layer is positioned on metal bed course 204 and the passivation layer 202; Inculating crystal layer 205 is positioned on the metal screen layer of metal bed course 204 correspondence positions; Ubm layer is between inculating crystal layer 205 and salient point 206a.
Second embodiment
Fig. 9～Figure 13 is the second embodiment sketch map of bump making process of the present invention.As shown in Figure 9, Semiconductor substrate 300 is provided, said Semiconductor substrate 300 is for having the Semiconductor substrate of semiconductor device, in order to simplify diagrammatic sketch, here only with blank Semiconductor substrate signal.On Semiconductor substrate 300, form the first metal bed course 304, it is following specifically to form technology: at first adopt the physical vapor deposition (PVD) method on Semiconductor substrate 300, to form the first metal layer; Adopt existing photoetching and the graphical the first metal layer of etching technique then, form the first metal bed course 304.
Continuation then, forms first passivation layer 302 that covers the first metal bed course 304 with reference to figure 9 on Semiconductor substrate 300 with chemical vapour deposition technique.
Shown in figure 10, flat but change first passivation layer 302 with chemical mechanical milling method or mechanical milling method to exposing the first metal bed course 304, the surface that makes the first metal bed course 304 with grind after the flush of first passivation layer 302.
With reference to Figure 10, on the first metal bed course 304, form the second metal bed course 306 again, the method for the said formation second metal bed course 306 repeats no more at this with the first metal bed course 304.Then, on Semiconductor substrate 300, form second passivation layer 308 that covers the second metal bed course 306 with chemical vapour deposition technique.
Shown in figure 11; Flat but change second passivation layer 308 with chemical mechanical milling method or mechanical milling method to exposing the second metal bed course 306; Make the surface of the second metal bed course 306 and the flush of second passivation layer 308 after the grinding, the second metal bed course 306 is embedded between second passivation layer 308.
According to the method described above, can also on second passivation layer 308 and the second metal bed course 306, form the 3rd passivation layer and the 3rd metal bed course respectively, by that analogy, can make the metal bed course and the passivation layer of right quantity according to arts demand.Multiple layer metal pad and Tunization layer can increase the support and the integrally-built mechanical strength of salient point basic unit, promote the reliability of bump structure.
In the present embodiment, said passivation layer can be high molecular polymers such as silica, silicon nitride or benzocyclobutene (BCB), polytetrafluoroethylene, polyimides.The material of said metal bed course is that Al, Cu or their alloy constitute.
Shown in figure 12, adopt metal wire welding (wire bond) method on the second metal bed course 306, to form plain conductor 310.
In the present embodiment, the material of plain conductor 310 is for dissolve leypewter, high slicker solder lead alloy, sn-ag alloy or SAC alloy etc. altogether.
With reference to Figure 13, on plain conductor 310, be coated with scaling powder; Then, Semiconductor substrate 300 is put into reflow ovens, the plain conductor 310 on the second metal bed course 306 is incubated backflow, form salient point 310a.
In the present embodiment, reflux temperature is 220 ℃～350 ℃.
As an instance; Before forming plain conductor 310; Can also on the second metal bed course 306 and second passivation layer 308, form the metal screen layer (not shown); Said metal screen layer is the combination of heat resistant metal layer and metal copper layer, its role is to keep good adhesion with the second metal bed course 306, and effectively stops the phase counterdiffusion of follow-up convex point material with the second metal bed course 306.
Then, on metal screen layer, form with Cu, Ni or its inculating crystal layer that constitutes, said inculating crystal layer position is corresponding with second metal gasket 306; Then, in order to strengthen the adhesiveness of follow-up salient point 310a, on inculating crystal layer, form the ubm layer of copper or copper and nickel combination again.
Salient point based on the foregoing description forms comprises: Semiconductor substrate 300; Be positioned at the first metal bed course 304 and first passivation layer 302 on the Semiconductor substrate 300, the said first metal bed course 304 is embedded in first passivation layer 302, and the first metal bed course 304 and first passivation layer, 302 flush; Be positioned at the second metal bed course 306 on the first metal bed course 304, be positioned at second passivation layer 308 on first passivation layer 302, the said second metal bed course 306 is embedded in second passivation layer 308, and the second metal bed course 306 and second passivation layer, 308 flush; Salient point 310a is positioned on the second metal bed course 306.
Except that the foregoing description, the salient point of said formation also comprises: metal screen layer is positioned on the second metal bed course 306 and second passivation layer 308; Inculating crystal layer is positioned on the metal screen layer of the second metal bed course, 306 correspondence positions; Ubm layer is between inculating crystal layer and salient point 310a.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
1. the formation method of a salient point is characterized in that, comprising:
Semiconductor substrate is provided, is formed with metal bed course and passivation layer on the said Semiconductor substrate, said metal bed course is embedded in the passivation layer;
The planarization passivation layer is to exposing the metal bed course, and said passivation layer flushes with the metal gasket laminar surface;
Adopt the metal wire welding procedure on the metal bed course, to form plain conductor;
The reflow metal lead forms salient point.
2. the formation method of salient point according to claim 1, it is characterized in that: the technology of said planarization passivation layer is chemical mechanical milling method or mechanical milling method.
3. the formation method of salient point according to claim 1 is characterized in that: the material of said stanniferous plain conductor is for dissolve leypewter, high slicker solder lead alloy, sn-ag alloy or SAC alloy altogether.
4. the formation method of salient point according to claim 1, it is characterized in that: the temperature of backflow stanniferous plain conductor is 220 ℃～350 ℃.
5. the formation method of salient point according to claim 1 is characterized in that: also comprise before on said metal bed course, forming plain conductor: on the metal bed course, form inculating crystal layer.
6. the formation method of salient point according to claim 5, it is characterized in that: the material of said inculating crystal layer is a copper.
7. the formation method of salient point according to claim 1 is characterized in that: be formed with one deck passivation layer and one deck metal gasket layer at least at least on the said Semiconductor substrate successively, the flush of the metal bed course of said each layer passivation layer and equivalent layer.
8. a salient point that adopts the method formation of claim 1 comprises: Semiconductor substrate; Be positioned at metal bed course and passivation layer on the Semiconductor substrate; Be positioned at the salient point on the metal bed course; It is characterized in that said metal bed course flushes with passivation layer surface.
9. salient point according to claim 8 is characterized in that: the material of said stanniferous plain conductor is for dissolve leypewter, high slicker solder lead alloy, sn-ag alloy or SAC alloy altogether.
10. salient point according to claim 8 is characterized in that: also include inculating crystal layer between said metal bed course and the salient point.
11. salient point according to claim 10 is characterized in that: the material of said inculating crystal layer is a copper.
12. salient point according to claim 8 is characterized in that: comprise one deck passivation layer and one deck metal gasket layer at least at least, the flush of the metal bed course of said each layer passivation layer and equivalent layer.
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| CN2010105694330A CN102487023A (en) | 2010-12-01 | 2010-12-01 | Salient point and forming method thereof |
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| CN2010105694330A CN102487023A (en) | 2010-12-01 | 2010-12-01 | Salient point and forming method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0669052A (en) * | 1992-08-21 | 1994-03-11 | Sawafuji Electric Co Ltd | Ignition coil device for engine and its assembly jig |
| US20050082685A1 (en) * | 2003-10-20 | 2005-04-21 | Bojkov Christo P. | Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion |
| US7268421B1 (en) * | 2004-11-10 | 2007-09-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond |
| CN101075595A (en) * | 2006-05-15 | 2007-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor wafer welding material projected block structure and its production |
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2010
- 2010-12-01 CN CN2010105694330A patent/CN102487023A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0669052A (en) * | 1992-08-21 | 1994-03-11 | Sawafuji Electric Co Ltd | Ignition coil device for engine and its assembly jig |
| US20050082685A1 (en) * | 2003-10-20 | 2005-04-21 | Bojkov Christo P. | Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion |
| US7268421B1 (en) * | 2004-11-10 | 2007-09-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond |
| CN101075595A (en) * | 2006-05-15 | 2007-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor wafer welding material projected block structure and its production |
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Application publication date: 20120606 |