CN102485965A - Electroplating method of deep blind hole - Google Patents
Electroplating method of deep blind hole Download PDFInfo
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- CN102485965A CN102485965A CN2010105744109A CN201010574410A CN102485965A CN 102485965 A CN102485965 A CN 102485965A CN 2010105744109 A CN2010105744109 A CN 2010105744109A CN 201010574410 A CN201010574410 A CN 201010574410A CN 102485965 A CN102485965 A CN 102485965A
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Abstract
The invention discloses an electroplating method of a deep blind hole. The invention is suitable to be used in electroplating of metals such as gold, nickel, copper, and silver, and alloys thereof in the deep blind hole. The method comprises steps that: a semiconductor chip is washed; an etching barrier layer is grown on the semiconductor chip; photoresist is coated on the barrier layer; the semiconductor chip is exposed and developed; a corrosion zone is etched by photo-etching; areas on the barrier layer that are not covered by the photoresist are etched by using a dry method, a wet method, and the like; the photoresist is removed by using ethanol and acetone; a required depth is etched by using ICP, and superfluous barrier layer is removed; an initial plating coat is evaporated or sputtered; the gas and solution intensities required by spray plating are adjusted according to the depth and the width of the blind hole. The method assists in solving a deep blind hole electroplating problem. With the method, the requirements of back metal electroplating of integrated circuits, and especially the requirements of large-power integrated circuit heat dissipation, are satisfied.
Description
Technical field
The present invention relates to unicircuit electroplating technology field, relate in particular to and a kind of dark blind hole is carried out electric plating method.
Background technology
Along with development of integrated circuits, the size of metal interconnected system sharply reduces in the unicircuit, and the number of plies of metal line increases gradually, and that individual devices becomes is more and more littler; This has just caused the device interconnection line more and more thinner, and under the condition that big electric current passes through, the heat radiation of device is exactly the subject matter that needs solution; If the heat that generates can not in time solve, in a short time, along with the rising of temperature; The resistivity of metal connecting line will continue to increase, thereby can improve the signal delay on the metal connecting line significantly, to such an extent as to be difficult to the speed ability that obtains expecting; If the long term device device work just might blow, thereby, entire circuit was lost efficacy.
Dorsal pore can effectively solve the problem of heat radiation; According to the Fourier in thermal conduction study experiment law, medium is directly proportional with the directional derivative
of medium temperature along curved surface dS normal direction along the heat dQ that normal direction n flows through an infinitesimal area dS in infinitely small period dt:
K (x wherein; Y; Z) be called medium at point (x; Y; Z) heat-conduction coefficient of locating, it get on the occasion of, can find out that from following formula the speed of heat dissipation capacity and heat extraction coefficient have very big relation; And metal is the good conductor of heat, and heat extraction coefficient is more much bigger than semiconductor material, thereby, be etched into dorsal pore to semiconductor material; The part lead-in wire is drawn through dorsal pore simultaneously, like this, and the dorsal pore filler metalization; Both can dispel the heat, can serve as lead-in wire again, just can improve the safety of device greatly.
Dorsal pore metallization can be used evaporation, sputter and plating, but evaporation, the needed cost of sputter are higher, and simultaneously, evaporation, that sputter surpasses certain thickness stress is bigger, causes the distortion of substrate easily, thereby influences the performance of device; It is lower to electroplate required cost, is easier to realize, on galvanized realization link; And the plating of dark blind hole is a difficult point, and its major cause is that the depth-to-width ratio of blind hole surpasses at 2: 1 o'clock, and traditional negative electrode such as moves at method; The exchange of solution in blind hole will be restricted, and the exchange difficulty of solution will cause metals ion to be difficult for moving in the blind hole like this; Directly the result is that blind hole bottom and wall just seldom or can metal refinings, and the outside surface of blind hole will deposit a large amount of metals, and such result is exactly that the blind hole inwall does not still obtain metallization; Under the situation of big electric current, still do not have the effect of heat radiation, device will be burnt out.
Summary of the invention
The technical problem that (one) will solve
In view of this, main purpose of the present invention is to provide a kind of dark blind hole is carried out electric plating method, to solve the galvanized problem of dark blind hole, satisfies the plating of integrated galvanized back of the body gold, particularly at the needs of the heat radiation of powerful unicircuit.
(2) technical scheme
For achieving the above object, the invention provides and a kind of dark blind hole is carried out electric plating method, this method comprises:
Step 1: clean semiconducter substrate;
Step 2: growth one deck medium on semiconducter substrate, as etching barrier layer;
Step 3: on etching barrier layer, be coated with the last layer photoresist material, make public then, develop, make the zone that needs etching by lithography;
Step 4: etch the medium layer that is not covered by photoresist material;
Step 5: adopt acetone and ethanol to remove photoresist material;
Step 6: the blind hole that etches required thickness with ICP;
Step 7: erode remaining blocking layer;
Step 8: evaporation or sputter plating seed layer on semiconducter substrate are as the criterion to cover whole semiconducter substrate;
Step 9:,,, electroplate out the layer of metal layer at the enterprising electroplating of plating seed layer according to area and the galvanized electric current of THICKNESS CALCULATION and the time of semiconducter substrate according to the required gas of depth adjustment spraying plating and the needed intensity of solution of blind hole.
In the such scheme, etching barrier layer described in the step 2 adopts evaporation, sputter or chemical vapor deposition (CVD) method to be produced on the semiconducter substrate.
In the such scheme, etching described in the step 4 adopts dry method or wet method mode to carry out.
In the such scheme, described in the step 8 on semiconducter substrate the evaporation or the plating seed layer of sputter, its thickness is 300 dust to 8000 dusts.
In the such scheme, electroplate the mode that adopts spouting of liquid to combine described in the step 9 with gas stirring.
In the such scheme, the blind hole depth of said semiconductor substrate materials is≤120um that the blind hole aperture is>=40um.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
1), provided by the inventionly this dark blind hole is carried out electric plating method, solved the galvanized problem of dark blind hole, satisfied the plating of integrated galvanized back of the body gold, particularly at the needs of the heat radiation of powerful unicircuit.
2), provided by the invention dark blind hole is carried out electric plating method, be on the basis of common electrical depositing process, to grow up, technical maturity has promotional value.
3), provided by the invention dark blind hole is carried out electric plating method, can regulate the intensity that stirs according to blind hole depth, thereby reach the galvanized purpose of dark blind hole.
4), provided by the invention dark blind hole is carried out electric plating method, be the improvement on traditional method, be prone to realize, mainly be the deposition of accelerating metal in the blind hole through the frequency of accelerating solution exchange in the dark blind hole.
5), provided by the invention dark blind hole is carried out electric plating method, be applicable to the electro-plating method of metals such as electrogilding, nickel, copper, silver and alloy thereof, and be applicable to that substrate material is Si, SiC, Al
2O
3, simple substance and compound semiconductor materials such as GaN, GaAs.
Description of drawings
Fig. 1 to Figure 10 makes dark blind hole electroplating technique schema according to the embodiment of the invention;
Figure 11 is a spraying plating synoptic diagram provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
Provided by the inventionly this dark blind hole is carried out electric plating method, stir gas through control and control the exchange of solution with the intensity of sprayed solution, and then control the speed of metal deposition, this method mainly comprises:
Step 1: clean semiconducter substrate; The blind hole depth of this semiconductor substrate materials is≤120um that the blind hole aperture is>=40um.
Step 2: adopt evaporation, sputter or chemical vapor deposition (CVD) method one deck medium of on semiconducter substrate, growing, as etching barrier layer.
Step 3: on etching barrier layer, be coated with the last layer photoresist material, make public then, develop, make the zone that needs etching by lithography.
Step 4: adopt dry method or wet method mode to etch the medium layer that is not covered by photoresist material.
Step 5: adopt acetone and ethanol to remove photoresist material.
Step 6: the blind hole that etches required thickness with ICP.
Step 7: erode remaining blocking layer.
Step 8: evaporation or sputter plating seed layer on semiconducter substrate, thickness is 300 dust to 8000 dusts, is as the criterion to cover whole semiconducter substrate.
Step 9: according to the required gas of depth adjustment spraying plating and the needed intensity of solution of blind hole; According to area and the galvanized electric current of THICKNESS CALCULATION and the time of semiconducter substrate; The mode that on plating seed layer, adopts spouting of liquid to combine with gas stirring is electroplated, and electroplates out the layer of metal layer.
Fig. 1 to Figure 10 makes dark blind hole electroplating technique schema according to the embodiment of the invention, mainly comprises:
1, the cleaning of semi-conductor chip: clean up semi-conductor chip with acetone, ethanol, water.
2, method growth one deck media such as evaporation on semi-conductor chip, sputter, CVD are as etching barrier layer; As shown in Figure 2, the kind of medium and thickness depend primarily on the substrate material and the gas of institute's etching.
3, photoetching
On the growth medium chip, be coated with last layer glue, the general thin about thickness of this layer glue is 1～2 μ m, and is as shown in Figure 3, after exposure, the development, makes the zone that needs etching by lithography, as shown in Figure 4.
4, etching
Through the blocking layer that dry method, wet etching are not covered by photoresist material, the method for etching is by the decision of blocking layer medium, and is as shown in Figure 5.
5, ICP etching
Remove photoresist material, as shown in Figure 6, with the needed degree of depth of ICP etching, as shown in Figure 7.
6, coating is opened in sputter
Remove remaining blocking layer; As shown in Figure 8; Evaporation/sputter plating seed layer on substrate; Be as the criterion to cover entire substrate, generally need the Seed Layer of 300-8000
, as shown in Figure 9.
7. electroplate
According to the degree of depth of blind hole, regulate required gas of spraying plating and the needed intensity of solution, according to area of chip and thickness, calculate galvanized electric current and time, electroplate; Electroplate out the layer of metal layer; Accomplish the plating of dark blind hole, shown in figure 10.
Figure 11 is a spraying plating synoptic diagram provided by the invention, mainly comprises: 1, sparge pipe; 2, pumping pipe; 3, gas ejector pipe; 4, positive plate; 5, plating piece; Wherein 1, sparge pipe and 2, pumping pipe connect through recycle pump; The intensity of the power regulation hydrojet through recycle pump, the size that gas ejector pipe is regulated air-flow through under meter is just controlled the degree of depth of electroplating liquid entering blind hole through the adjusting of recycle pump and under meter; Realize the exchange of liquid in the blind hole, realize the plating of dark blind hole.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. one kind is carried out electric plating method to dark blind hole, it is characterized in that this method comprises:
Step 1: clean semiconducter substrate;
Step 2: growth one deck medium on semiconducter substrate, as etching barrier layer;
Step 3: on etching barrier layer, be coated with the last layer photoresist material, make public then, develop, make the zone that needs etching by lithography;
Step 4: etch the medium layer that is not covered by photoresist material;
Step 5: adopt acetone and ethanol to remove photoresist material;
Step 6: the blind hole that etches required thickness with ICP;
Step 7: erode remaining blocking layer;
Step 8: evaporation or sputter plating seed layer on semiconducter substrate are as the criterion to cover whole semiconducter substrate;
Step 9:,,, electroplate out the layer of metal layer at the enterprising electroplating of plating seed layer according to area and the galvanized electric current of THICKNESS CALCULATION and the time of semiconducter substrate according to the required gas of depth adjustment spraying plating and the needed intensity of solution of blind hole.
2. according to dark blind hole being carried out electric plating method, it is characterized in that etching barrier layer described in the step 2 adopts evaporation, sputter or chemical gaseous phase depositing process to be produced on the semiconducter substrate according to claim 1 is described.
3. according to dark blind hole being carried out electric plating method, it is characterized in that etching described in the step 4 adopts dry method or wet method mode to carry out according to claim 1 is described.
4. according to dark blind hole being carried out electric plating method, it is characterized in that according to claim 1 is described, described in the step 8 on semiconducter substrate the evaporation or the plating seed layer of sputter, its thickness is 300 dust to 8000 dusts.
5. according to dark blind hole being carried out electric plating method, it is characterized in that, electroplate the mode that adopts spouting of liquid to combine described in the step 9 with gas stirring according to claim 1 is described.
6. according to dark blind hole being carried out electric plating method, it is characterized in that the blind hole depth of said semiconductor substrate materials is≤120um that the blind hole aperture is>=40um according to claim 1 is described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105744109A CN102485965A (en) | 2010-12-06 | 2010-12-06 | Electroplating method of deep blind hole |
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|---|---|---|---|
| CN2010105744109A CN102485965A (en) | 2010-12-06 | 2010-12-06 | Electroplating method of deep blind hole |
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| CN102485965A true CN102485965A (en) | 2012-06-06 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261569A (en) * | 2015-09-02 | 2016-01-20 | 业成光电（深圳）有限公司 | Manufacturing method for blind hole of insulating substrate for electronic apparatus |
| CN108660489A (en) * | 2018-06-07 | 2018-10-16 | 常德力元新材料有限责任公司 | A kind of preparation method in aperture and the agonic three-dimensional porous metal material of physical property |
| CN111945202A (en) * | 2020-07-21 | 2020-11-17 | 中国电子科技集团公司第十三研究所 | Blind hole electroplating method for ceramic leadless shell |
| CN113278971A (en) * | 2021-04-29 | 2021-08-20 | 中国电子科技集团公司第二十九研究所 | Curved surface printed board preparation method based on jet printing |
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| US4875982A (en) * | 1987-02-06 | 1989-10-24 | Velie Circuits, Inc. | Plating high aspect ratio holes in circuit boards |
| JP2001274161A (en) * | 2000-03-24 | 2001-10-05 | Kobe Steel Ltd | Method of forming semiconductor wiring film |
| CN1609281A (en) * | 2002-11-28 | 2005-04-27 | 希普雷公司 | Method for electrolytic copper plating |
| CN101022078A (en) * | 2007-03-23 | 2007-08-22 | 中国科学院光电技术研究所 | Unequal depth micro nano slot structure forming method |
| CN101345194A (en) * | 2008-05-07 | 2009-01-14 | 北大方正集团有限公司 | Silicon groove forming method and device |
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2010
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Patent Citations (5)
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| US4875982A (en) * | 1987-02-06 | 1989-10-24 | Velie Circuits, Inc. | Plating high aspect ratio holes in circuit boards |
| JP2001274161A (en) * | 2000-03-24 | 2001-10-05 | Kobe Steel Ltd | Method of forming semiconductor wiring film |
| CN1609281A (en) * | 2002-11-28 | 2005-04-27 | 希普雷公司 | Method for electrolytic copper plating |
| CN101022078A (en) * | 2007-03-23 | 2007-08-22 | 中国科学院光电技术研究所 | Unequal depth micro nano slot structure forming method |
| CN101345194A (en) * | 2008-05-07 | 2009-01-14 | 北大方正集团有限公司 | Silicon groove forming method and device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261569A (en) * | 2015-09-02 | 2016-01-20 | 业成光电（深圳）有限公司 | Manufacturing method for blind hole of insulating substrate for electronic apparatus |
| CN108660489A (en) * | 2018-06-07 | 2018-10-16 | 常德力元新材料有限责任公司 | A kind of preparation method in aperture and the agonic three-dimensional porous metal material of physical property |
| CN108660489B (en) * | 2018-06-07 | 2020-04-24 | 常德力元新材料有限责任公司 | Preparation method of three-dimensional porous metal material with non-deviation aperture and physical property |
| CN111945202A (en) * | 2020-07-21 | 2020-11-17 | 中国电子科技集团公司第十三研究所 | Blind hole electroplating method for ceramic leadless shell |
| CN111945202B (en) * | 2020-07-21 | 2021-10-15 | 中国电子科技集团公司第十三研究所 | Blind hole electroplating method for ceramic leadless shell |
| CN113278971A (en) * | 2021-04-29 | 2021-08-20 | 中国电子科技集团公司第二十九研究所 | Curved surface printed board preparation method based on jet printing |
| CN113278971B (en) * | 2021-04-29 | 2022-02-01 | 中国电子科技集团公司第二十九研究所 | Curved surface printed board preparation method based on jet printing |
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Application publication date: 20120606 |