CN101345194A - Silicon groove forming method and device - Google Patents

Silicon groove forming method and device Download PDF

Info

Publication number
CN101345194A
CN101345194A CNA2008101060254A CN200810106025A CN101345194A CN 101345194 A CN101345194 A CN 101345194A CN A2008101060254 A CNA2008101060254 A CN A2008101060254A CN 200810106025 A CN200810106025 A CN 200810106025A CN 101345194 A CN101345194 A CN 101345194A
Authority
CN
China
Prior art keywords
silicon
hard mask
etching
mask layer
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2008101060254A
Other languages
Chinese (zh)
Other versions
CN100595895C (en
Inventor
王托猛
蔡新春
谢海华
杨勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Founder Microelectronics Co Ltd
Original Assignee
Peking University Founder Group Co Ltd
Shenzhen Founder Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University Founder Group Co Ltd, Shenzhen Founder Microelectronics Co Ltd filed Critical Peking University Founder Group Co Ltd
Priority to CN200810106025A priority Critical patent/CN100595895C/en
Publication of CN101345194A publication Critical patent/CN101345194A/en
Application granted granted Critical
Publication of CN100595895C publication Critical patent/CN100595895C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

The invention discloses a silicon trough forming method and a device, belonging to the field of semiconductor integration circuit chip process technique. The method of the invention comprises the steps as follows: a hard mask layer grows on the silicon substrate; the surface of the hard mask layer is coated by a photoresist layer; a photoresist pattern is gained by a lithography process; the hard mask layer is etched; the photoresist pattern is copied to the hard mask layer; HBr/CF4/He-O2 mixed gas is introduced into silicon substrate etching equipment so as to etch the silicon substrate and form a silicon trough. The device of the invention comprises a hard mask growth module, a photoresist layer coating module, a hard mask etching module and a silicon substrate etching module. The method and the device of the invention are mainly applied to the etching of the silicon substrate, can improve safety and reduce consumption of HBr, reduce the maintenance cost of the equipment and save the comprehensive consumption cost of the mixed gas.

Description

Silicon groove forming method and device
Technical field
The invention belongs to semiconductor integrated circuit chip technology field, be specially the method for silicon substrate being carried out etching.
Background technology
Semiconductor power device is widely used in fields such as consumer electronics, computer and peripheral hardware, network service, automotive electronics, LED display, can be used as voltage control device, it has following characteristics: input impedance height, driving power are low, drain current negative temperature coefficient, no second breakdown, working range is wide and Heat stability is good.
Mos field effect transistor (metallic oxide semiconductor fieldeffecttransistor, Trench MOSFET) is the high cellular density of novel vertical structure device in the semiconductor power device, has the characteristics of low on-resistance, low grid leak charge density, low actuating switch loss and high switching speed.Wherein the silicon substrate etching technics has obtained broad research as Trench MOSFET technology key point.Industry is mainly selected HB for use at present r/ CL 2/ He-O 2Perhaps HB r/ NF 3/ He-O 2Mist adopts intensified response ion device in magnetic field to carry out the silicon substrate etching.
Mainly there is the problem of following several aspects in the traditional silicon groove forming method:
No matter one adopts HB r/ CL 2/ He-O 2Mist still adopts HB r/ NF 3/ He-O 2Mist carries out etching, HB rThe consumption of gas is higher.
Two, in the etching reaction process, use the HB of big flow rBe easy to generate and generate a large amount of S iBr 4, S iBr xO yAccessory substance; Too much accessory substance S iBr xO yBe deposited in the process cavity, not only influenced the cleanliness factor of cavity, and increased the loss of equipment and spare part, and the replacement cost that has increased the plant maintenance spare part.
Three, CL 2, NF 3Have toxicity, use above-mentioned gas to increase the insecurity of silicon groove etching.
No matter four, adopt HB r/ CL 2/ He-O 2Mist still adopts HB r/ NF 3/ He-O 2Mist carries out etching, and the integrated cost that consumes mist is higher.
Summary of the invention
Technical problem to be solved by this invention provides a kind of silicon groove forming method that can improve the etching fail safe.
For addressing the above problem, the invention provides a kind of silicon groove forming method, adopt following technical scheme:
The hard mask layer of on silicon substrate, growing;
At hard mask layer surface-coated photoresist, obtain the photoresist figure through photoetching process;
The etching hard mask layer duplicates the photoresist figure to hard mask layer;
In the silicon substrate etching apparatus, feed HB r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, forms the silicon groove.
Described silicon substrate is a monocrystalline substrate; Described hard mask is a silicon dioxide.
The vertical angle of described silicon groove is greater than 87 degree.
Wherein, describedly in the silicon substrate etching apparatus, feed HB r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, and the step that forms the silicon groove comprises: feed HB in the silicon substrate etching apparatus r/ CF 4/ He-O 2Mist carries out anisotropic etching to silicon substrate, forms the silicon groove.
Further, described etching hard mask layer duplicates the photoresist figure after the step of hard mask layer, also comprises: the step of removing photoresist layer.
Wherein, described silicon substrate etching apparatus is a magnetic field intensified response ion device.
When carrying out the silicon substrate etching, chamber pressure is 45~60mT; Power is 450~550W; HB rFlow is 40~45SCCM; CF 4Flow is 5~7SCCM; He-O 2Flow is 5~7SCCM.
Further, describedly in the silicon substrate etching apparatus, feed HB r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, forms after the step of silicon groove, also comprises:
Utilize the hydrofluoric acid solution wet method to remove remaining hard mask layer;
The silicon trench bottom is carried out the fillet etching.
Silicon groove forming method of the present invention is by feeding HB in the silicon substrate etching apparatus r/ CF 4/ He-O 2Mist replaces HB r/ NF 3/ He-O 2Mist or HB r/ CL 2/ He-O 2Mist carries out etching to silicon substrate, can improve the fail safe of etching.
Another object of the present invention is to provide a kind of silicon flute profile apparatus for converting that can improve the etching fail safe.
For achieving the above object, the present invention adopts following technical scheme:
A kind of silicon flute profile apparatus for converting comprises:
The hard mask layer pop-in upgrades is used for the hard mask layer of growing on silicon substrate;
The photoresist layer coat module is used at hard mask layer surface-coated photoresist layer, obtains the photoresist figure through photoetching process;
The hard mask layer etch module is used for the etching hard mask layer, duplicates the photoresist figure to hard mask layer;
The silicon substrate etch module is used for feeding HB to the silicon substrate etching apparatus r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, forms the silicon groove.
Described silicon flute profile apparatus for converting also comprises:
Photoresist layer is removed module, is used to remove photoresist layer;
Hard mask layer is removed module, is used to utilize the hydrofluoric acid solution wet method to remove remaining hard mask layer.
Further, described silicon flute profile apparatus for converting also comprises:
The fillet etch module is used for the silicon trench bottom is carried out the fillet etching.
Silicon flute profile apparatus for converting of the present invention is by feeding HB in the silicon substrate etching apparatus r/ CF 4/ He-O 2Mist replaces HB r/ NF 3/ He-O 2Mist or HB r/ CL 2/ He-O 2Mist carries out etching to silicon substrate, can improve the fail safe of etching.
Description of drawings
Fig. 1 is the schematic flow sheet of silicon groove forming method in the specific embodiment of the invention;
Fig. 2 is the silicon chip structural representation behind the photoresist layer process photoetching technique exposure imaging in the specific embodiment of the invention;
Fig. 3 is for carrying out silicon chip structural representation after the etching to hard mask layer in the specific embodiment of the invention;
Fig. 4 is the silicon chip structural representation behind the removal photoresist in the specific embodiment of the invention;
Fig. 5 is for carrying out the silicon chip structural representation after the silicon substrate etching in the specific embodiment of the invention;
Fig. 6 is for utilizing hydrofluoric acid HF solution wet method in the specific embodiment of the invention and remove remaining hard mask layer and to the silicon chip structural representation after the silicon trench bottom fillet etching;
Fig. 7 is the structural representation of silicon flute profile apparatus for converting in the specific embodiment of the invention.
Embodiment
The present invention aims to provide a kind of silicon groove forming method, by using HB r/ CF 4/ He-O 2Mist replaces HB r/ NF 3/ He-O 2Mist and HB r/ CL 2/ He-O 2Mist carries out etching to monocrystalline substrate, has improved the fail safe of etching; And, form the silicon groove of same size, use HB r/ CF 4/ He-O 2Mist can reduce HB rThe consumption of gas, thus the replacement cost of reduction plant maintenance spare part further, can reduce the wastage in bulk or weight cost of mist; And, after etching,, can reduce the discharge of wedge angle by the silicon groove is carried out the fillet etching.
Describe below in conjunction with accompanying drawing and specific embodiment.
Fig. 1 is the schematic flow sheet of silicon groove forming method in the specific embodiment of the invention.As shown in Figure 1, silicon groove forming method of the present invention, concrete steps are as follows:
Step 101: the hard mask layer of on silicon substrate, growing.
The present invention grows the hard mask layer of specific thicknesses by high-temperature technology in surface of silicon, forms the silicon chip with thin hard mask layer.Wherein, described silicon substrate is meant monocrystalline substrate; Described hard mask layer is silicon dioxide (S iO 2); Specifically, can be the S of 0.25~0.5 micron thickness iO 2Layer also can be 500 S iO 2Deposition 3000 on the layer
Figure A20081010602500072
The tetraethoxysilane of low pressure (LPTEOS) layer.If adopt 500
Figure A20081010602500073
S iO 2Deposition 3000 on the layer
Figure A20081010602500074
The LPTEOS layer of low pressure is as hard mask layer, and described LPTEOS layer can obtain by low-pressure chemical vapor deposition method in semiconductor technology.
Step 102:, obtain the photoresist figure through photoetching process at hard mask layer surface-coated photoresist layer.
The present invention is at first revolved on the hard mask layer surface of silicon chip and is covered one deck photoresist, utilizes photoetching technique exposure then, and the silicon chip that will scribble photoresist layer is put in the developer solution, and the photoetching glue pattern develops; Its objective is for etching hard mask layer S optionally iO 2Fig. 2 is the silicon chip structural representation behind the photoresist layer process photoetching technique exposure imaging in the specific embodiment of the invention.
Step 103: the etching hard mask layer, duplicate the photoresist figure to hard mask layer.
The present invention is with hard S iO 2As mask layer, and directly do not use photoresist layer as mask layer, this is because when carrying out the silicon substrate etching, S iO 2Can control the side wall passivation protective layer better and deposit and volatilize, obtain perpendicularity silicon groove preferably.The present invention can carry out the plasma dry etching to hard mask layer by the common etching apparatus of Lam Rainbow 4520 models.Fig. 3 is for carrying out silicon chip structural representation after the etching to hard mask layer in the specific embodiment of the invention.After hard mask layer carried out etching, the window perpendicularity of described hard mask layer was generally greater than 87 degree, the size of window when carrying out the silicon substrate etching, can be used for controlling the silicon groove the technology live width (Critical Dimension, CD).
After the hard mask layer etching was finished, the present invention adopted dry method O 2Plasma is got rid of remaining photoresist layer.Fig. 4 is a structural representation of removing silicon chip behind the photoresist layer in the specific embodiment of the invention.
Step 104: in the silicon substrate etching apparatus, feed HB r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, forms the silicon groove.
After the hard mask layer etching, hard mask layer window exposed portions serve silicon substrate, the monocrystalline silicon of this part is easy to be oxidized to fine and close sull owing to be exposed in the air.Therefore, before employing magnetic field intensified response ion device is carried out etching to monocrystalline substrate, at first to penetrate etching to described sull.Specifically, the etching condition that penetrates etching is as follows: pressure is 50Mt, and power is 400W, and magnetic field is 30 Gausses, CF 4Gas flow is 35SCCM, and the time is 15 seconds.
Then, at hard mask layer S iO 2Protection under, in silicon substrate etching apparatus cavity, feed HB r/ CF 4/ He-O 2Mist is close to the etching of anisotropy vertical direction to monocrystalline substrate.Concrete etching condition is as follows: chamber pressure is 45~60mT; Power is 450~550W; HB rFlow is 40~45SCCM; CF 4Flow is 5~7SCCM; He-O 2Flow is 5~7SCCM.After etching was finished, the vertical angle of silicon groove was greater than 87 degree.
The etching condition of most preferred embodiment of the present invention is as follows: pressure 60Mt, power 500W, magnetic field 30 Gausses, HB rFlow 40SCCM, CF 4Flow 7SCCM, He-O 2Flow 5SCCM, 150 seconds time.Certainly, each parameter can have 10% float; Wherein, the time can be looked the silicon groove depth and be increased and decreased, and the CD of silicon groove is relevant with the CD of litho pattern, also we can say the CD and the hard mask layer S of silicon groove iO 2Window width relevant.The silicon groove that forms under the etching condition of above-mentioned most preferred embodiment, the degree of depth are 1.0 ± 0.1um, and the CD of silicon groove is 0.4 ± 0.4um.Fig. 5 is for carrying out the silicon chip structural representation after the silicon substrate etching in the specific embodiment of the invention.
Silicon substrate etching apparatus of the present invention is a magnetic field intensified response ion device, certain the present invention carries out etching to silicon substrate and is not limited to this equipment, also can adopt high density plasma etch equipment, as TCP plasma dry etching apparatus or DPS plasma dry etching apparatus, required etching condition is done suitable adjustment and is got final product.
With employing HB r/ NF 3/ He-O 2Mist comparatively speaking, silicon groove forming method of the present invention has the following advantages:
1), adopts HB r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, has ensured the fail safe of etching.
2), when forming the silicon groove of same size, the present invention adopts HB r/ CF 4/ He-O 2Mist has reduced HB rThe consumption of gas.
For example, be 1.0 ± 0.1um when forming the degree of depth, when CD is the silicon groove of 0.4 ± 0.4um size, adopting HB r/ NF 3/ He-O 2Mist and HB r/ CF 4/ He-O 2Under two kinds of situations of mist, HB rThe consumption ratio of gas is 17: 8, and is as shown in table 1; Therefore adopt CF 4Gas replaces NF 3Gas can be saved HB rThe consumption of gas.
Table 1
Mist Etching condition
HB r/NF 3/He-O 2 Penetrate etching: 50mT/400W-0G/35CF 4/ 15S silicon groove etching: 45mT/500W-30G/85HB r/10NF 3/5He-O 2 /150S
HB r/CF 4/He-O 2 Penetrate etching: 50mT/400W-0G/35CF 4/ 15S silicon groove etching: 60mT/500W-30G/40HB r/7CF 4/5He-O 2 /150S
3), reduced the etching cost of silicon groove.
When carrying out the silicon substrate etching, gas usage that is adopted and pairing price are as shown in table 2.
Table 2
HB r NF 3 CF 4
Unit 44L 47L 47L
Price (unit) 64000 38000 15000
Consolidated statement 1, table 2 form the silicon groove of same size as can be seen, select HB for use r/ CF 4/ He-O 2The integrated cost that mist consumed is lower.
4), reduced the parts replacement cost.
When carrying out the silicon substrate etching, use the HB of big flow rBe easy to generate the more S that is difficult to volatilize iBr xO y, be deposited on easy dirty etching apparatus cavity in the wall of chamber; And use the HB of low discharge instead r, obviously can reduce the periodicmaintenance number of times of equipment, improve the useful life of equipment and spare part, reduce cost of equipment maintenance.
In like manner, adopt HB r/ CF 4/ He-O 2Mist replaces HB r/ CL 2/ He-O 2The situation of mist and above-mentioned situation are similar, though the consumption ratio of each composition is slightly different, can reach above-mentioned similar effects equally, do not do at this and give unnecessary details.
In order to remove remaining hard mask layer S iO 2, the present invention removes by adopting hydrofluoric acid HF solution wet method; Be hydrofluoric acid HF solution and S iO 2Reaction generates water miscible product H 2SiF 6, concrete chemical equation is as follows: S iO 2+ HF → H 2SiF 6+ H 2O.Fig. 6 is for utilizing hydrofluoric acid HF solution wet method in the specific embodiment of the invention and remove remaining hard mask layer and to the structural representation of silicon chip after the silicon trench bottom fillet etching.
In order to reduce the discharge of wedge angle, the present invention can carry out fillet Rounding etching to the silicon trench bottom, makes bottom land level and smooth as far as possible.Wherein, carrying out the Rounding etching can use isotropism to do etching apparatus AE 2001 equipment at quarter; Carry out after the Rounding etching, the degree of depth of silicon groove becomes 1.1 ± 0.1um, and the CD of silicon groove becomes 0.6 ± 0.6um; Can satisfy the requirement on devices of product through the silicon flute profile looks after the Rounding etching.
In sum, silicon groove forming method of the present invention is by using HB r/ CF 4/ He-O 2Mist replaces HB r/ CL 2/ He-O 2Or HB r/ NF 3/ He-O 2Mist carries out etching to silicon substrate, not only can improve the fail safe of etching, reduces HB rThe consumption of gas, and can reduce the etching cost of silicon groove and the cost of plant maintenance.
On the other hand, the present invention also provides a kind of silicon flute profile apparatus for converting, wherein, by the silicon substrate etch module silicon substrate is carried out etching, can reduce HB rThe consumption of gas, thereby the replacement cost of reduction plant maintenance spare part; And the fail safe that can improve etching, and the wastage in bulk or weight cost of reduction mist; Further, carry out the fillet etching, can reduce the discharge of wedge angle by the fillet etch module.
Below in conjunction with accompanying drawing and specific embodiment described silicon flute profile apparatus for converting is described.
Fig. 7 is the structural representation of silicon flute profile apparatus for converting in the specific embodiment of the invention.As shown in Figure 7, described silicon flute profile apparatus for converting comprises: hard mask layer pop-in upgrades 701, photoresist layer coat module 702, hard mask layer etch module 703 and silicon substrate etch module 704.
Wherein, the hard mask layer pop-in upgrades is used for the hard mask layer of growing on silicon substrate; The photoresist layer coat module is used at hard mask layer surface-coated photoresist layer, obtains the photoresist figure through photoetching process; The hard mask layer etch module is used for the etching hard mask layer, duplicates the photoresist figure to hard mask layer; The silicon substrate etch module is used for feeding HB to the silicon substrate etching apparatus r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, forms the silicon groove.
When described silicon flute profile apparatus for converting carries out work, in the silicon substrate etching apparatus, feed HB r/ CF 4/ He-O 2Mist, the etch silicon substrate, thus form the silicon groove; When forming the silicon groove of same size, adopt HB r/ NF 3/ He-O 2Mist and HB r/ CF 4/ He-O 2Under two kinds of situations of mist, the HB that consumes rThe ratio of gas is 17: 8, consumes NF 3Gas and CF 4The ratio of gas is 10: 7, consumes He-O 2The ratio of gas is identical.Can draw thus, adopt HB r/ CF 4/ He-O 2Mist carries out the silicon substrate etching, has reduced HB rThe consumption of gas, thus accessory substance S reduced iBr xO yGrowing amount, reduce cost of equipment maintenance; And because the NF of same volume 3The gas cost is than CF 4The gas height has also reduced the wastage in bulk or weight cost of mist.
In like manner, HB r/ CF 4/ He-O 2Mist is with respect to HB r/ CL 2/ He-O 2Mist carries out the silicon substrate etching, also can reach similar effects, does not do at this and gives unnecessary details.
Described silicon flute profile apparatus for converting comprises that also photoresist layer is removed module and hard mask layer is removed module.(not shown)
Wherein, described photoresist layer removal module is used to remove photoresist layer; Described hard mask layer is removed module and is used to utilize the hydrofluoric acid solution wet method to remove remaining hard mask layer.
Device of the present invention is removed module by photoresist layer and is removed remaining photoresist layer after carrying out the hard mask layer etching by the hard mask layer etch module; And, carry out the silicon substrate etching in the silicon substrate etch module, form after the silicon groove, remove module by hard mask layer and remove remaining hard mask layer.But the scope of protection of the invention is not limited thereto, and can also carry out the silicon substrate etching in the silicon substrate etch module, forms the silicon groove and removes remaining photoresist layer and hard mask layer by photoresist layer removal module and hard mask layer removal module respectively afterwards.
Further, in order to reduce the wedge angle discharge, described silicon flute profile apparatus for converting also comprises the fillet etch module.(not shown)
Described fillet etch module is used for the silicon trench bottom is carried out the fillet etching.
In sum, silicon flute profile apparatus for converting of the present invention is by using HB r/ CF 4/ He-O 2Mist replaces HB r/ CL 2/ He-O 2Or HB r/ NF 3/ He-O 2Mist, the fail safe that not only can improve etching reduces HB rThe consumption of gas, and can reduce the etching cost of silicon groove and the cost of plant maintenance.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claim was defined.

Claims (11)

1, a kind of silicon groove forming method is characterized in that, comprising:
The hard mask layer of on silicon substrate, growing;
At hard mask layer surface-coated photoresist, obtain the photoresist figure through photoetching process;
The etching hard mask layer duplicates the photoresist figure to hard mask layer;
In the silicon substrate etching apparatus, feed HB r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, forms the silicon groove.
2, silicon groove forming method according to claim 1 is characterized in that,
Described silicon substrate is a monocrystalline substrate;
Described hard mask is a silicon dioxide.
3, silicon groove forming method according to claim 2 is characterized in that, the vertical angle of described silicon groove is greater than 87 degree.
4, silicon groove forming method according to claim 3 is characterized in that, describedly feeds HB in the silicon substrate etching apparatus r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, and the step that forms the silicon groove comprises: feed HB in the silicon substrate etching apparatus r/ CF 4/ He-O 2Mist carries out anisotropic etching to silicon substrate, forms the silicon groove.
5, silicon groove forming method according to claim 4 is characterized in that, described etching hard mask layer duplicates the photoresist figure after the step of hard mask layer, also comprises: the step of removing photoresist layer.
6, silicon groove forming method according to claim 5 is characterized in that, described silicon substrate etching apparatus is a magnetic field intensified response ion device.
7, silicon groove forming method according to claim 6 is characterized in that, when carrying out the silicon substrate etching, chamber pressure is 45~60mT; Power is 450~550W; HB rFlow is 40~45SCCM; CF 4Flow is 5~7SCCM; He-O 2Flow is 5~7SCCM.
8, according to the described silicon groove forming method of each claim in the claim 1 to 7, it is characterized in that, describedly in the silicon substrate etching apparatus, feed HB r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, forms after the step of silicon groove, also comprises:
Utilize the hydrofluoric acid solution wet method to remove remaining hard mask layer;
The silicon trench bottom is carried out the fillet etching.
9, a kind of silicon flute profile apparatus for converting is characterized in that, comprising:
The hard mask layer pop-in upgrades is used for the hard mask layer of growing on silicon substrate;
The photoresist layer coat module is used at hard mask layer surface-coated photoresist, obtains the photoresist figure through photoetching process;
The hard mask layer etch module is used for the etching hard mask layer, duplicates the photoresist figure to hard mask layer; The silicon substrate etch module is used for feeding HB to the silicon substrate etching apparatus r/ CF 4/ He-O 2Mist carries out etching to silicon substrate, forms the silicon groove.
10, silicon flute profile apparatus for converting according to claim 9 is characterized in that, also comprises:
Photoresist layer is removed module, is used to remove photoresist layer;
Hard mask layer is removed module, is used to utilize the hydrofluoric acid solution wet method to remove remaining hard mask layer.
11, silicon flute profile apparatus for converting according to claim 10 is characterized in that, also comprises:
The fillet etch module is used for the silicon trench bottom is carried out the fillet etching.
CN200810106025A 2008-05-07 2008-05-07 Silicon groove forming method and device Active CN100595895C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200810106025A CN100595895C (en) 2008-05-07 2008-05-07 Silicon groove forming method and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200810106025A CN100595895C (en) 2008-05-07 2008-05-07 Silicon groove forming method and device

Publications (2)

Publication Number Publication Date
CN101345194A true CN101345194A (en) 2009-01-14
CN100595895C CN100595895C (en) 2010-03-24

Family

ID=40247155

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200810106025A Active CN100595895C (en) 2008-05-07 2008-05-07 Silicon groove forming method and device

Country Status (1)

Country Link
CN (1) CN100595895C (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347237A (en) * 2010-07-29 2012-02-08 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device structure comprising stress layer
CN102485965A (en) * 2010-12-06 2012-06-06 中国科学院微电子研究所 Method for electroplating deep blind hole
CN102955200A (en) * 2011-08-30 2013-03-06 上海华虹Nec电子有限公司 Dry etching method for mono-crystalline silicon back etching of optical divider
CN103165435A (en) * 2013-03-14 2013-06-19 上海华力微电子有限公司 Silicon etching process
CN103576445A (en) * 2012-07-24 2014-02-12 无锡华润上华半导体有限公司 Photoetching method for photoresist as silicon groove etching mask
CN103854994A (en) * 2012-12-05 2014-06-11 北大方正集团有限公司 Etching method
CN103887224A (en) * 2014-03-20 2014-06-25 上海华力微电子有限公司 Method for forming shallow trench isolation
CN109390227A (en) * 2017-08-08 2019-02-26 天津环鑫科技发展有限公司 A kind of lithographic method of small line width vertical-type groove
CN109585281A (en) * 2018-12-05 2019-04-05 扬州扬杰电子科技股份有限公司 A kind of method for etching wafer
CN113066719A (en) * 2021-03-18 2021-07-02 吉林华微电子股份有限公司 Silicon wafer manufacturing method and silicon wafer
CN114924341A (en) * 2022-05-06 2022-08-19 上海交通大学 Method and system for improving verticality of side wall of FIB etching ultra-shallow grating structure
WO2023178895A1 (en) * 2022-03-21 2023-09-28 苏州东微半导体股份有限公司 Manufacturing method for silicon carbide device

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347237B (en) * 2010-07-29 2013-10-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device structure comprising stress layer
CN102347237A (en) * 2010-07-29 2012-02-08 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device structure comprising stress layer
CN102485965A (en) * 2010-12-06 2012-06-06 中国科学院微电子研究所 Method for electroplating deep blind hole
CN102955200A (en) * 2011-08-30 2013-03-06 上海华虹Nec电子有限公司 Dry etching method for mono-crystalline silicon back etching of optical divider
CN103576445B (en) * 2012-07-24 2016-08-03 无锡华润上华半导体有限公司 Photoetching method as the photoresist of silicon groove etching mask
CN103576445A (en) * 2012-07-24 2014-02-12 无锡华润上华半导体有限公司 Photoetching method for photoresist as silicon groove etching mask
CN103854994A (en) * 2012-12-05 2014-06-11 北大方正集团有限公司 Etching method
CN103165435A (en) * 2013-03-14 2013-06-19 上海华力微电子有限公司 Silicon etching process
CN103887224A (en) * 2014-03-20 2014-06-25 上海华力微电子有限公司 Method for forming shallow trench isolation
CN103887224B (en) * 2014-03-20 2017-01-11 上海华力微电子有限公司 Method for forming shallow trench isolation
CN109390227A (en) * 2017-08-08 2019-02-26 天津环鑫科技发展有限公司 A kind of lithographic method of small line width vertical-type groove
CN109390227B (en) * 2017-08-08 2020-09-29 天津环鑫科技发展有限公司 Etching method of small-linewidth vertical groove
CN109585281A (en) * 2018-12-05 2019-04-05 扬州扬杰电子科技股份有限公司 A kind of method for etching wafer
CN113066719A (en) * 2021-03-18 2021-07-02 吉林华微电子股份有限公司 Silicon wafer manufacturing method and silicon wafer
WO2023178895A1 (en) * 2022-03-21 2023-09-28 苏州东微半导体股份有限公司 Manufacturing method for silicon carbide device
CN114924341A (en) * 2022-05-06 2022-08-19 上海交通大学 Method and system for improving verticality of side wall of FIB etching ultra-shallow grating structure

Also Published As

Publication number Publication date
CN100595895C (en) 2010-03-24

Similar Documents

Publication Publication Date Title
CN100595895C (en) Silicon groove forming method and device
CN102738074B (en) Method for forming semiconductor structure
US9991116B1 (en) Method for forming high aspect ratio patterning structure
CN101752208B (en) Semiconductor high-voltage terminal structure and production method thereof
CN101572229A (en) Method for flattening surface of polysilicon
CN103578988A (en) Fin part and finned-type field-effect transistor and forming method thereof
JP6263822B2 (en) Manufacturing method of solar cell
CN105810582A (en) Etching method
CN100492603C (en) Plasma etching method
CN101599429B (en) Method for forming side wall
CN108364867A (en) Deep silicon etching method
CN102243995B (en) The integrated approach of different thickness grid oxygen in high-pressure process
CN1632921A (en) Two-step reduction etching technique capable of reducing grid characteristic dimension
JP3094470B2 (en) Dry etching method
CN102315129B (en) Preparation method of vertical silicon nanowire field effect transistor
CN102142377A (en) Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device
CN103413779B (en) Silicon etching method for forming through hole
CN101577253B (en) Method for writing rounded top angle of gate during preparation of EEPROM device
CN103021925A (en) STI (shallow trench isolation) manufacturing process, trench etching method and photoresist processing method
CN100397586C (en) Polycrystalline silicon pulse etching process for improving anisotropy
CN103632950B (en) Nitride film formation method between polysilicon in groove type double-layer grid MOS
CN102916043B (en) MOS-HEMT device and manufacturing method thereof
CN105720002B (en) Inclined hole lithographic method
CN101436536B (en) Method for dry method etching polycrystalline silicon in deep plow groove
CN103137564B (en) Method for achieving expanding base region structure in bipolar-complementary metal oxide semiconductor (BiCMOS) device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20220718

Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province

Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd.

Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 5 floor

Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd.

Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd.