CN102479545A

CN102479545A - 6T CMOS SRAM unit

Info

Publication number: CN102479545A
Application number: CN2010105716645A
Authority: CN
Inventors: 梁擎擎; 钟汇才
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2010-11-29
Filing date: 2010-11-29
Publication date: 2012-05-30
Anticipated expiration: 2030-11-29
Also published as: CN102479545B

Abstract

The invention discloses a 6T CMOS SRAM unit, which comprises two NMOS transmission gate transistors, two PMOS pull-up transistors and two NMOS pull-down transistors, and is characterized in that the source electrode of the PMOS pull-up transistor is connected with a word line connected with the grid electrode of the NMOS transmission gate transistor, and the threshold voltage of the NMOS transmission gate transistor is higher than the voltage value of the word line in a standby state. By connecting the source of the pull-up transistor originally connected to a high voltage to the gate terminal of the transfer gate transistor together with the word line, the potential at the standby time is significantly lower than the high potential at the read-write time, thereby reducing the standby leakage current.

Description

A kind of 6T CMOS sram cell

Technical field

The present invention relates to the SIC (semiconductor integrated circuit) design field, particularly a kind of 6T CMOS sram cell.

Background technology

In VLSI designs (VLSI, Very Large Scale Integrated Circuits), consumption of electric becomes a more and more important characteristic.In all electric quantity consumptions, the consumption of the standby leakage (stand-by leakage) of SRAM (Static Random Access Memory, static RAM) is a very significant part.With reference to figure 1; Fig. 1 is a basic 6T CMOS sram cell at present commonly used, comprises drawing pull up transistor 104 the same high voltage of drain electrode (Pdd) of (pull-up)

transistor

104 and 106, two PMOS of two NMOS drop-down (pull-down) transistor to link to each other on two NMOS transmission grid (pass-gate) transistors 102, two PMOS; The source electrode of two NMOS pull-down transistors 106 links to each other with low-voltage; The same word line of grid (wordline) of transmission gate transistor 102 connects, for this 6T sram cell, in order to reduce the standby leakage of SRAM; The most frequently used method is the threshold voltage that increases the sram cell device; But this way not only can make the access delay of storage unit, has also increased not matching of storage unit internal node changing voltage, thereby has also limited the minimum value of supply voltage.

Therefore, be necessary to propose a kind of sram cell that can reduce standby leakage and need not to improve device threshold voltage.

Summary of the invention

In order to address the above problem; The invention provides a kind of 6T CMOS sram cell; Comprise that two NMOS transmission gate transistors, two PMOS pull up transistor and two NMOS pull-down transistors; It is characterized in that the source electrode that said PMOS pulls up transistor is connected the magnitude of voltage the when threshold voltage of said NMOS transmission gate transistor is higher than holding state on the word line with the word line that links to each other with said NMOS transmission gate transistor grid.

According to 6T CMOS sram cell of the present invention, originally be connected to high-tension source electrode with pulling up transistor and together be connected, and make the threshold voltage voltage on the word line during that transmits gate transistor less than holding state with word line with the gate terminal of transmission gate transistor; Like this when holding state; Transmit gate transistor and pull up transistor and all be connected the noble potential the when current potential during standby significantly is lower than read-write, thereby reduction standby leakage amount with low-tension supply; On the other hand; When access status, transmission gate transistor and pulling up transistor all is connected with high-voltage power supply, has reduced the soft fault rate (soft failure) of read-write.

Description of drawings

Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:

Fig. 1 shows the synoptic diagram of basic 6T CMOS sram cell;

Fig. 2 shows the synoptic diagram according to the 6T CMOS sram cell of the embodiment of the invention;

Fig. 3 shows basic 6T CMOS sram cell centralized storage node voltage and changes synoptic diagram;

Fig. 4 shows the emulation contact potential series figure according to the 6T CMOS sram cell operation of the embodiment of the invention.

Embodiment

Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.

With reference to figure 2; 6T CMOS sram cell according to the embodiment of the invention has been shown among Fig. 2; Said unit comprises: two NMOS transmission gate transistor 302, two PMOS 304 and two NMOS pull-down transistors 306 that pull up transistor; Said six transistors 302,304, the connection between 306 are identical with the connection of basic 6T CMOS sram cell; The one PMOS pulls up transistor and is connected to first phase inverter 310 with a NMOS pull-down transistor; The 2nd PMOS centralized storage node n1 that is connected to second phase inverter, 320, the first phase inverters 310 with the 2nd NMOS pull-down transistor that pulls up transistor directly is connected to two transistorized grids of second phase inverter, and the centralized storage node n2 of second phase inverter 320 directly is connected to two transistorized grids of first phase inverter; The centralized storage node n1 of first phase inverter 310 writes and reads through the NMOS transmission gate transistor that meets bit line (bit line) Bit1; The centralized storage node n2 of second phase inverter 320 writes and reads through the 2nd NMOS transmission gate transistor that meets bit line Bit2, and wherein Bit1 and Bit2 are opposite each other signals, and the grid of two said transmission transistors 302 connects word line 308.For sram cell of the present invention; The drain electrode of said NMOS pull-down transistor is connected with low-voltage; Said PMOS pulls up transistor 304 source electrode with being connected with said word line 308, and the threshold voltage of said NMOS transmission gate transistor 302 magnitude of voltage on the word line when being higher than holding state, and said transmission gate transistor is closed when holding state like this; And other transistors are in low power supply status, thereby have reduced standby leakage.With reference to figure 3, Fig. 3 shows centralized storage node n1 and the n2 synoptic diagram with mains voltage variations, in the illustrated embodiment; The voltage that n1 and n2 are ordered overturns about 0.3V, therefore, and when holding state; Because word line is connected with pulling up transistor, through selecting about the supply voltage value (like 0.4V) bigger slightly, among other embodiment than this turnover voltage; The representative value of the current potential on the holding state word line is about 0.3-0.7V, and the representative value of the current potential during read-write state on the word line is about 0.7-1V, and the current potential during holding state can select significantly to be lower than the potential value of read-write state; For example the read-write state word line potential is 1V, and the holding state word line potential is selected about 0.4V, and the source voltage that pulls up transistor at PMOS during owing to this voltage ratio read-write state significantly reduces; Standby leakage will greatly reduce, in addition, and when read-write state; The source voltage that PMOS pulls up transistor still can be kept higher point position (like 0.7-1V), and than the method that increases device threshold voltage, this method can not make access delay; Can not change the turnover voltage of inner access node n1/n2, promptly the supply voltage minimum value can not be limited yet yet.

As shown in Figure 2; Sram cell of the present invention is carried out emulation, at said sram cell 3 00 pulse power 330 is provided, the low-voltage of the said pulse power is about 0.4V; The low-tension supply of emulation holding state; The high voltage of the said pulse power is about 0.7-1V, the high-voltage power supply of emulation read-write operation state, and Fig. 4 is the contact potential series figure in storage/access (read/write) when operation of the emulation of sram cell of the present invention.

More than 6T CMOS sram cell according to the present invention has been carried out detailed description, connect through pulling up transistor and originally be connected to high-tension source electrode and together be connected, and make the threshold voltage voltage on the word line during that transmits gate transistor less than holding state with word line with the gate terminal of transmission gate transistor; Like this when holding state; Transmit gate transistor and pull up transistor and all be connected the noble potential the when current potential during standby significantly is lower than read-write, thereby reduction standby leakage amount with low-tension supply; On the other hand; When access status, transmission gate transistor and pulling up transistor all is connected with high-voltage power supply, has reduced the soft fault rate (soft failure) of read-write.

Though specify about example embodiment and advantage thereof, be to be understood that under the situation of the protection domain that does not break away from the qualification of spirit of the present invention and accompanying claims, can carry out various variations, replacement and modification to these embodiment.

Claims

1. 6T CMOS sram cell; Comprise that two NMOS transmission gate transistors, two PMOS pull up transistor and two NMOS pull-down transistors; It is characterized in that; The source electrode that said PMOS pulls up transistor is connected the current potential the when threshold voltage of said NMOS transmission gate transistor is higher than holding state on the word line with the word line that links to each other with said NMOS transmission gate transistor grid.

2. current potential when the current potential when unit according to claim 1, wherein said holding state on the word line is lower than read-write state.

3. the current potential when unit according to claim 2, wherein said holding state on the word line is 0.3-0.7V.

4. the current potential when unit according to claim 2, wherein said read-write state on the word line is 0.7-1V.

5. unit according to claim 1, the drain electrode of wherein said NMOS pull-down transistor connects with low-voltage.

6. unit according to claim 1, wherein said two PMOS pull up transistor and form two phase inverters that couple each other with two NMOS pull-down transistors, and the centralized storage point of said phase inverter is connected with said NMOS transmission gate transistor respectively.