CN102456741B - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN102456741B
CN102456741B CN201110318482.1A CN201110318482A CN102456741B CN 102456741 B CN102456741 B CN 102456741B CN 201110318482 A CN201110318482 A CN 201110318482A CN 102456741 B CN102456741 B CN 102456741B
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gate electrode
buried
conductive type
type impurity
impurity layer
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CN102456741A (zh
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川岛义也
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Renesas Electronics Corp
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Abstract

一种半导体器件，意在防止外阱通过沟槽栅电极与单元区域的阱分离，同时抑制栅极电阻的增加，其中在与栅极接触区重叠的方向上延伸的掩埋栅电极仅延伸到栅电极之前，以没有与栅电极重叠，在图中的垂直方向上，位于每个掩埋栅电极之间的源极接触形成为比掩埋栅电极短，栅电极的一侧上的掩埋栅电极的端部通过布置在栅电极之前的掩埋连接电极彼此连接，掩埋连接电极在与半导体器件的长边平行的方向上延伸，并且掩埋连接电极没有连接到与接触侧掩埋栅电极相邻的接触的一侧上的掩埋栅电极。

Description

半导体器件
相关申请的交叉引用
包括说明书、附图和摘要的2010年10月20日提交的日本专利申请No.2010-235632的公开通过引用整体并入这里。
技术领域
本发明涉及一种具有沟槽栅电极的半导体器件。
背景技术
高耐受电压半导体器件包括具有沟槽栅电极的半导体器件，例如，垂直MOSFET或IGBT。这种半导体器件所需的一个性能是导通电阻低。半导体器件的精细化是降低导通电阻的一种方法。然而，随着精细化，近年来产生了一个问题，即栅电极之间的距离减小了，从而栅电极的寄生电容增加了。考虑到上述，FOM(品质因数)，即(导通电阻)×(栅电极的寄生电容)近年来被用作示出具有沟槽栅极结构的半导体器件的性能的一个度量。
提高FOM的一种技术包括通过采用确保半导体器件的耐受电压以增加外延层的杂质浓度并且降低电阻的结构来降低导通电阻的方法。例如，P.Goarin等人公开了通过在沟槽内部形成深沟槽并且形成厚氧化物膜来确保半导体器件的耐受电压的方法(Proceedingsof19thInternationalSymposiumonPowerSemiconductorDevices&ICs，2007，pp.61-64)。此外，Y.Kawashima等人公开了通过利用pn结来确保半导体器件的耐受电压的方法(Proceedingsofthe22ndInternationalSymposiumonPowerSemiconductorDevices&ICs，2010，pp.329-332)。日本未审查专利公布No.2009-32951描述了通过延伸势阱直到邻近单元区域的周围区域，可以防止降低半导体器件的耐受电压。
日本未审查专利公布No.2001-217419描述了：通过在平面布局中形成基本上弓形形状的沟槽的角，能够防止施加在栅极绝缘膜上的电场强度的局部增加。
发明内容
当与外延层的导电类型相反的导电类型的杂质层(即，与单元区域的阱相同结构的杂质层)布置到围绕单元区的***时，由于在杂质区和外延层之间形成了pn结，所以能够确保***处的耐受电压。然而，由于沟槽栅电极比上述的杂质区域(外阱)形成得更深，所以使外阱处于通过沟槽栅电极与单元区域的阱分离的浮置状态。为了防止这样，需要巧妙地设计沟槽栅电极的平面布局。另一方面，由于沟槽电极大约延伸了长的距离，所以栅极电阻可以依据平面布局而增加。
因此，需要巧妙设计沟槽栅电极的平面布局，以抑制外部的阱通过沟槽栅电极与单元区域的阱分离，同时抑制栅极电阻的增加。
根据本发明的一方面，提供一种半导体器件，包括：
半导体衬底；
第一导电类型半导体层，其形成在半导体衬底的上方；
第二导电类型杂质层，其形成在半导体层的表面层中；
第一导电类型杂质层，其形成到除了边缘之外的第二导电类型杂质层的表面层；
栅极接触区，其通过在平面图中向内凹进第一导电类型杂质层而形成；
上栅电极，其至少一部分由其中没有形成第一导电类型杂质层的第二导电类型杂质层的区域上方的绝缘层形成，围绕第一导电类型杂质层，并且在平面图中在与栅极接触区重叠的部分处向内突出；
多个第一掩埋栅电极，其形成在其中形成第一导电类型杂质层的半导体层的区域中，在半导体层中比第二导电类型杂质层掩埋得更深，沿着第一方向彼此平行延伸，且其两端分别延伸超出第一导电类型杂质层从而连接到上栅电极；
第一掩埋连接电极，其在与上栅电极重叠的位置处掩埋在半导体层中，掩埋到与第一掩埋栅电极相同的深度，并将第一掩埋栅电极的端部彼此连接；和
源极接触，其在半导体层中掩埋得比第一导电类型杂质层更深且比第二导电类型杂质层的底部更浅，并且每个都位于第一掩埋栅电极中的每一个之间，其中
在与位于栅极接触区中的上栅电极重叠的方向上延伸的第一掩埋栅电极中的至少一些的端部在平面图中位于栅极接触区的边缘上，
端部通过第一掩埋连接电极彼此连接，以及
第一掩埋连接电极没有连接到作为邻近于在其端部通过第一掩埋连接电极彼此连接的第一掩埋栅电极的第一掩埋栅电极的接触的一侧上的第一掩埋栅电极。
根据本发明的方面，由于在位于栅极接触区中的第二导电类型杂质层和半导体层之间形成了pn结，所以能够在第一导电类型杂质层的***处确保垂直方向上的耐受电压。此外，虽然第一掩埋栅电极的端部通过栅极接触区附近的第一掩埋连接电极彼此连接，但是第一掩埋连接电极没有连接到接触的一侧上的第一掩埋栅电极。因此，位于栅极接触区中的第二导电类型杂质层可以连接到位于接触的一侧上的第一掩埋栅电极和与之邻近布置的第一掩埋栅电极之间的部分处形成第一导电类型杂质层的区域中的第二导电类型杂质层。位于其中形成第一导电类型杂质层的层中的第二导电类型杂质层通过源极接触被提供有预定的电势。因而，能够防止位于栅极接触区中的第二导电类型杂质层的浮置。
此外，由于其端部定位在栅极接触区的边缘上的第一掩埋栅电极通过第一掩埋连接栅电极彼此连接，所以能够抑制栅极电阻的增加。
根据本发明的这些方面，能够防止外阱由于沟槽栅电极而与单元区的阱断开，同时抑制了栅极电阻增加。
附图说明
图1是示出根据第一实施例的半导体器件的构造的平面图；
图2是示出第二导电类型杂质层和***杂质层的布局的平面图；
图3是示出图1中的区域α中掩埋栅电极的布局的放大平面图；
图4是沿着图3中的A-A′的截面图；
图5是示出制造图1至图4中所示的半导体器件的方法的截面图；
图6是示出制造图1至图4中所示的半导体器件的方法的截面图；
图7是示出制造图1至图4中所示的半导体器件的方法的截面图；
图8是根据比较实施例的半导体器件的放大平面图；
图9是示出根据第二实施例的半导体器件的构造的放大平面图；
图10是沿着图9中的A-A′的截面图；
图11是根据第三实施例的半导体器件的平面图；
图12是示出根据第四实施例的半导体器件的构造的放大平面图；
图13是根据第五实施例的半导体器件的截面图；
图14是图13中所示的半导体器件的放大平面图；和
图15是示出根据第六实施例的半导体器件的构造的截面图。
具体实施方式
参考附图通过优选实施例描述本发明。在所有图中，相同的组成元素带有相同的附图标记，将选择性地省略其描述。
第一实施例
图1是示出根据第一实施例的半导体器件的构造的平面图。图2是示出图1中所示的半导体器件的第二导电类型杂质层120和***杂质层122的布局的平面图。图3是示出在由图1和图2中的虚线示出的区域α中的掩埋栅电极140的布局的放大平面图。图4是沿着图3中的A-A′的截面图。
根据本实施例的半导体器件具有半导体衬底100、半导体层110、第二导电类型杂质层120、第一导电类型的杂质层150、栅极接触区102、上栅电极160、多个掩埋栅电极140、掩埋连接电极141、143和源极接触220。如图4中所示，半导体层110形成在半导体衬底100上方，并且具有第一导电类型(例如，n型)。如图4中所示，第二导电类型杂质层120形成在半导体层110的表面层上，并且例如具有p导电类型。如图2和图4中所示，第一导电类型杂质层150形成在除边缘之外的第二导电类型杂质层120的表面层的区域中。如图4中所示，在平面图中，通过向内凹进第一导电类型杂质层150形成栅极接触区102。如图1和图4中所示，至少一部分上栅电极160通过其中没有形成第一导电类型杂质层150的第二导电类型杂质层120的区域上方的绝缘层162形成。上栅电极160围绕第一导电类型杂质层150，并且在平面图中其与栅极接触区102重叠的部分向内突出。如图4中所示，掩埋栅电极140形成在其中形成第一导电类型杂质层150的半导体层110的区域中，并且在半导体层110中掩埋得比第二导电类型杂质层120更深。如图1、2和3中所示，掩埋栅电极140沿着第一方向(图中的垂直方向)彼此平行延伸，并且在其两端分别延伸超出第一导电类型杂质层150且与上栅电极160连接。掩埋连接电极141、143掩埋在半导体层110中与上栅电极160重叠的位置，并且掩埋到与掩埋栅电极140的深度相同的深度，并且将掩埋栅电极140的端部彼此连接。源极接触220在半导体层110中掩埋得比第一导电类型杂质层150更深，并且比第二导电类型杂质层120的底部更浅，并且每个都位于掩埋栅电极140中的每一个之间。然后，在与处于栅极接触区102中的栅电极160重叠的方向上延伸的至少一部分掩埋栅电极142的端部处于栅极接触区102的边缘上，并且端部通过掩埋连接电极141彼此连接。此外，掩埋连接电极141没有与掩埋栅电极144连接，掩埋栅电极144是与端部通过掩埋连接电极141彼此连接的掩埋栅电极142邻近的掩埋栅电极140。将进行更具体的描述。
在本实施例中，半导体器件具有垂直型MOS晶体管。半导体衬底100具有第一导电类型(例如，n型)。半导体层110通过半导体衬底100上的外延生长形成，并用作MOS晶体管的漏极。在没有形成有半导体层110的半导体100的表面处，对于整个表面布置漏电极330。除了要形成***杂质层122的区域之外，第二导电类型杂质层120用作MOS晶体管的阱。第一导电类型杂质层150用作MOS晶体管的源极。恒定电势，例如，地电位通过源极接触220施加到第一导电类型杂质层150和第二导电类型杂质层120。源极接触220的上端与图1和图4中所示的源电极320连接。
如图4中所示，掩埋栅电极140掩埋在半导体层110中形成的沟槽中。栅极绝缘膜130形成在沟槽的内周围表面和底部处。掩埋栅电极140在半导体层120中掩埋得比第二导电类型杂质层120更深。因而，第二导电类型杂质层120通过半导体层110分开。然后，在第二导电类型杂质层120的最外侧，位于掩埋栅电极140的外侧的第二导电类型杂质层120的一部分区域，形成***杂质层122。在图1和图2中所示的实施例中，半导体器件的平面形状是矩形。然后，沿着半导体器件的边缘形成***杂质层122，以围绕第一导电类型杂质层150。
在平面图中，第一导电类型杂质层150的一部分***向内凹进。然后，凹进部分形成栅极接触区102。在图1和图2中所示的实施例中，栅极接触区102形成为在平面图中基本上位于半导体器件的短边侧的中心部分。一部分上栅电极160和栅电极310形成在栅极接触区102中。在位于栅极接触区102的部分处，栅电极310与上栅电极160接触。此外，上栅电极160沿着半导体器件的四个边布置。沿着半导体器件的长边延伸的一部分上栅电极160连接到掩埋栅电极140。因此，栅电极310通过上栅电极160连接到掩埋栅电极140。
如图1、2和3中所示，在平面图中与半导体器件的短边平行的方向上，掩埋栅电极140从半导体器件的一个长边附近延伸到另一个长边附近。然后，掩埋栅电极140的端部在半导体器件长边附近连接到上栅电极160。此外，掩埋连接电极143平行于半导体器件的长边在半导体器件的长边附近延伸，使得掩埋连接电极143与上栅电极160重叠。然后，掩埋栅电极140的端部通过掩埋连接电极143彼此连接。
虽然掩埋栅电极140布置成多个，并且每个以预定的距离彼此平行，但是在平面图中在与接触区102重叠的方向上延伸的掩埋栅电极140的掩埋栅电极142仅在栅电极310之前延伸以便于没有覆盖栅电极310。此外，在图中的垂直方向上，位于每个掩埋栅电极142之间的源极接触222的长度比掩埋栅电极142短。然后，栅电极310侧上的掩埋栅电极142的端部通过布置在栅电极310之前的掩埋连接电极141彼此连接。掩埋连接电极141在与半导体器件的长边平行的方向上延伸。掩埋连接电极141和掩埋栅电极142的端部与上栅电极160重叠。
然后，掩埋连接电极141没有连接到邻近掩埋栅电极142的掩埋栅电极144。从而，如图3中所示，在掩埋栅电极142和掩埋栅电极144之间的部分处，***杂质层122连接到第二导电类型杂质层120。源极接触222也布置在掩埋栅电极142和掩埋栅电极144之间。因此，通过位于掩埋栅电极142和掩埋栅电极144之间的第二导电类型杂质层120，***杂质层122连接到源极接触222。
图5、图6和图7是示出制造图1至图4中所示的半导体器件的方法的截面图。首先，如图5中所示，在半导体衬底100上方外延生长半导体层110。然后，形成掩模图案(没有示出)，并且利用该掩模图案作为掩模，将第二导电类型杂质注入半导体层110中。由此，形成了***杂质层122。然后，在半导体层110中形成用来形成掩埋栅电极140的沟槽。然后，热氧化半导体层110的表面。由此，形成了栅极绝缘膜130和绝缘层162。然后，在绝缘层162上方和沟槽中形成导电膜170，例如，多晶硅膜。
如图6中所示，选择性地移除导电膜170。由此，形成了上栅电极160和掩埋栅电极140(包括掩埋栅电极142、144等)。然后，利用上栅电极160作为掩模，向半导体层110中注入第二导电类型杂质。由此，形成第二导电类型杂质层120。此外，在第二导电类型杂质层120上方形成掩模图案，并利用该掩模图案作为掩模，向第二导电类型杂质层120中注入第一导电类型杂质。由此，形成第一导电类型杂质层150。然后，在任意时刻进行用来活化注入的杂质的热处理。由于第二导电类型杂质层120和***杂质层122中的杂质在热处理期间扩散，所以第二导电类型杂质层120和***杂质层122彼此结合。然后，当***杂质层122适合于在形成***杂质层122时在平面图中从上栅电极160向第二导电类型杂质层120伸出时，第二导电类型杂质层120和***杂质层122更可靠地接合。
然后，如图7中所示，在上栅电极160和半导体层110上方形成层间绝缘膜200。然后，通过选择性移除层间绝缘膜200形成孔，并在孔中掩埋导体材料。由此，形成了栅极接触210和源极接触220。然后，在层间绝缘膜200上方形成栅电极310和源电极320。
下面将要描述本实施例的功能和效果。如上所述，掩埋连接电极141没有连接到邻近掩埋栅电极142的掩埋栅电极144。因此，***杂质层122通过位于掩埋栅电极142和掩埋栅电极144之间的第二导电类型杂质层120连接到源极接触222。此外，由于源极接触222通过源电极320连接到源极接触220，所以这能够防止***杂质层122的浮置。
此外，由于掩埋连接电极141将掩埋栅电极142彼此连接，所以能够抑制在掩埋栅电极142的一部分处的掩埋栅电极140的栅极电阻的增加。
参考图8中示出的比较实施例，描述该效果。在图8中示出的比较实施例中，掩埋连接电极141中途断开，并且没有将一部分掩埋栅电极142彼此连接。相反地，掩埋连接电极141连接到掩埋栅电极144。在这种情况下，由于***杂质层122在其中掩埋连接电极141中途断开的部分处连接到第二导电类型杂质层120，所以其没有处于浮置状态。然而，由于掩埋连接电极141中途断开，所以增加了掩埋栅电极142的栅极电阻。相反地，在本实施例中，由于掩埋连接电极141将所有的掩埋栅电极142彼此连接，所以能够抑制掩埋栅电极142的栅极电阻的增加。
第二实施例
图9是示出根据第二实施例的半导体器件的构造的放大平面图，其对应于第一实施例的图3。图10是沿着图9中的A-A′的截面图。除了下面要描述的几点之外，根据本实施例的半导体器件具有与根据第一实施例的半导体器件相同的构造。
首先，邻近掩埋栅电极142的掩埋栅电极144具有与掩埋栅电极142相同的长度，并且在图中的垂直方向上，端部的位置与掩埋栅电极142的端部的位置相同。然后，通过掩埋连接电极141连接掩埋栅电极144的端部。
此外，在源极接触220中，在掩埋栅电极144和与之相邻的掩埋栅电极145之间延伸的源极接触222还在位于栅极接触区102处的上栅电极160的部分和掩埋栅电极145之间延伸。
而且在本实施例中，可以获得与第一实施例相同的效果。此外，虽然源极接触222也在位于栅极接触区102处的上栅电极160的部分和掩埋栅电极145之间延伸，但是掩埋栅电极144没有形成在源极接触222和***杂质层122之间。因而，由于缩短了连接到***杂质层122的源极接触220的部分(也就是，源极接触222)到***杂质层122的距离，所以能够抑制源极接触222和***杂质层122之间的电压损耗。
第三实施例
图11是根据第三实施例的半导体器件的平面图，其对应于第一实施例的图1。除了栅极接触区102位于半导体器件的角处之外，根据本实施例的半导体器件具有与第一或第二实施例的半导体器件相同的构造。图11示出了与第一实施例相同的情形。而且在本实施例中，能够获得与第一或第二实施例相同的效果。此外，在封装成最终产品时，还能够缩短从引线框架(在图中位于芯片上面)到栅极焊盘的连接所需的布线长度。
第四实施例
图12是示出根据第四实施例的半导体器件的构造的放大平面图，其对应于第一实施例的图3。除了下面几点之外，本实施例的半导体器件具有与第一至第三实施例的半导体器件相同的构造。图12示出了与第一实施例相同的情况。
首先，掩埋栅电极140形成为网络形式，以构成网格。即，掩埋栅电极140不仅形成在图中的垂直方向上，而且形成在图中的横向方向上。因此，相邻的掩埋栅电极140彼此连接。
然后，源极接触220布置在由掩埋栅电极140形成的每个网格单元中。掩埋栅电极140没有形成在邻近栅极接触区102且最靠近掩埋栅极144的源极接触220的源极接触224和***杂质层122之间。
而且在本实施例中，由于源极接触224通过第二导电类型杂质层120连接到***杂质层122，所以能够获得与第一至第三实施例相同的效果。此外，由于掩埋栅电极140形成为网格结构，所以能够降低掩埋栅电极140的栅极电阻。
第五实施例
图13是根据第五实施例的半导体的截面图，其对应于第一实施例的图4。图14是图13中示出的半导体器件的放大平面图。除了提供多个第二导电类型掩埋层124之外，根据本实施例的半导体器件具有与第一至第四实施例相同的结构。
第二导电类型掩埋层124形成在半导体层110中。第二导电类型掩埋层124在其上端连接到第二导电类型杂质层120或***杂质层122，并且彼此隔开。在该图中示出的实施例中，每个第二导电类型掩埋层124布置为位于网格的每个顶点上。此外，一些第二导电类型掩埋层124在平面图中与源极接触220重叠，其他第二导电类型掩埋层124在平面图中与***杂质层122重叠。在本实施例中，虽然在任意区域中，布置第二导电类型掩埋层124的空间彼此相同，但是这不是限制性的。
而且在本实施例中，能够获得与第二实施例相同的效果。此外，第二导电类型掩埋层124形成在半导体层110中比第二导电类型杂质层120更深的位置处。第二导电类型掩埋层124与半导体层110形成pn结，并且该pn结提高了漏电极330和源电极320之间的耐受电压。因此，能够通过增加半导体层110中的杂质浓度降低半导体器件的导通电阻。
第六实施例
图15是示出根据第六实施例的半导体器件的结构的截面图，其对应于第一实施例的图4。除了用第二导电类型半导体衬底101代替了第一导电类型半导体衬底100之外，根据本实施例的半导体器件具有与第一至第五实施例相同的结构。也就是说，根据本实施例的半导体用作IGBT(绝缘栅双极晶体管)。而且在本实施例中，能够获得与第一至第五实施例相同的效果。
虽然已经参考附图对于优选实施例描述了本发明，但是它们只是本发明的示例，并且能够采取除了上述这些结构之外的各种其它结构。

Claims (7)

1.一种半导体器件，包括：
半导体衬底；
第一导电类型半导体层，所述第一导电类型半导体层形成在所述半导体衬底上方；
第二导电类型杂质层，所述第二导电类型杂质层形成在所述半导体层的表面层中；
第一导电类型杂质层，所述第一导电类型杂质层形成到除边缘外的所述第二导电类型杂质层的表面层；
栅极接触区，所述栅极接触区被形成为使得在平面图中，所述第一导电类型杂质层延伸以围绕所述栅极接触区；
上栅电极，所述上栅电极的至少一部分在其中没有形成所述第一导电类型杂质层的所述第二导电类型杂质层的区域上方经由绝缘层形成，围绕所述第一导电类型杂质层，其中，在平面图中，所述上栅电极在所述上栅电极的与所述栅极接触区重叠的部分处向内突出；
多个第一掩埋栅电极，所述多个第一掩埋栅电极形成在其中形成所述第一导电类型杂质层的所述半导体层的区域中，比所述第二导电类型杂质层更深地掩埋在所述半导体层中，在平面图中，沿着第一方向彼此平行延伸，并且在第一方向上在其两端上分别延伸超出所述第一导电类型杂质层，从而连接到所述上栅电极；
掩埋连接电极，所述掩埋连接电极在与所述上栅电极重叠的位置处、以与所述第一掩埋栅电极相同的深度掩埋在所述半导体层中，并且将所述第一掩埋栅电极中的至少一些的端部彼此连接；和
多个源极接触，所述多个源极接触比所述第一导电类型杂质层更深地且比所述第二导电类型杂质层的底部更浅地掩埋在所述半导体层中，并且每一个源极接触位于两个第一掩埋栅电极之间，
其中在与位于所述栅极接触区中的所述上栅电极重叠的方向上延伸的所述第一掩埋栅电极中的所述至少一些在其端部处在平面图中位于所述栅极接触区的边缘上，
其中所述第一掩埋栅电极中的所述至少一些的所述端部通过所述掩埋连接电极彼此连接，并且
其中所述掩埋连接电极没有连接到在所述第一掩埋栅电极的与通过所述掩埋连接电极在其端部彼此连接的所述第一掩埋栅电极相邻的一侧上的所述第一掩埋栅电极，并且
其中在平面图中，所述第一掩埋栅电极中的所述至少一些在与所述栅极接触区重叠的方向上延伸仅到达布置在所述栅极接触区中的栅电极之前，使得所述第一掩埋栅电极中的所述至少一些避免与布置在所述栅极接触区中的所述栅电极重叠。
2.根据权利要求1的半导体器件，
其中在平面图中在经过位于所述栅极接触区处的所述上栅电极的一部分的侧面的方向上延伸的所述第一掩埋栅电极当中，与所述第一掩埋栅电极中的所述至少一些相邻的所述第一掩埋栅电极在其端部处在第一方向上位于与所述掩埋连接电极相同的位置。
3.根据权利要求2的半导体器件，
其中在所述第一掩埋栅电极当中，在位于所述栅极接触区中的所述上栅电极的所述一部分的侧面的所述第一掩埋栅电极沿着位于所述栅极接触区中的所述上栅电极的所述一部分的侧面延伸，并且所述源极接触形成在位于所述栅极接触区中的所述上栅电极的所述一部分和与所述上栅电极的所述一部分相邻的所述第一掩埋栅电极之间。
4.根据权利要求1的半导体器件，进一步包括：
第二掩埋栅电极，所述第二掩埋栅电极在与第一方向垂直的方向上延伸，并且将所述第一掩埋栅电极中的一个分别连接到所述第一掩埋栅电极中的相邻的一个。
5.根据权利要求1的半导体器件，进一步包括：
多个第二导电类型掩埋层，所述多个第二导电类型掩埋层形成在所述半导体层中，并且在其上端连接到所述第二导电类型杂质层，并且被布置为彼此分开。
6.根据权利要求1的半导体器件，其中所述半导体衬底是第一导电类型。
7.根据权利要求1的半导体器件，其中所述半导体衬底是第二导电类型。
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