CN102456654A - 无衬底的功率器件封装 - Google Patents

无衬底的功率器件封装 Download PDF

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Publication number
CN102456654A
CN102456654A CN2011103551572A CN201110355157A CN102456654A CN 102456654 A CN102456654 A CN 102456654A CN 2011103551572 A CN2011103551572 A CN 2011103551572A CN 201110355157 A CN201110355157 A CN 201110355157A CN 102456654 A CN102456654 A CN 102456654A
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Prior art keywords
wafer
substrate
solder bump
power semiconductor
chip
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CN2011103551572A
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CN102456654B (zh
Inventor
冯涛
牛志强
龚玉平
吴瑞生
黄平
石磊
何约瑟
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

一种无衬底的复合功率半导体器件包括一个很薄的衬底，以及一个位于衬底顶面上的顶部金属层。衬底和外延层的总厚度小于25微米。焊料***焊盘形成在顶部金属层上方，成型混料包围着焊料***焊盘，并使焊料***焊盘至少部分裸露出来。

Description

无衬底的功率器件封装
技术领域
本发明主要涉及超薄晶圆，更确切地说，是关于垂直功率半导体器件的无衬底芯片以及背部金属沉积工艺。
背景技术
半导体器件领域在一个晶圆上制备多个半导体器件封装芯片方面面临诸多挑战。对于芯片级封装金属氧化物半导体场效应管(MOSFET)器件，尤其是在半导体衬底的一个表面上具有栅极和源极区、在其对面具有漏极区的垂直传导的功率MOSFET器件而言更是如此。在指定的半导体器件正面形成电连接，在器件的背面必须再额外形成电连接。在半导体封装中，器件两边的电连接通常必须延伸到一个公共面上，便于器件的封装后使用。对于垂直传导的功率MOSFET器件等半导体器件而言，研究方向必须是较小的引脚图案/最小化的引脚以及较薄的封装厚度。小型化电子器件的行业趋势正在向最优化的近乎芯片级尺寸封装方向发展。与之类似，这也需要每个半导体器件封装芯片具有较小的电阻，例如导通电阻Rdson。可以通过减小半导体器件封装芯片的厚度来实现。由于传导电流垂直穿过半导体芯片，半导体芯片厚度的减小将大幅降低器件的导通电阻。
半导体器件封装芯片的另一个必备特征是较好的热耗散，这可以利用裸露底部和顶部来实现。另一个必备的效果是为半导体器件提供强大的支撑。强大的支撑带来的较好的稳定性也将降低损坏半导体器件芯片/衬底的风险。最后，作为晶圆级批量工艺，制备完成这些半导体器件的封装芯片也很重要，以便提高效率，并且减少制造这些半导体器件封装芯片所需的时间和成本。
对于在一个表面上带有多个连接，在对面带有至少一个连接的半导体器件(例如MOSFET器件)而言，获得上述必须的特征将需要在延伸连接到公共面上重新配置。通常还需要封装半导体器件的简便、快捷、高效的方法。
半导体晶圆通常一开始很厚，以便在晶圆处理以及制备半导体器件相关的各种工业中提供结构支撑。正面(器件端)工艺完成后，芯片通常需要背部研磨处理，以除去背部衬底部分。对于集成电路(IC)芯片而言，由于所有的器件元件都位于晶圆已经制成的正面上，并不再需要进一步的晶圆处理，所以晶圆可以做得非常薄。然而，垂直功率MOSFET等垂直传导器件还需要在背部研磨之后进行背部处理(例如刻蚀、背部金属制备等)，因此为了避免损坏晶圆需要更多的技术支持。对于垂直功率器件来说，已经有了制备超薄(例如约为2至4密耳)晶圆/芯片的传统方法。对于透视图，2密耳约为人的一根头发的直径，比一张纸薄的多。这种厚度甚至更薄的晶圆非常易碎，易受损坏。然而，晶圆越薄，在垂直半导体器件中的电阻就越低，也就是说，在这种半导体器件中，电流是垂直的，即垂直于晶圆背面。减小晶圆厚度是降低Rdson的有效途径。在晶圆厚度8密耳的低压功率沟槽MOSFET器件中，衬底电阻可以是总Rdson的50％。使用超薄晶圆还可以确保功率器件满足总封装厚度的严格要求。然而，垂直半导体晶圆越薄，在晶圆背部处理和其他背部研磨后的工艺时造成损坏(例如晶圆裂碎)的风险越高。
图1A-1E表示通过旋涂方法，用于减薄和处理晶圆(例如硅或玻璃)的3MTM晶圆支持***示例的剖面图。如图1A所示，旋涂上一层紫外树脂或紫外-固化液体106，在初始厚度约为750微米的晶圆108的正面107上做成一个涂层。然后将带涂层的晶圆翻转过来，通过沉积在支撑玻璃102和紫外树脂涂层106之间的光-热转换(LTHC)释放复合物104，真空连接到支撑玻璃102上。利用紫外线照射固化树脂涂层。如图1B所示，利用研磨轮112，通过研磨晶圆108的背面110，例如将它减薄到20微米。再次将带有支撑玻璃102的减薄晶圆108翻转过来，置于具有切割框116的切割带114上，以便承载图1C所示的晶圆。在LTHC释放物104上方使用激光照射，以除去支撑玻璃102。如图1D所示，除去紫外树脂层106和晶圆108上的支撑玻璃102。如图1E所示，剥掉减薄晶圆108上的紫外树脂层106。在该传统方法中，与全厚度晶圆类似，可以轻松地进行晶圆级减薄和处理。然而，这种方法存在许多弊端。例如，粘合剂104、树脂106以及其他聚合物材料在真空处理工艺(例如金属化)时，可以在真空腔中除气。去除支撑晶圆(支撑玻璃102)的步骤可能有损坏晶圆的风险。最终，总厚度变化(Total thicknessvariation，简称TTV)取决于支撑晶圆(Handle Wafer)厚度的精确性。支撑晶圆仅能再次使用有限的次数，这使得它比较昂贵。
还可选择，利用自支撑环研磨技术，研磨晶圆的中心部分，保留边缘处未研磨晶圆材料的支撑环。这种技术无需使用处理晶圆，就能提供机械支撑。
美国专利号7,776,746提出了超薄晶圆背部处理的方法和装置。如图2所示，装置100含有一个通常是环形结构的外环110，可以由金属或半导体等任意合适的刚性材料制成。外环110可以是任意结构的，最好具有一个矩形剖面，以便于使用带有夹具的装置。外环110的尺寸适合于晶圆140内部。外环110的外径可以是8英寸，以适合6英寸的晶圆放置在其内部。可以附加高温研磨和/或切割带120，或者以其他方式在外环110的底面145上，附着在它周围。切割带120含有一个背部研磨和/或切割带，抵抗金属化等晶圆背部处理引起的发热。外环110为高温切割带120提供支撑机构和刚性支撑。
美国专利号6,162,702提出了一种自支撑的超薄硅晶圆工艺。图3A-3B表示一种成型的超薄硅晶圆的背部和剖面图，用同心圆周晶圆较厚的***边缘之间的空间表示。在该工艺中，使用一个掩膜制备超薄晶圆自支撑的环或栅格。如图3B所示，硅晶圆304具有一个超薄的中心部分，由较厚硅的圆周边缘302支撑。利用传统的移除装置，通过传统的方式，减薄中心部分。作为一种替代方法，利用光致抗蚀剂掩膜或光致抗蚀剂掩膜和硬掩膜的组合，除去中心部分。
美国专利公开号2009/0020854提出了一种制备带有边缘支撑环的超薄晶圆工艺。该工艺提出了一种具有带角度内壁的边缘支撑环，可以与背部研磨工艺后晶圆的超薄中心部分旋转刻蚀兼容。根据旋转刻蚀工艺，在将晶圆装入真空腔用于背部金属化之前，以及背部金属化之前，都无需进行烘干工艺。如图4所示，在旋转刻蚀工艺时的旋转刻蚀化学药品流程的示意图，晶圆80具有一个基本上是非线性带角度的内壁86，从超薄中心部分81的平面开始向上延伸并弯曲，一直到形成在背部89上的边缘支撑环85的顶部88。如图中箭头所示，在旋转刻蚀工艺时，可以从晶圆80开始旋涂化学刻蚀和去离子水。在后续处理过程中，边缘支撑环85有利于对晶圆80减少后的处理和加工。
上述传统方法的好处在于，真空腔中除了半导体晶圆本身以外，没有引入其他材料，因此减少了对排气的担忧。此外，TTV比支撑晶圆的方式更好，并且消耗的成本较低。但遗憾的是，传统的自动晶圆处理***，对于用支撑环移动的超薄晶圆来说，不是必须的，这样可能会损坏晶圆脆弱的超薄部分，从而损伤晶圆。因此，这种晶圆不能像普通晶圆那样处理，而且标准的晶圆处理设备必须通过改造才能用于带有环的特殊结构。
以上所有的原有技术都是关于超薄晶圆处理技术。这些技术都是基于处理“薄晶圆”不是问题的假设基础上。然而，如果晶圆厚度进一步降低，例如降至1密耳甚至更小，减薄后的晶圆极其脆弱，易受损坏，这时处理薄晶圆变成了一个重要问题。在晶圆级和芯片级处理和加工晶圆时，使用较薄的晶圆，损坏晶圆的风险较大。对于垂直传导的半导体，处理薄晶圆更是如此，这是因为背部研磨后还需要在脆弱的超薄晶圆上进行背部处理(例如金属化)。上述方法都不适用于这么薄的晶圆。
正是在这一前提下，提出了本发明的各种实施例。此外，必须提出一种有效的方法，将芯片的正面和背面连接到一个单独平面，以便封装后使用器件。
发明内容
鉴于上述问题，本发明提供了一种垂直传导的功率半导体器件，包括：
一个衬底；一个位于衬底顶面上的顶部金属层；沉积在顶部金属层上方的焊料***焊盘；以及包围着焊料***焊盘的晶圆级模型，并使焊料***焊盘至少部分裸露出来。
上述的器件，焊料***焊盘是通过一个下部的焊盘金属化(UBM)层，连接到顶部金属层上。上述的器件，还包括一个形成在衬底背部的背部金属层。
上述的器件，背部金属层包括一个底部漏极电极，顶部金属层包括源极和栅极电极。
上述的器件，衬底包括一个位于衬底顶端的外延层。上述的器件，其特征在于，衬底的总厚度小于25微米。
上述的器件，衬底包括一个公共漏极，器件包括一个以上的垂直传导的金属氧化物半导体场效应管(MOSFET)。
上述的器件，垂直传导的功率半导体器件包括一个芯片级封装(CSP)。
上述的器件，CSP包括一个或多个用导电材料填充的直通衬底通孔(TSV)，它们将底部电极电连接到器件顶部。上述的器件，其特征在于，模型覆盖了垂直传导的功率半导体器件的背部。
上述的器件，CSP还包括一个用焊料填充的直通衬底通孔(TSV)，该通孔将底部电极电连接到器件顶部。上述的器件，其特征在于，CSP包括沿CSP边缘路由的背部连接。
本发明还提供一种功率器件封装，包括：
一个无衬底的复合功率半导体器件，包括：一个垂直传导的功率半导体器件芯片，该器件芯片在顶面上具有一个顶部金属层；沉积在顶部金属层上方的焊料***焊盘；以及包围着焊料***焊盘的晶圆级模型，其中焊料***焊盘是裸露的；
一个外部导电互联，将器件面向引线框一侧的电极连接到引线框上；以及一个成型混料，将外部导电互联和无衬底的复合功率半导体器件芯片密封成一个封装。
上述的封装，外部导电互联通过焊料***焊盘，电连接到无衬底的复合功率半导体器件的顶端。
上述的封装，外部导电互联由一个源极夹片构成。
上述的封装，无衬底的复合功率半导体器件是一个倒装晶片器件。
上述的封装，外部导电互联贴装到无衬底的复合功率半导体器件的背部。
上述的封装，芯片的厚度小于或等于25微米。
本发明还提供一种用于制备功率半导体器件的方法，包括：
a)制备一个垂直传导的功率半导体器件晶圆，包括一个位于晶圆顶面上的顶部金属层；
b)在顶部金属层上方，制备焊料***焊盘；
c)在焊料***焊盘周围，制备晶圆级模型，使焊料***焊盘通过晶圆级模型的顶部裸露出来；
d)研磨器件晶圆的背部，将器件的半导体材料部分的总厚度减小到最终厚度；并且在晶圆的背面制备一个背部金属。
上述的方法，在焊料***焊盘周围制备晶圆级模型，还包括：共同研磨晶圆级模型和焊料***焊盘的顶部，以便使至少部分焊料***焊盘裸露出来。
上述的方法，最终厚度小于25微米。
上述的方法，还包括：
f)通过在划线处部分切割宽凹槽，在垂直传导的功率半导体器件的背部形成多个凹槽，其中器件晶圆仍然通过晶圆级模型固定在一起；
g)用另一个晶圆级模型填充凹槽；并且
h)切割分成单独的封装。
上述的方法，还包括在步骤c)之前，要在划线处垂直传导的功率半导体器件顶部，形成凹槽，其中所述的研磨晶圆的背部，触及凹槽，并将器件的半导体材料部分分离。
上述的方法，制备垂直传导的功率半导体器件还包括，在半导体材料部分中，形成一个或多个至少部分直通衬底通孔(TSV)，并用导电材料填充TSV，从而最后使TSV将电连接从器件的背面路由至器件的正面。
上述的方法，其中，制备垂直传导的功率半导体器件还包括，制备一个或多个用焊锡填充的至少部分直通衬底通孔(TSV)，从而最后使TSV将电连接从器件的背面路由至器件的正面。
附图说明
参考所附附图，以更加充分的描述本发明的实施例。然而，所附附图仅用于说明和阐述，并不构成对本发明范围的限制。
图1A-1E表示研磨原有技术的晶圆背部工艺的剖面图。
图2表示带有支撑环晶圆的俯视图，用于原有技术的背部处理。
图3A-3B分别表示具有原有技术的自支撑环的超薄晶圆的仰视图和剖面图。
图4表示用于制备原有技术的超薄晶圆的边缘支撑环的剖面图。
图5表示用于原有技术的晶圆背部处理的带有晶圆连接结构的晶圆剖面图。
图6A-6B表示用于原有技术的晶圆背部处理的带有一种可选连接结构的晶圆剖面图。
图7A表示依据本发明的一个实施例，一种功率器件封装的剖面图。
图7B-7C分别表示带有图7A所示封装的晶圆级模型的无衬底复合功率器件芯片的剖面图和俯视图。
图8表示依据本发明的一个可选实施例，一种功率器件封装的剖面图。
图9A-9B分别表示依据本发明的一个实施例，带有晶圆级模型的无衬底公共漏极MOSFET CSP的剖面图和俯视图。
图10A-10B分别表示依据本发明的一个实施例，带有晶圆级模型的无衬底单独的MOSFET CSP的剖面图和俯视图。
图11表示表示依据本发明的一个可选实施例，带有晶圆级模型的无衬底单独的MOSFET CSP的剖面图。
图12A-12K和12L-12P表示依据本发明的一个实施例，制备带有图9A所示类型的晶圆级模型的无衬底公共漏极MOSFET CSP的工艺步骤的剖面图。
图13A-13B表示依据本发明的一个实施例，制备带有图7A所示类型的晶圆级模型的无衬底复合功率器件芯片的第一个和最后一个工艺步骤的剖面图。
图14A-14B表示依据本发明的一个实施例，制备带有图10A所示类型的晶圆级模型的无衬底单独MOSFET CSP的第一个和最后一个工艺步骤的剖面图。
图15A-15B表示依据本发明的一个实施例，制备带有图11所示类型的晶圆级模型的无衬底复合功率器件芯片的第一个和最后一个工艺步骤的剖面图。
图16A-16B表示本发明可选实施例的俯视图和仰视图。
具体实施方式
尽管为了解释说明，以下详细说明包含了许多具体细节，但是本领域的任何技术人员都应理解基于以下细节的多种变化和修正都属本发明的范围。因此，本发明的典型实施例的提出，对于请求保护的发明没有失去任何的一般性，而且不附加任何限制。
对于厚度为1密耳甚至更小的超薄晶圆，最好对器件晶圆/芯片的正面有支撑，以便于晶圆背部处理和晶圆/芯片标准处理。
万国半导体公司已经研发出一种永久的晶圆连接结构，即机械支撑芯片，为最终产品中所含的每个芯片提供来自于器件正面的支撑。冯涛等人于2010年3月30日申请的美国专利申请号12/749,696题为《近乎无衬底的复合功率半导体器件及其方法》的专利中，提出了一种近乎无衬底的复合功率半导体器件(VSLCPSD)。如图5近乎无衬底的复合功率半导体器件的剖面图所示，该器件1具有一种三明治结构，即一个功率半导体器件(PSD)20、一个正面器件载体(FDC)或一个支撑芯片40以及一个由中间连接材料制成的中间连接层(IBL)60。PSD20具有背部衬底部分、带有带图案的正面器件金属垫的正面半导体器件部分，以及减小到近乎消失的厚度TPSD。FDC具有一个带图案的背面载体金属化，为正面器件金属垫、带图案的正面载体金属垫提供电接触，多个并联的直通-载体导电通孔分别将背面载体金属化连接到正面载体金属垫上。减小的厚度TPSD产生很低的背部衬底电阻，直通-载体导电通孔对正面器件金属垫产生很低的正面接触电阻。形成在支撑芯片40中的通孔，使顶部金属化的延伸物穿过支撑芯片40，到达支撑芯片40的正面。通孔中金属的高导电性意味着，支撑芯片40的厚度，不会对器件的电学特性产生负面影响。支撑芯片40大约200微米(8密耳)厚，但是由于PSD20衬底非常薄，以及支撑芯片40的通孔中的金属具有很低的电阻，因此器件的总导通电阻Rdson很低。
也是来自于万国半导体公司的冯涛等人于2010年5月28日申请的美国专利申请号12/790,773题为《带有衬底端裸露的器件端电极的半导体器件及其制备方法》的专利中，提出了一种无衬底的复合功率半导体器件，类似于美国专利申请号12/749,696中所述的器件。图6A表示一种底部源极功率MOSFET的剖面图，该MOSFET具有一个支撑芯片，贴装在半导体器件的正面，与图5所示的近乎无衬底复合功率半导体器件类似。如图6A所示，该器件具有一个三明治结构，即一个功率半导体器件(PSD)34b、一个正面器件载体(FDC)或一个支撑芯片40以及一个由中间连接材料制成的中间连接层(IBL)60。PSD 34b含有一个带有底部漏极金属层22的半导体衬底(SCS)21。SCS 21可以由重掺杂的接触层21a上方的轻掺杂外延漂流层21b构成。衬底沟槽(TST)57已经延伸穿过SCS 21，触及衬底端裸露的器件端栅极电极(SEDGE)56，即使芯片已经倒置安装后(即上下颠倒地安装)，仍然可以从顶面接入栅极电极。图6B表示一种与图6A类似的底部源极功率MOSFET的剖面图，但是用焊料***焊盘95周围的成型混料(或称为塑封材料)90代替支撑芯片40。
在这些技术中，可以通过在连接前，对硅支撑晶圆进行准确地刻蚀，来控制TTV。然而，在支撑晶圆上进行硅通孔(TSV)刻蚀不仅浪费时间，还存在成本问题。
本发明的实施例改进了上述图5和图6A-6B所述方法的基本思路，也就是说，从超薄器件晶圆/芯片的正面提供支撑，以便于晶圆处理/加工以及芯片集成。然而，本发明的实施例使用焊料***焊盘以及晶圆级成型结构的组合，代替晶圆连接，实现了工艺的简化，以及生产成本的大幅降低。此外，本发明的实施例所用的方法也可以与已有的金属夹片连接组装工艺兼容。在本发明的实施例中，晶圆级模型代替了支撑芯片，焊料***焊盘代替了带有更好的导电性的直通通孔。
图7A-7C表示依据本发明的第一实施例，一种无衬底功率器件封装700的不同角度的示意图。如图7A所示，器件封装700含有一个无衬底复合功率器件芯片，其中晶圆级模型(Wafer level molding，或称为晶圆级塑封材料层/体)702贴装在超薄器件芯片706的正面。在本实施例中，芯片706可以是一个底部漏极、垂直传导的功率MOSFET器件。MOSFET的内部结构(例如源极和本体区、栅极结构等)在本领域中已为人们所熟知，在此为了简便不再赘述。位于内部成型混料(Molding compound)702中的焊料***焊盘(Solder bump，或称为焊料凸块)720，该焊料***焊盘720将芯片706的正面电连接到夹片708(例如源极夹片，夹片clip通常为金属夹片)，夹片708通过很薄的焊料层713连接到引线框部分710上。夹片708当然可以用任意适宜的外部(芯片706的外部)导电连线代替。芯片706的背面通过很薄的焊料层714，连接到引线框部分711上。外部成型混料(或称为塑封材料)712可以将芯片706、夹片708以及部分引线框作为一个单独的封装密封。
图7B是无衬底的功率器件封装700内部的放大视图。如图7B所示，芯片706含有一个底部金属722，底部金属722可以电连接到芯片706的底部漏极、位于底部金属722上方的重掺杂衬底724以及位于衬底724上方的轻掺杂外延漂流层/漂移层726。在本说明中，“衬底”也可以认为是半导体材料，例如重掺杂衬底724以及轻掺杂外延层726。重掺杂衬底724和外延层726的总厚度小于50微米，或者甚至小于25微米。衬底如此之薄，这种器件就可以认为是近乎“无衬底”。外延层726的厚度约为几微米，通常是4-5微米。芯片706也含有顶部金属728，顶部金属728含有一个分立的源极电极和栅极电极，位于外延漂流层726上方。顶部金属728被分成不同的源极和栅极金属区，源极和栅极金属区通过钝化层704相互电绝缘。焊料***焊盘720以及由可焊接金属制成的可选的凸点下金属化(Under bump metallization，简称UBM)层730，可以形成在顶部金属728上的所选位置处，例如如图7C的俯视图所示。如果顶部金属728是一种不可焊接金属(例如铝金属)，那么可以使用UBM层730。可焊接的UBM层730可以形成在顶部金属728上方，以便于制备焊料***焊盘。UBM层通常可以包括镍(Ni)、金(Au)或铜(Cu)。
晶圆级模型702沉积在焊料***焊盘720之间的结构上方。作为示例，不作为局限，晶圆级模型的厚度可以大于150微米。晶圆级模型702可以由成型混料制成。成型混料702和芯片706之间的热失配不应过大，以避免晶圆扭曲变形。对于指定的工艺，热失配的度数可以由实验决定。作为示例，但不作为局限，晶圆级模型702所用的材料包括模制粉、硅凝胶、模制环氧树脂、高温聚合物、环氧树脂、密封剂或另一种成型混料。参见图7A，一个附加的外部成型混料712包围在功率器件封装700的内部。
图8所示的示意图，表示依据本发明的第二实施例，一种无衬底功率器件封装800的剖面图。与图7A所示的封装700类似，器件封装800含有一个无衬底的复合功率器件芯片，带有晶圆级模型702贴装在超薄器件芯片806的顶部。在本实施例中，芯片806可以是倒装芯片功率MOSFET器件，倒装安装在封装中，也就是说，与图7A的芯片706相比，它是倒置安装在引线框811上的。焊料***焊盘720将晶圆/芯片806的正面电连接到引线框811上。晶圆/芯片806的背面通过一个很薄的焊锡层814连接到夹片808上(例如漏极夹片)，夹片808通过很薄的焊锡层813连接到引线框811的810部分。引线框811可以与引线框上的倒装芯片(FCOL)封装兼容。成型混料712可以作为一个单独的封装密封整个结构。
芯片806的详细结构类似于图7B所示的芯片706。带有封装800的晶圆级模型的无衬底复合功率器件芯片的正视图类似于封装700。
在本发明的第三实施例中，图7A和图8所示类型的无衬底功率器件封装结构可用于无衬底的公共漏极双MOSFET芯片级封装(CSP)。图9A表示带有晶圆级模型902的无衬底的公共漏极双MOSFET CSP 900的剖面图。双MOSFET CSP 900含有两个在半导体晶片906中的MOSFET。与图7B所示的垂直MOSFET 706类似，每个公共漏极MOSFET CSP 900的垂直MOSFET都含有一个公共底部金属922、一个位于底部漏极金属922上方的重掺杂衬底724、一个位于重掺杂衬底724上方的轻掺杂外延漂流层726以及顶部金属728，顶部金属728包括源极电极和栅极电极，位于外延漂流层726上方，并且通过UBM层730，连接到焊料***焊盘720上。每个器件的所有层的总厚度类似于图7B所示的器件706。在本实施例中，底部金属922为所有形成在无衬底公共漏极MOSFET CSP 900中的MOSFET器件提供公共漏极金属。衬底724和外延层726构成公共漏极的一部分。晶圆级模型902密封了整个无衬底公共漏极MOSFET CSP 900。图9B为带有晶圆级模型902的无衬底公共漏极MOSFET CSP 900的正视图，表示两个相邻的器件。作为示例，图9A可以是图9B沿C-C线的剖面图。尽管，为了解释说明，仅表示出了两个器件，但是本领域的技术人员应明确，通过合适的布局，可以在一个芯片上制备多个器件。在本图中，公共漏极并没有表示成可连接的；当然，如果需要的话，可以裸露出背部金属922，以便连接漏极。
在本发明的第四实施例中，图7A和8A所示类型的无衬底功率器件封装结构也可用于无衬底的单独的MOSFET芯片级封装(CSP)。图10A表示带有晶圆级模型1002的无衬底的单独的MOSFET CSP 1000的剖面图。无衬底的单独的MOSFET CSP 1000含有一个底部金属722(可以是底部漏极金属)、一个位于底部金属722上方的重掺杂衬底724、一个位于衬底724上方的轻掺杂的外延漂流层726以及顶部金属728，顶部金属728包括源极电极和栅极电极，位于外延漂流层726上方。如图10A所示，顶部电极728可以通过UBM层730，连接到焊料***焊盘920上。器件1000中所有层的总厚度类似于图7B所示的器件706。在本实施例中，制备直通衬底通孔(TSV)1004，穿过衬底724和外延层726。对于单独的TSV 1004而言，它的直径约为1微米甚至更大。如果有一个以上的TSV 1004，那么每个的直径可能更小。可以用钨(W)或铜(Cu)等导电金属填充TSV 1004，TSV 1004将背部金属722与CSP的正面连接起来。TSV 1004可以通过顶部金属层728的729部分以及UBM材料730，电连接到焊料***焊盘922上。晶圆级模型1002可以密封整个无衬底的单独的MOSFET CSP 1000。在本实施例中，对于漏极连接，无需将TSV与正面垫绝缘，因为衬底就是漏极。当然，如果有必要的话，绝缘材料可以内衬在TSV中，以便沿TSV的侧壁，将TSV中的导电材料与半导体材料绝缘。
图10B表示带有晶圆级模型1002的无衬底的单独的MOSFET CSP 1000的正视图，该MOSFET CSP 1000含有源极焊料***焊盘920、漏极焊料***焊盘922以及栅极焊料***焊盘924。要注意的是，图10A中的剖面取自图10B沿C-C线。由于通过TSV 1004，背面可一直向上到达正面，因此所有的器件电极(例如源极、栅极和漏极)都可以从器件的正面连接。
图11表示依据本发明的第五实施例，带有晶圆级模型1102的可选无衬底的单独的MOSFET CSP 1100的剖面图。CSP 1100的层结构除了仅形成一个很大的TSV 1104穿过衬底724以及外延层726之外，其他都与图10A中的CSP 1000类似。TSV 1104的直径约为5-20微米。焊锡材料可以填充在TSV 1104中，以便将背部金属722与CSP1100相连接，并且在TSV 1104上方形成漏极焊料***焊盘922。作为示例，金属层1106和UBM层1108可以形成在TSV 1104的侧壁上，金属层1106邻近衬底724和外延层726，UBM层1108邻近TSV 1104内的焊锡。晶圆级模型1102可以密封整个无衬底的单独的MOSFET CSP 1100。由于背部金属含有钛、镍和银的合金(TiNiAg)等可焊接的材料，因此焊锡可以直接沉积在通孔中的背部金属上方。
依据本发明的实施例，图12A-12K和12L-12P表示用于制备图9A-9B所示类型的带有晶圆级模型的无衬底MOSFET CSP的工艺流程的示例。该工艺从具有全厚度(例如初始厚度ti约为750微米)晶圆的功率MOSFET开始。图12A为CSP的剖面图，该CSP与图9B所示的类型沿A-A线类似，为了非限制性示例，图9B表示的是两个邻近的器件。如图所示，顶部金属层1206含有源极和栅极电极，位于公共外延层1204上，外延层1204位于公共衬底1202上。通过氮化物或氧化物等钝化材料1208，金属层1206部分可以相互绝缘。
如图12B所示，UBM层1210可以形成在金属层1206上方，在钝化材料1208中的开口处。作为示例，如图12C所示，可以预先将衬底1020的背部研磨到预设厚度tp，例如500微米。如图12D所示，在接合材料1210上方，形成***1212，最好是焊料***焊盘。如图12E所示，晶圆级模型1214可以形成在焊料***焊盘1212上方。如图12F所示，晶圆级模型1214的顶部和焊料***焊盘向下研磨，使焊料***焊盘1212裸露出来。
然后，如图12G所示，将衬底1202的背部再次向下研磨，以减小衬底厚度，使衬底1202和外延层1204的总厚度非常小，例如小于25微米。如图12H所示，薄金属层1216，例如TiNiAg或任意其他金属，形成在衬底1202的背部。
如图12I所示，穿过金属层1216、衬底1202、外延层1204以及钝化层1208，在划线处用宽切割刀片切割，使凹槽1218形成在结构的背面，从而将半导体材料分离，但是晶圆级模型1214仍然将晶圆保持在一起。凹槽1218的宽度最好大于25微米。然后，如图12J所示，晶圆级模型1220可以填充在凹槽1218中，并且覆盖晶圆的边缘和背部。可以将晶圆分成单独的无衬底公共漏极，如图12K所示，可以用较薄的切割刀片，沿划线切割该结构，分离带有晶圆级模型的MOSFET CSP。
还可选择，为了使晶圆的扭曲最小，如图12D所示，在形成焊料***焊盘之后，可以额外进行制备凹槽1213的工艺。如图12L所示，在图12D所示的工艺之后，可以通过穿过外延层1204和重掺杂衬底层1202的顶部，在晶圆的划线处部分切割，形成凹槽1213。凹槽1213的直径可以大于25微米。图12E-12H所示的步骤可以用图12M-12P所示的可选工艺代替。
如图12M所示，晶圆级模型1214形成在焊料***焊盘1212上方以及凹槽1213内部。如图12N所示，可以研磨晶圆级模型1214和焊料***焊盘1212的顶部，使焊料***焊盘1212裸露出来。然后，如图12O所示，可以再次向下研磨衬底1202的背部，以减小厚度，从而使衬底1202和外延层1204的总厚度小于25微米。这个背部研磨工艺通过触及凹槽1213，也将单独芯片的半导体部分(即衬底1202和外延层1204)相互分开，然而它们仍然被晶圆级模型1214固定在合适的位置上。如图12P所示，薄金属层1216可以形成在衬底1202的背部。然后，继续进行与图12J-12K所示的相同步骤，包括在带有晶圆级模型1220的晶圆背部制备一个涂层，并通过穿过凹槽1218切割该结构，将带有晶圆级模型的单独的无衬底公共漏极MOSFET CSP分离。还可选择，裸露背部金属层1216。
依据本发明的另一个实施例，制备图7A-7C和图8所示类型的带有晶圆级模型的无衬底复合功率器件芯片的工艺流程，与图12A-12K所示的工艺流程基本类似。该工艺从一个晶圆开始，包括多个带有全厚度晶圆(例如厚度约为750微米)的无衬底复合功率MOSFET器件。
图13A表示图7C所示类型的一种功率MOSFET器件沿B-B线的剖面图。如图所示，顶部金属层可以分成一个第一部分1306(可能是一个源极电极)以及一个第二部分1308(可能是一个栅极电极)。顶部金属层的第一和第二部分位于一个公共外延层1204上，外延层1204位于一个公共(重掺杂的)衬底1202上。通过钝化层1310，金属层部分1306、1308相互绝缘。该工艺的下一个步骤类似于图12B-12H所示的工艺。图13B表示无衬底的复合功率MOSFET器件的剖面图，该MOSFET器件的衬底1202和外延层1204的总厚度小于25微米，焊料***焊盘1212沉积在UBM层1210上方，晶圆级模型1214形成在焊料***焊盘1212上方，并且研磨它，使焊料***焊盘裸露出来，金属层1216沉积在衬底1202的背部。通过切割划线处的晶圆，使单独的无衬底复合功率MOSFET器件相互分开。对于已有的硅芯片而言，图13B所示的最终结构可以与金属夹片接合封装兼容。然后，利用一个金属夹片，将单独的无衬底复合功率MOSFET器件安装在功率半导体封装中的引线框上，如图7A和8A所示，源极夹片或漏极夹片当中的任何一个，将面向外部的电极连接到一部分引线框上。还可选择，利用接合引线、导电带或其他导电互连，将芯片面向外部的一侧连接到引线框上。
制备类似于图10A-10B所示类型的带有晶圆级模型的无衬底单-的MOSFET CSP的工艺流程，与图12A-12K所示的工艺流程基本类似。该工艺从一个晶圆开始，包括多个带有全厚度晶圆(例如厚度约为750微米)的无衬底单一的功率MOSFET器件，以及一部分TSV内衬有穿过外延层和衬底顶部形成的金属。图14A表示图10B所示类型的一种功率MOSFET器件沿C-C线的剖面图。如图所示，第一顶部金属层部分1406(可以是一个源极电极)以及一个第二顶部金属层部分1408(可以是一个栅极电极)，位于一个公共外延层1204上，外延层1204位于一个公共衬底1202上。通过钝化材料1410，金属层部分1406、1408相互绝缘。TSV 1412可以穿过外延层1204和衬底1202的顶部形成，并用金属填充。TSV 1412的深度大于外延层1204和衬底1202的最终总厚度，因此，TSV 1412在最后的背部掩膜过程后，将裸露出来。TSV 1412可以连接到背部金属层1216上，背部金属层1216可以是底部漏极金属。该工艺的其他步骤与图12B-12K所示的步骤类似。通过切割划线处的晶圆(图中没有表示出)，使单独的无衬底单一的MOSFET CSP相互分开。图14B表示无衬底单一的MOSFET CSP的剖面图，其中衬底1202和外延层1204的总厚度非常薄，例如小于25微米。CSP还包括沉积在UBM层1210上方的焊料***焊盘1212、沉积在衬底1202背部的金属层1216、形成在TSV1412上方的金属垫1408上方的焊料***焊盘1213以及形成在焊料***焊盘1212、1213上方的晶圆级模型1214，并且回刻晶圆级模型1214，使焊料***焊盘裸露出来。晶圆级模型1214也可以覆盖芯片的背部和边缘。
制备图11所示类型的带有晶圆级模型的无衬底单一的MOSFET CSP的一种可选的工艺流程，与图12A-12K所示的工艺流程基本类似。该工艺从一个晶圆开始，包括多个带有全晶圆厚度(例如厚度约为750微米)的无衬底单一的功率MOSFET器件，以及一个很宽的部分TSV穿过外延层和衬底顶部形成，一个金属层内衬在TSV的底部和侧壁。图15A表示图11所示类型的功率MOSFET器件的剖面图。如图所示，顶部金属层1506作为一个源极电极，位于公共外延层1204上，公共外延层1204位于公共衬底1202上。所形成的TSV 1512部分穿过衬底。TSV 1512的侧壁和底部可以用金属层1508覆盖。通过钝化材料1510，金属层1506、1508可以相互绝缘。TSV 1512的深度大于外延层1204和衬底1202的最终总厚度，以便在最后的背部研磨步骤后，将TSV 1512裸露出来，并且连接到背部金属层1216上，背部金属层1216作为底部漏极电极。该工艺的其他步骤与图12B-12K所示的步骤类似。然而，在TSV 1512内填充焊锡。背部研磨使TSV的底部裸露出来。通过切割划线处的结构(图中没有表示出)，使单独的无衬底单一的MOSFET CSP相互分开。图15B表示无衬底单一的MOSFET CSP的剖面图，该MOSFET CSP的衬底1202和外延层1204的总厚度超薄，例如小于25微米。焊料***焊盘1212沉积在UBM层1210上方，UBM层1210连接到金属层1506上。在本实施例中，UBM层1211形成在TSV 1512的侧壁上，焊锡填充在TSV 1512中，构成焊料***焊盘1213和背部金属层1216之间的接头。背部研磨之前，晶圆级模型1214形成在焊料***焊盘1212和1213上方，使焊料***焊盘裸露出来；晶圆级模型也可以覆盖芯片的背部和边缘。
在另一个实施例中，本发明可用于晶圆级CSP，其中芯片背部的电接触一直延伸到芯片外部的芯片正面。发明人冯涛于2008年1月31日递交的美国专利申请公开号为2009/0194880A1，美国申请号为12/023,921的专利中提出的一种用于制备该器件的技术，特此引用其内容以作参考。图16A和16B分别表示本发明的一个实施例，将芯片背面的连接路由到芯片正面的底部和顶部透视图。在这种情况下，到背部金属1616的连接沿芯片边缘的再路由路径1603，电路由到正面再路由电极1605；即沿CSP边缘的再路由路径(Re-routing paths)1603将相当于芯片背面/背部连接的背部金属1616电连接到CSP正面的再路由电极(Re-routing electrodes)1605。通过其他的实施例，正面电极也可以含有源极电极1612和栅极电极1613，它们都由晶圆级模型1614装入的焊料***焊盘构成，依据本发明，半导体衬底可以背部刻蚀得超薄。在这种情况下，可以通过在未切割晶圆的边缘或拐角处制备通孔，形成再路由通路1603，然后用金属等导电材料内衬通孔。还可选择，首先在通孔中沉积绝缘材料，使通孔中的导电材料与半导体衬底绝缘。切割后，通孔变成内衬导电材料的切口，从而形成再路由通路1603。
除非特别声明，否则本说明所提及的所有可选件(包括任何附加的权利要求、摘要及附图)，都可以用用作同样、等效或类似目的的可选件代替。因此，除非特别声明，否则，每个所提及的可选件都仅是普通的一系列等效或类似可选件的一个示例。任何可选件(无论首选与否)，都可与其他任何可选件(无论首选与否)组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能，否则所附的权利要求书中的任何部分都不应认为是本申请所引述的文献或者其他任何相关或相近文档中所记载的“方法”或“步骤”的条款所构成的限制。尤其是权利要求书中“的步骤”的使用并不应认为引自任何其他文献。
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Claims (25)

1.一种垂直传导的功率半导体器件，其特征在于，包括：
一个衬底；
一个位于衬底顶面上的顶部金属层；
沉积在顶部金属层上方的焊料***焊盘；以及
包围着焊料***焊盘的晶圆级模型，并使焊料***焊盘至少部分裸露出来。
2.如权利要求1所述的器件，其特征在于，焊料***焊盘是通过一个下部的焊盘金属化(UBM)层，连接到顶部金属层上。
3.如权利要求1所述的器件，其特征在于，还包括一个形成在衬底背部的背部金属层。
4.如权利要求3所述的器件，其特征在于，背部金属层包括一个底部漏极电极，顶部金属层包括源极和栅极电极。
5.如权利要求1所述的器件，其特征在于，衬底包括一个位于衬底顶端的外延层。
6.如权利要求1所述的器件，其特征在于，衬底的总厚度小于25微米。
7.如权利要求1所述的器件，其特征在于，衬底包括一个公共漏极，器件包括一个以上的垂直传导的金属氧化物半导体场效应管(MOSFET)。
8.如权利要求1所述的器件，其特征在于，垂直传导的功率半导体器件包括一个芯片级封装(CSP)。
9.如权利要求8所述的器件，其特征在于，CSP包括一个或多个用导电材料填充的直通衬底通孔(TSV)，它们将底部电极电连接到器件顶部。
10.如权利要求9所述的器件，其特征在于，模型覆盖了垂直传导的功率半导体器件的背部。
11.如权利要求8所述的器件，其特征在于，CSP还包括一个用焊料填充的直通衬底通孔(TSV)，该通孔将底部电极电连接到器件顶部。
12.如权利要求11所述的器件，其特征在于，CSP包括沿CSP边缘路由的背部连接。
13.一种功率器件封装，其特征在于，包括：
一个无衬底的复合功率半导体器件，包括：
一个垂直传导的功率半导体器件芯片，该器件芯片在顶面上具有一个顶部金属层；
沉积在顶部金属层上方的焊料***焊盘；以及
包围着焊料***焊盘的晶圆级模型，其中焊料***焊盘是裸露的；
一个外部导电互联，将器件面向引线框一侧的电极连接到引线框上；以及
一个成型混料，将外部导电互联和无衬底的复合功率半导体器件芯片密封成一个封装。
14.如权利要求13所述的封装，其特征在于，外部导电互联通过焊料***焊盘，电连接到无衬底的复合功率半导体器件的顶端。
15.如权利要求14所述的封装，其特征在于，外部导电互联由一个源极夹片构成。
16.如权利要求13所述的封装，其特征在于，无衬底的复合功率半导体器件是一个倒装晶片器件。
17.如权利要求16所述的封装，其特征在于，外部导电互联贴装到无衬底的复合功率半导体器件的背部。
18.如权利要求13所述的封装，其特征在于，芯片的厚度小于或等于25微米。
19.一种用于制备功率半导体器件的方法，其特征在于，包括：
a)制备一个垂直传导的功率半导体器件晶圆，包括一个位于晶圆顶面上的顶部金属层；
b)在顶部金属层上方，制备焊料***焊盘；
c)在焊料***焊盘周围，制备晶圆级模型，使焊料***焊盘通过晶圆级模型的顶部裸露出来；
d)研磨器件晶圆的背部，将器件的半导体材料部分的总厚度减小到最终厚度；并且在晶圆的背面制备一个背部金属。
20.如权利要求19所述的方法，其特征在于，在焊料***焊盘周围制备晶圆级模型，还包括：共同研磨晶圆级模型和焊料***焊盘的顶部，以便使至少部分焊料***焊盘裸露出来。
21.如权利要求19所述的方法，其特征在于，最终厚度小于25微米。
22.如权利要求19所述的方法，其特征在于，还包括：
f)通过在划线处部分切割宽凹槽，在垂直传导的功率半导体器件的背部形成多个凹槽，其中器件晶圆仍然通过晶圆级模型固定在一起；
g)用另一个晶圆级模型填充凹槽；并且
h)切割分成单独的封装。
23.如权利要求19所述的方法，其特征在于，还包括在步骤c)之前，要在划线处垂直传导的功率半导体器件顶部，形成凹槽，其中所述的研磨晶圆的背部，触及凹槽，并将器件的半导体材料部分分离。
24.如权利要求19所述的方法，其特征在于，制备垂直传导的功率半导体器件还包括，在半导体材料部分中，形成一个或多个至少部分直通衬底通孔(TSV)，并用导电材料填充TSV，从而最后使TSV将电连接从器件的背面路由至器件的正面。
25.如权利要求19所述的方法，其特征在于，制备垂直传导的功率半导体器件还包括，制备一个或多个用焊锡填充的至少部分直通衬底通孔(TSV)，从而最后使TSV将电连接从器件的背面路由至器件的正面。
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