CN102456615B - Manufacturing process of removing metal layer redundancy metal filling - Google Patents
Manufacturing process of removing metal layer redundancy metal filling Download PDFInfo
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- CN102456615B CN102456615B CN201110285102.9A CN201110285102A CN102456615B CN 102456615 B CN102456615 B CN 102456615B CN 201110285102 A CN201110285102 A CN 201110285102A CN 102456615 B CN102456615 B CN 102456615B
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Abstract
The invention provides a manufacturing process of removing a metal layer redundancy metal filling. The process has the following steps: 1) depositing a dielectric layer with a low k value; 2) forming an etching barrier layer on the deposited dielectric layer with the low k value; 3) completing photolithography and etching so as to remove the etching barrier layer in a non-redundant metal area; 4) depositing again the low k value medium so as to reach low-k-value dielectric layer with a required thickness; 5) completing the photolithography and the etching so as to form a through hole; 6) performing again the photolithography and the etching so as to form a metallic channel and a redundancy metal trough; 7) carrying out filling of lead metal, through hole metal and redundancy metal and completing metal layer deposition; 8) carrying out chemical mechanical planarization to the metal layer; 9) continuously carrying out chemical mechanical planarization to the low-k-value dielectric layer and a metal mixing layer and further removing the redundancy metal. In the invention, through a technology of further removing the redundancy metal by using the chemical mechanical planarization during making single damascene and dual damascene interconnection, coupling capacitance in and between the metal layers caused by the redundancy metal filling can be effectively reduced or eliminated. The process is suitable for practical usage.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, particularly relate to a kind of manufacturing process of removing redundant metal filling of metal layer.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled.After entering into 130 nm technology node, be subject to the restriction of the high-ohmic of aluminium, copper-connection gradually substitution of Al interconnection becomes the metal interconnected main flow that obtains.Due to difficult realization of dry etch process of copper, the manufacture method of copper conductor can not obtain by etching sheet metal as aluminum conductor.The manufacture method of the copper conductor extensively adopting is now the embedding technique that is called Damascus technics.First this technique deposit low k value dielectric layer on silicon chip, then by photoetching be etched in dielectric layer and form metallic channel, continues follow-up metal level deposition and metal level cmp and make plain conductor.This technique comprises single Damascus technics of only making plain conductor and the dual damascene process of simultaneously making contact hole and plain conductor.
In Damascus technics, use final formation of metal level cmp and be embedded in the plain conductor in dielectric layer.In order to reach uniform grinding effect, require the metallic pattern density on silicon chip even as far as possible.And the metallic pattern density of product design usually can not meet the requirement of the cmp uniformity.The method solving is at the white space of domain, to fill redundancy metal to make domain pattern density homogenizing.Redundancy metal has improved the uniformity of pattern density, but has inevitably introduced extra intermetallic coupling capacitance.In order to reduce extra coupling capacitance, bring the negative effect of device, when design redundancy metal is filled, will reduce as far as possible the filling quantity of redundancy metal.
Electric capacity can be calculated by following formula:
Wherein, ε
0for permittivity of vacuum; ε
rfor medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.From above-mentioned formula, reduce the relative area of metal and increase intermetallic apart from reducing electric capacity.That is to say, the volume that reduces redundancy metal can reduce the extra intermetallic coupling capacitance of introducing owing to adding redundancy metal.
The patent No. is the manufacture method that the Chinese patent of CN101752298A relates to a kind of metal interconnect structure, comprise: Semiconductor substrate is provided, in described Semiconductor substrate, have dual damascene opening in intermetallic dielectric layer, intermetallic dielectric layer, be covered in barrier layer on described intermetallic dielectric layer and the metal level on barrier layer, described metal level is filled in dual damascene opening; Described in planarization, the surface of intermetallic dielectric layer is to form metal interconnecting layer; On described metal interconnecting layer, form the first etching stop layer; By flatening process, remove described the first etching stop layer; On metal interconnecting layer remove described the first etching stop layer by flatening process after, form the passivation layer on the second etching stop layer, the second etching stop layer and be embedded in the soldering pad layer in described passivation layer, described soldering pad layer is positioned on described metal interconnecting layer.Described method can avoid the circuit being caused by the metal protuberance of metal interconnecting layer to connect defect, improves the reliability of semiconductor device.
The patent No. is the manufacture method that the Chinese patent of CN101740479A relates to a kind of semiconductor device, comprise: Semiconductor substrate is provided, described in planarization, the surface of Semiconductor substrate is to form metal interconnecting layer, and described planarization at least comprises: remove the excess metal outside described dual damascene opening; Remove the barrier layer outside described dual damascene opening; In Semiconductor substrate after planarization, form the passivation layer on etching stop layer, etching stop layer and be embedded in the soldering pad layer in described passivation layer, described soldering pad layer is positioned on described metal interconnecting layer; Before removing the barrier layer outside described dual damascene opening, also comprise: the equipment that described Semiconductor substrate is placed in to the described etching stop layer of formation carries out heat treated, and the temperature of described heat treated is more than or equal to the temperature of follow-up arbitrary technique.Adopt the manufacture method of described semiconductor device, can avoid the oxidized erosion and form corrosion default in rear-end cleaning process of these projections, improve the reliability of device.
In order effectively to reduce or eliminate redundancy metal, fill in the metal level of introducing and the coupling capacitance of metal interlevel, the invention provides the manufacturing process of a kind of attenuate or removal redundant metal filling of metal layer.Preferred embodiment provided by the present invention and that as just example but invention is construed as limiting embodies to some extent in embodiment.
Summary of the invention
In view of the above problems, the object of the present invention is to provide the manufacturing process of a kind of attenuate or removal redundant metal filling of metal layer.The present invention proposes that a kind of single Damascus and dual damascene are metal interconnected middlely to be utilized the further attenuate of cmp or remove completely than the technique of the redundancy metal of wire metal foil making.The present invention, by removing redundant metal filling of metal layer, can effectively reduce or eliminate redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
The object of the invention to solve the technical problems realizes by the following technical solutions.
A kind of manufacturing process of removing redundant metal filling of metal layer that the present invention proposes, its processing step is as follows:
1) deposit low k value dielectric layer;
2) on the low k value dielectric layer of deposition, form etching barrier layer;
3) complete the etching barrier layer that photoetching and etching are removed nonredundancy metallic region;
4) again deposit the low k value dielectric layer that low k value medium reaches desired thickness;
5) complete photoetching and etching and form through hole;
6) photoetching and etching form metallic channel and redundancy metal groove again;
7) carry out the filling of wire metal, via metal and redundancy metal, complete metal level deposition;
8) metal level is carried out to cmp;
9) continue cmp low k value dielectric layer and metal mixed layer, further remove redundancy metal.
Described etching barrier layer, its material is carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide.
Described etching barrier layer, its thickness range is between 1 nanometer to 1000 nanometer.
The object of the invention to solve the technical problems can also obtain further realizing by the following technical solutions.
The manufacturing process of described removal redundant metal filling of metal layer, after step (4) completes, at etching barrier layer deposited hard mask layer, complete again photoetching and etching and form hard mask metallic channel and hard mask redundancy metal groove, carry out photoetching and etching and form through hole, continue etching, remove residue hard mask layer, form metallic channel and redundancy metal groove.
The manufacturing process of described removal redundant metal filling of metal layer, redundancy metal groove is more shallow than metallic channel.
This method the present invention, by removing redundant metal filling of metal layer, can effectively reduce or eliminate redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.Yet appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Fig. 1 illustrates the profile of low k value dielectric layer and etching barrier layer.
Fig. 2 has illustrated the profile of the etching barrier layer of photoetching and etching removal nonredundancy metallic region.
Fig. 3 has illustrated low k value dielectric layer post-depositional profile again.
Fig. 4 has illustrated the profile of photoetching and etching formation through hole.
Fig. 5 illustrates the profile of low k value dielectric layer, etching barrier layer and hard mask layer.
Fig. 6 has illustrated the profile that photoetching and etching form hard mask metallic channel and hard mask redundancy metal groove.
Fig. 7 has illustrated the profile of photoetching and etching formation through hole.
Fig. 8 has illustrated the profile of photoetching and etching formation metallic channel, through hole and redundancy metal groove.
Fig. 9 has illustrated wire metal after metal level deposition and metal level cmp, via metal and redundancy metal filling profile.
Figure 10 illustrates continuation cmp and further removes redundancy metal filling profile.
Reference numeral: 1. low k value dielectric layer, 2. etching barrier layer, 3. through hole, 4. hard mask layer, 5. hard mask metallic channel, 6. hard mask redundancy metal groove, 7. metallic channel, 8. redundancy metal groove, 9. via metal, 10. wire metal, 11. redundancy metals.
Embodiment
For further setting forth the present invention, reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, the manufacturing process to the removal redundant metal filling of metal layer proposing according to the present invention, is described in detail as follows.
Different embodiments of the invention will details are as follows, to implement different technical characterictic of the present invention, will be understood that, the unit of the specific embodiment of the following stated and configuration are in order to simplify the present invention, and it is not only for example limits the scope of the invention.
A kind of manufacturing process of removing redundant metal filling of metal layer that the present invention proposes, its processing step is as follows:
1) deposit low k value dielectric layer;
2) on the low k value dielectric layer of deposition, form etching barrier layer;
3) complete the etching barrier layer that photoetching and etching are removed nonredundancy metallic region;
4) again deposit the low k value dielectric layer that low k value medium reaches desired thickness;
5) complete photoetching and etching and form through hole;
6) photoetching and etching form metallic channel and redundancy metal groove again;
7) carry out the filling of wire metal, via metal and redundancy metal, complete metal level deposition;
8) metal level is carried out to cmp;
9) continue cmp low k value dielectric layer and metal mixed layer, further remove redundancy metal.
Wherein the material of etching barrier layer is carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, and its thickness range is between 1 nanometer to 1000 nanometer.
First deposit after low k value dielectric layer, on the low k value dielectric layer of deposition, form etching barrier layer, Fig. 1 illustrates the profile of low k value dielectric layer and etching barrier layer.Complete photoetching and etching and remove the etching barrier layer of nonredundancy metallic region, Fig. 2 has illustrated the profile of the etching barrier layer of photoetching and etching removal nonredundancy metallic region.Again deposit low k value medium, make its low k value dielectric layer that reaches desired thickness, Fig. 3 has illustrated low k value dielectric layer post-depositional profile again.Complete photoetching and etching and form through hole, Fig. 4 has illustrated the profile of photoetching and etching formation through hole.Photoetching and etching form metallic channel and redundancy metal groove again, and Fig. 8 has illustrated the profile of photoetching and etching formation metallic channel, through hole and redundancy metal groove.Carry out the filling of wire metal, via metal and redundancy metal, complete metal level deposition, again metal level is carried out to cmp, Fig. 9 has illustrated wire metal after metal level deposition and metal level cmp, via metal and redundancy metal filling profile.Continue cmp low k value dielectric layer and metal mixed layer, further remove redundancy metal.Figure 10 illustrates continuation cmp and further removes redundancy metal filling profile.
Object of the present invention can also be implemented with another kind of embodiment.
A kind of manufacturing process of removing redundant metal filling of metal layer that the present invention proposes, its processing step is as follows:
1) deposit low k value dielectric layer;
2) on the low k value dielectric layer of deposition, form etching barrier layer;
3) complete the etching barrier layer that photoetching and etching are removed nonredundancy metallic region;
4) again deposit the low k value dielectric layer that low k value medium reaches desired thickness;
5) complete deposited hard mask layer;
6) complete photoetching and etching and form hard mask metallic channel and hard mask redundancy metal groove;
7) complete photoetching and etching and form through hole;
8) continue etching, remove residue hard mask layer, form metallic channel and redundancy metal groove;
9) carry out the filling of wire metal, via metal and redundancy metal, complete metal level deposition;
10) metal level is carried out to cmp;
11) continue cmp low k value dielectric layer and metal mixed layer, further remove redundancy metal.
Wherein the material of etching barrier layer is carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, and its thickness range is between 1 nanometer to 1000 nanometer.
First deposit after low k value dielectric layer, on the low k value dielectric layer of deposition, form etching barrier layer, Fig. 1 illustrates the profile of low k value dielectric layer and etching barrier layer.Complete photoetching and etching and remove the etching barrier layer of nonredundancy metallic region, Fig. 2 has illustrated the profile of the etching barrier layer of photoetching and etching removal nonredundancy metallic region.Again deposit low k value medium, make its low k value dielectric layer that reaches desired thickness, Fig. 3 has illustrated low k value dielectric layer post-depositional profile again.Complete subsequently deposited hard mask layer, Fig. 5 illustrates the profile of low k value dielectric layer, etching barrier layer and hard mask layer.Carry out photoetching and etching again and form hard mask metallic channel and hard mask redundancy metal groove, Fig. 6 has illustrated the profile that photoetching and etching form hard mask metallic channel and hard mask redundancy metal groove.Complete photoetching and etching and form through hole, Fig. 7 has illustrated the profile of photoetching and etching formation through hole.Photoetching and etching form metallic channel and redundancy metal groove again, and Fig. 8 has illustrated the profile of photoetching and etching formation metallic channel, through hole and redundancy metal groove.Carry out the filling of wire metal, via metal and redundancy metal, complete metal level deposition, again metal level is carried out to cmp, Fig. 9 has illustrated wire metal after metal level deposition and metal level cmp, via metal and redundancy metal filling profile.Continue cmp low k value dielectric layer and metal mixed layer, further remove redundancy metal.Figure 10 illustrates continuation cmp and further removes redundancy metal filling profile.
This method is being made single Damascus and the metal interconnected middle technique of utilizing cmp further to remove redundancy metal of dual damascene by a kind of, can effectively reduce or eliminate redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (5)
1. a manufacturing process of removing redundant metal filling of metal layer, is characterized in that, its processing step is as follows:
1) deposit low k value dielectric layer;
2) on the low k value dielectric layer of deposition, form etching barrier layer;
3) complete the etching barrier layer that photoetching and etching are removed nonredundancy metallic region;
4) again deposit the low k value dielectric layer that low k value medium reaches desired thickness;
5) complete photoetching and etching and form through hole;
6) photoetching and etching form metallic channel and redundancy metal groove again;
7) carry out the filling of wire metal, via metal and redundancy metal, complete metal level deposition;
8) metal level is carried out to cmp;
9) continue cmp low k value dielectric layer and metal mixed layer, further remove redundancy metal.
2. a kind of manufacturing process of removing redundant metal filling of metal layer as claimed in claim 1, is characterized in that, the material of described etching barrier layer is carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide.
3. a kind of manufacturing process of removing redundant metal filling of metal layer as claimed in claim 1, is characterized in that, the thickness range of described etching barrier layer is between 1 nanometer to 1000 nanometer.
4. a kind of manufacturing process of removing redundant metal filling of metal layer as claimed in claim 1, is characterized in that, described redundancy metal groove is more shallow than metallic channel.
5. a kind of manufacturing process of removing redundant metal filling of metal layer as claimed in claim 1, it is characterized in that, after described step (4) completes, at etching barrier layer deposited hard mask layer, complete again photoetching and etching and form hard mask metallic channel and hard mask redundancy metal groove, carry out photoetching and etching and form through hole, continue etching, remove residue hard mask layer, form metallic channel and redundancy metal groove.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| CN101231667A (en) * | 2007-01-22 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method of filling redundancy for semiconductor manufacturing process and semiconductor device |
| US7470630B1 (en) * | 2005-04-14 | 2008-12-30 | Altera Corporation | Approach to reduce parasitic capacitance from dummy fill |
| CN102117348A (en) * | 2009-12-31 | 2011-07-06 | 中国科学院微电子研究所 | Preprocessing method using redundancy metal filling for realizing layout density uniformity |
| CN102130043A (en) * | 2010-12-30 | 2011-07-20 | 中国科学院微电子研究所 | Method for filling redundancy metal |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| US7470630B1 (en) * | 2005-04-14 | 2008-12-30 | Altera Corporation | Approach to reduce parasitic capacitance from dummy fill |
| CN101231667A (en) * | 2007-01-22 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method of filling redundancy for semiconductor manufacturing process and semiconductor device |
| CN102117348A (en) * | 2009-12-31 | 2011-07-06 | 中国科学院微电子研究所 | Preprocessing method using redundancy metal filling for realizing layout density uniformity |
| CN102130043A (en) * | 2010-12-30 | 2011-07-20 | 中国科学院微电子研究所 | Method for filling redundancy metal |
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