CN102969270A - Semiconductor device and production method thereof - Google Patents
Semiconductor device and production method thereof Download PDFInfo
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- CN102969270A CN102969270A CN2011102557571A CN201110255757A CN102969270A CN 102969270 A CN102969270 A CN 102969270A CN 2011102557571 A CN2011102557571 A CN 2011102557571A CN 201110255757 A CN201110255757 A CN 201110255757A CN 102969270 A CN102969270 A CN 102969270A
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Abstract
The invention discloses a semiconductor device and a production method thereof. The method comprises steps of providing a semiconductor substrate, wherein the semiconductor substrate comprises a redundant metal area and a non-redundant metal area; forming a dielectric layer on the semiconductor substrate; reducing the dielectric layer on the non-redundant metal area; etching the dielectric layer so as to form a redundant metal slot and a metal wire slot, wherein the depth of the redundant metal slot is less than that of the metal wire slot; depositing metal layers in the redundant metal slot and the metal wire slot and on the dielectric layer; and conducting the chemical mechanical polishing process till the surface of the dielectric layer is exposed and forming redundant metal and a metal wire, wherein the height of the redundant metal is less than that of the metal wire. By the aid of the method, the depth of the redundant metal slot is less than that of the metal wire slot. Compared with the prior art, the thickness (height) of the redundant metal is reduced, and coupling capacitance in metal layers and among metal layers, which is introduced through the filling of the redundant metal, is reduced effectively.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of semiconductor device and preparation method thereof.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, be subject to the restriction of the high-ohmic of aluminium, copper-connection gradually substitution of Al interconnection becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper interconnecting line can not obtain by etching sheet metal that as aluminum interconnecting the manufacture method of the copper interconnecting line that extensively adopts now is the embedding technique that is called Damascus technics.This Damascus technics comprises single Damascus technics of only making plain conductor and makes simultaneously the dual damascene process of through hole (also claiming contact hole) and plain conductor.Specifically, single damascene structure (also claiming single inlay structure) only is that the production method of single-layer metal wire is changed into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layer is filled), dual-damascene structure then is that through hole and plain conductor are combined, and so only needs together metal filled step.The common method of making dual-damascene structure generally has following several: all-pass hole precedence method (Full VIA First), half through hole precedence method (Partial VIA First), plain conductor precedence method (Full Trench First) and self aligned approach (Self-alignment method).
As shown in Figure 1, existing a kind of plain conductor manufacture craft comprises the steps: at first, metallization medium layer 110 at first on Semiconductor substrate 100; Then in dielectric layer 110, form metallic channel by photoetching and etching technics; Depositing metal layers subsequently, described metal level are filled in the metallic channel and on described dielectric layer 110 surfaces and have also deposited metal; Then, carry out cmp (CMP) technique and remove metal on the described dielectric layer 110, thereby in described metallic channel, made plain conductor 140.
As mentioned above, in Damascus technics, need to utilize chemical mechanical milling tech, be embedded in plain conductor 140 in the dielectric layer 110 with final formation.Yet, because the removal rate of metal and dielectric layer material is generally not identical, therefore can causes the depression (dishing) of not expecting and corrode (erosion) phenomenon the selectivity of grinding.Depression often occurs in metal and goes down to the plane of contiguous dielectric layer or exceed more than the plane of contiguous dielectric layer, and corroding then is that the part of dielectric layer is excessively thin.Depression and erosion are subject to the structure of figure and the Effects of Density of figure.Therefore, in order to reach uniform grinding effect, require the metallic pattern density on the Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.At present, solution is to fill the pattern density homogenizing that the redundancy metal pattern makes domain at the white space of domain, thereby also forms redundancy metal (dummy metal) 150 when forming plain conductor 140 in dielectric layer 110, as shown in Figure 2.But, although redundancy metal has improved the uniformity of pattern density, but introduced inevitably in the extra metal level and the coupling capacitance of metal interlevel.
Summary of the invention
The invention provides a kind of semiconductor device and preparation method thereof, fill in the metal level of introducing and the coupling capacitance of metal interlevel effectively to reduce redundancy metal.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form dielectric layer in Semiconductor substrate;
Dielectric layer on the attenuate nonredundancy metal area;
The described dielectric layer of etching is to form redundancy metal groove and metallic channel, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer; And
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
Optionally, in the manufacture method of described semiconductor device, utilize the dielectric layer on the mode attenuate nonredundancy metal area of photoetching and etching.
Optionally, in the manufacture method of described semiconductor device, the described dielectric layer of etching comprises with the step that forms redundancy metal groove and metallic channel: the dielectric layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
Optionally, in the manufacture method of described semiconductor device, the described dielectric layer of etching comprises with the step that forms redundancy metal groove and metallic channel:
Dielectric layer on the described nonredundancy metal area of etching forms through hole;
The dielectric layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
Optionally, in the manufacture method of described semiconductor device, the described dielectric layer of etching comprises with the step that forms redundancy metal groove and metallic channel:
Form hard mask layer at described dielectric layer;
The described hard mask layer of etching forms the hard mask layer groove and removes hard mask layer in the described redundancy metal district;
Dielectric layer on the described nonredundancy metal area of etching forms through hole with the position at described hard mask layer groove;
The dielectric layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
Optionally, in the manufacture method of described semiconductor device, described dielectric layer is the low k dielectric layer.
Accordingly, the present invention also provides a kind of semiconductor device, comprising: Semiconductor substrate; Be formed at the dielectric layer on the described Semiconductor substrate; Be formed at redundancy metal and plain conductor in the described dielectric layer, the height of described redundancy metal is less than the height of described plain conductor.
The present invention is after metallization medium layer, dielectric layer on elder generation's attenuate nonredundancy metal area, and then the described dielectric layer of etching is to form redundancy metal groove and metallic channel, and continue follow-up metal level deposition and chemical mechanical milling tech with formation redundancy metal and plain conductor, owing to make the degree of depth of described redundancy metal groove less than the degree of depth of metallic channel, therefore the height of the final redundancy metal that forms is less than the height of plain conductor, compared with prior art reduced the thickness (highly) of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Description of drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device of the present invention;
Fig. 4 A～4E is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention one;
Fig. 5 A～5F is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention two;
Fig. 6 A～6H is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention three.
Embodiment
Mention that in background technology although redundancy metal has improved the uniformity of pattern density, but introduced in the extra metal level and the coupling capacitance of metal interlevel, electric capacity can be calculated by following formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.This shows, reduce the relative area of metal and increase intermetallic apart from reducing electric capacity.That is to say that the volume that reduces redundancy metal can reduce the extra intermetallic coupling capacitance introduced owing to adding redundancy metal.For this reason, the present invention is after metallization medium layer, dielectric layer on elder generation's attenuate nonredundancy metal area, and then the etching dielectric layer is to form redundancy metal groove and metallic channel, and make the degree of depth of redundancy metal groove less than the degree of depth of metallic channel, compared with prior art reduced the thickness (highly) of redundancy metal, filled in the metal level of introducing and the coupling capacitance of metal interlevel thereby effectively reduce redundancy metal.
Please refer to Fig. 3, it is the schematic flow sheet of the manufacture method of semiconductor device of the present invention.As shown in Figure 3, the manufacture method of described semiconductor device comprises the steps:
Step S310: Semiconductor substrate is provided, and Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Step S320: form dielectric layer in described Semiconductor substrate;
Step S330: the dielectric layer on the described nonredundancy metal area of attenuate;
Step S340: the described dielectric layer of etching is to form redundancy metal groove and metallic channel, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Step S350: depositing metal layers in redundancy metal groove and metallic channel and on the dielectric layer; And
Step S360: carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
The present invention also provides a kind of semiconductor device that utilizes said method to make, and comprising: Semiconductor substrate; Be formed at the dielectric layer on the described Semiconductor substrate; And be formed at redundancy metal and plain conductor in the described dielectric layer, the height of described redundancy metal is less than the height of described plain conductor, compared with prior art reduced the thickness of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Semiconductor device that respectively the present invention is proposed below in conjunction with generalized section and preparation method thereof is described in further detail.
Embodiment one
Shown in Fig. 4 A, at first, provide Semiconductor substrate 400, this Semiconductor substrate 400 comprises redundancy metal district 402 and nonredundancy metal area 401, described redundancy metal district 402 is in order to form redundancy metal, and the semiconductor substrate region outside the described redundancy metal district 402 is nonredundancy metal area 401.Wherein, be formed with metal line in the described Semiconductor substrate 400.Because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that in Semiconductor substrate 400, forms metal line, but those skilled in the art are still this and know.
Continue with reference to figure 4A, then, form dielectric layer 410 in Semiconductor substrate 400, the thickness of described dielectric layer 410 is the required thickness of dielectric layers of the plain conductor degree of depth and the thickness of dielectric layers sum of wanting attenuate in subsequent step.Wherein, described dielectric layer 410 is preferably low-k (K) dielectric layer, postpones with the resistance capacitance that reduces its parasitic capacitance and metallic copper, satisfies the requirement of Quick conductive.Better, it is black diamond (black diamond that described dielectric layer 410 adopts the trade mark of Material Used (Applied Materials) company, BD) silicon oxide carbide, perhaps adopt the Coral material of Novellus company, again or adopt and to utilize spin coating process to make the Silk advanced low-k materials of Dow Corning Corporation etc.
In other embodiments of the invention, before described Semiconductor substrate 400 forms dielectric layer 410, also can form first etching stop layer (not shown), described etching stop layer can be used for preventing that the metal in the metal line is diffused in the dielectric layer 410, and described etching stop layer can prevent that also the metal line in the Semiconductor substrate 400 is etched in follow-up etching process of carrying out in addition.The material of described etching stop layer for example is silicon nitride, and the dielectric layer of itself and follow-up formation has preferably adhesiveness.
Shown in Fig. 4 B, then, utilize photoetching process to form the first mask layer at described dielectric layer 410, described the first mask layer exposes the dielectric layer on the nonredundancy metal area 401, subsequently take described the first mask layer as mask, the described dielectric layer 410 of etching is with the dielectric layer on the attenuate nonredundancy metal area 401, and then removes described the first mask layer, and described the first mask layer can utilize the mode of dry method or wet method to remove.After finishing this step, the thickness of dielectric layers in the described redundancy metal district 402 is greater than the thickness of dielectric layers on the described nonredundancy metal area 401.
Shown in Fig. 4 C, thereafter, utilize photoetching process to form the second mask layer with metallic channel pattern and redundancy metal groove pattern at dielectric layer 410, and take described the second mask layer as mask, the described dielectric layer 410 of etching forms metallic channel 412 and redundancy metal groove 411, because the dielectric layer on the described nonredundancy metal area 401 has been thinned, therefore although be in this step etching simultaneously, but the degree of depth of the final redundancy metal groove 411 that forms will be less than the degree of depth of metallic channel 412, described metallic channel 412 is the thickness that dielectric layer is thinned with the difference of redundancy metal groove 411 degree of depth (highly), then removes described the second mask layer.Wherein, the height of described redundancy metal groove 412 can change accordingly according to concrete technology, and the thickness that the dielectric layer on the described nonredundancy metal area 401 is thinned can determine according to concrete technology that also the present invention also will not limit this.
Shown in Fig. 4 D, subsequently, to described redundancy metal groove 411 and metallic channel 412 interior depositing metal layers 420, because the characteristic of depositing operation also can deposit metal on this process medium layer 410, the material of wherein said metal level 420 is copper.
Shown in Fig. 4 E, subsequently, carry out cmp (CMP) technique until expose the surface of dielectric layer 410, with at redundancy metal groove 411 interior formation redundancy metals 421, and at metallic channel 412 interior plain conductors 422, the height of described redundancy metal 421 is less than the height of described plain conductor 422.Owing to make the degree of depth of redundancy metal groove 411 less than the degree of depth of metallic channel 412, therefore the height of the final redundancy metal 421 that forms is less than the height of plain conductor 422, compared with prior art reduced the height (thickness) of redundancy metal 421, filled in the metal level of introducing and the coupling capacitance of metal interlevel thereby effectively reduce redundancy metal.
Embodiment two
Shown in Fig. 5 A, at first, provide Semiconductor substrate 500, this Semiconductor substrate 500 comprises redundancy metal district 502 and nonredundancy metal area 501, forms dielectric layer 510 in Semiconductor substrate 500 subsequently.
Shown in Fig. 5 B, then, utilize the thickness of dielectric layers on the described nonredundancy metal area 501 of photoetching and etching technics attenuate, finish this step after, the thickness of dielectric layers in the described redundancy metal district 502 is greater than the thickness of dielectric layers on the described nonredundancy metal area 501.
Shown in Fig. 5 C, utilize photoetching process to form the first mask layer with through-hole pattern at dielectric layer 510, and take described the first mask layer as mask, dielectric layer on the described nonredundancy metal area 501 of etching, thereby form through hole 513 at the nonredundancy metal area, and then remove described the first mask layer.
Shown in Fig. 5 D, subsequently, form the second mask layer with metallic channel pattern and redundancy metal groove pattern at described dielectric layer 510, and take described the second mask layer as mask, the dielectric layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form redundancy metal groove 511, and at through hole 513 correspondence positions formation metallic channel 512, because the dielectric layer on the described nonredundancy metal area 501 has been thinned, therefore the degree of depth of the final described redundancy metal groove 511 that forms is less than the degree of depth of described metallic channel 512.
Shown in Fig. 5 E, subsequently, to described redundancy metal groove 511 and metallic channel 512 interior depositing metal layers 520, because the characteristic of depositing operation also can deposit metal on this process medium layer 510.
Shown in Fig. 5 F, subsequently, carry out chemical mechanical milling tech until expose the surface of dielectric layer 510, with at redundancy metal groove 511 interior formation redundancy metals 521, and at metallic channel 512 interior plain conductors 522, the height of described redundancy metal 521 is less than the height of plain conductor 522, therefore the height of the final redundancy metal 521 that forms is less than the height of plain conductor 522, namely compared with prior art reduced the height of redundancy metal 521, effectively reduced redundancy metal and filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment three
As shown in Figure 6A, at first, provide Semiconductor substrate 600, this Semiconductor substrate 600 comprises redundancy metal district 602 and nonredundancy metal area 601, forms dielectric layer 610 in Semiconductor substrate 600 subsequently.
Shown in Fig. 6 B, then, utilize the dielectric layer on the described nonredundancy metal area 601 of photoetching and etching technics attenuate, finish this step after, the thickness of dielectric layers in the described redundancy metal district 602 is greater than the thickness of dielectric layers on the described nonredundancy metal area 601.
Shown in Fig. 6 C, then, form hard mask layer 630 at dielectric layer 610, preferably, have better etching selection ratio at hard mask layer described in the subsequent etching technique 630 and dielectric layer 610.
Shown in Fig. 6 D, subsequently, the described hard mask layer 630 of etching forms hard mask layer groove 631, and removes the hard mask layer in the described redundancy metal district 602.
Shown in Fig. 6 E, thereafter, the described dielectric layer 610 of etching forms through hole 613 with the position at hard mask layer groove 631, and described hard mask layer groove 631 has played the effect of autoregistration (Self-alignment).
Shown in Fig. 6 F, then, etching dielectric layer 610 forms metallic channel 612 with the position at through hole 613, and forms redundancy metal groove 611 in the redundancy metal district, and the degree of depth of described redundancy metal groove 611 is less than the degree of depth of metallic channel 612.
Shown in Fig. 6 G, subsequently, to redundancy metal groove 611 and metallic channel 612 interior depositing metal layers 620, because the characteristic of depositing operation also can deposit metal on this process medium layer 610.
Shown in Fig. 6 H, subsequently, carry out chemical mechanical milling tech until expose the surface of described dielectric layer 610, with at redundancy metal groove 611 interior formation redundancy metals 621, and at metallic channel 612 interior plain conductors 622, the height of described redundancy metal 621 is less than the height of described plain conductor 622, because the height of the final redundancy metal 621 that forms is less than the height of plain conductor 622, namely compared with prior art reduced the height (thickness) of redundancy metal 621, therefore can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this specification, each embodiment stresses is difference with other embodiment, the mutually reference of relevant part.And accompanying drawing all adopts the form of simplifying very much and all uses non-accurately ratio, only is used for purpose convenient, each embodiment of lucidly aid illustration the present invention.
In addition, although below describe the present invention in detail as an example of the dual damascene metal interconnect structure (referring to embodiment three) of the dual damascene metal interconnect structure (referring to embodiment two) of single Damascus metal interconnect structure (referring to embodiment one), through hole elder generation etching and the first etching of the hard mask groove of self-alignment type example respectively, those skilled in the art can also carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form dielectric layer in described Semiconductor substrate;
Dielectric layer on the described nonredundancy metal area of attenuate;
The described dielectric layer of etching is to form redundancy metal groove and metallic channel, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer; And
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, utilizes the dielectric layer on the mode attenuate nonredundancy metal area of photoetching and etching.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the described dielectric layer of etching comprises with the step that forms redundancy metal groove and metallic channel:
The dielectric layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the described dielectric layer of etching comprises with the step that forms redundancy metal groove and metallic channel:
Dielectric layer on the described nonredundancy metal area of etching forms through hole;
The dielectric layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
5. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the described dielectric layer of etching comprises with the step that forms redundancy metal groove and metallic channel:
Form hard mask layer at described dielectric layer;
The described hard mask layer of etching forms the hard mask layer groove and removes hard mask layer in the described redundancy metal district;
Dielectric layer on the described nonredundancy metal area of etching forms through hole with the position at described hard mask layer groove;
The dielectric layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
6. such as the manufacture method of the described semiconductor device of any one in the claim 1 to 5, it is characterized in that described dielectric layer is the low k dielectric layer.
7. a semiconductor device that utilizes method claimed in claim 1 to form is characterized in that, comprising:
Semiconductor substrate;
Be formed at the dielectric layer on the described Semiconductor substrate;
Be formed at redundancy metal and plain conductor in the described dielectric layer, the height of described redundancy metal is less than the height of described plain conductor.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022061825A1 (en) * | 2020-09-27 | 2022-03-31 | 华为技术有限公司 | Preparation method for through silicon via structure, and through silicon via structure |
| CN114743931A (en) * | 2022-06-14 | 2022-07-12 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor integrated device |
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| US20080174022A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
| US20090200683A1 (en) * | 2008-02-13 | 2009-08-13 | International Business Machines Corporation | Interconnect structures with partially self aligned vias and methods to produce same |
| US20090239375A1 (en) * | 2008-03-19 | 2009-09-24 | Philipp Riess | Dual Damascene Process |
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- 2011-08-31 CN CN2011102557571A patent/CN102969270A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20080174022A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
| US20090200683A1 (en) * | 2008-02-13 | 2009-08-13 | International Business Machines Corporation | Interconnect structures with partially self aligned vias and methods to produce same |
| US20090239375A1 (en) * | 2008-03-19 | 2009-09-24 | Philipp Riess | Dual Damascene Process |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022061825A1 (en) * | 2020-09-27 | 2022-03-31 | 华为技术有限公司 | Preparation method for through silicon via structure, and through silicon via structure |
| CN114743931A (en) * | 2022-06-14 | 2022-07-12 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor integrated device |
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Application publication date: 20130313 |