CN102446956B

CN102446956B - A kind of semiconductor high-power device and manufacture method thereof

Info

Publication number: CN102446956B
Application number: CN201110259354.4A
Authority: CN
Inventors: 万小敏
Original assignee: Individual
Current assignee: Individual
Priority date: 2011-09-05
Filing date: 2011-09-05
Publication date: 2016-02-17
Anticipated expiration: 2031-09-05
Also published as: CN102446956A

Abstract

The present invention relates to semiconductor device and preparation method thereof technical field, that refers in particular to a kind of Super-Junction of having structure partly leads high-power body device and simple and effective implementation method thereof.This structure has comprised the center of forward work and has assisted the termination environment of reverse operation; All regions all have P/N post to be arranged in order; For N-type device: the p type island region field width degree in all regions is all identical with the degree of depth, territory, the p type island region spacing in all regions is also identical; The polysilicon of P post is connected to or/and metal is as field plate by increasing on surface, make surface field lower than critical electric field when bearing high voltage, and finally make all P/N columnar regions comprising center and external zones all effectively be exhausted, and first puncture in center.Simplicity of design of the present invention, only needs suitable adjustment field plate spacing and quantity both can meet the device of different puncture voltage specification; Manufacture simple, all P/N posts are standard P/N pole unit and form, and are applicable to deep trouth technique and repeatedly ion implantation technology simultaneously; Structure is reliable, can effectively realize oppositely withstand voltage, effectively improves finished product rate.

Description

A kind of semiconductor high-power device and manufacture method thereof

Technical field

Designing semiconductor device of the present invention and preparation method thereof technical field, that refers in particular to a kind of Super-Junction of having structure partly leads high-power body device and simple and effective implementation method thereof.

Background technology

Metal-oxide layer-semiconductor-field-effect transistor, being called for short metal-oxide half field effect transistor (Metal-Oxide-SemiconductorField-EffectTransistor, MOSFET) is a kind of field-effect transistor (field-effecttransistor) that can be widely used in analog circuit and digital circuit.MOSFET is different according to the polarity of its " passage ", can be divided into the MOSFET of N-type and P type, usually be also called NMOSFET and PMOSFET.Common N-type MOSFET adopts one block of P-type silicon semi-conducting material as substrate, diffuses to form N-type region territory thereon, covers insulating barrier, finally providing holes on N-type region territory, as electrode at end face.In order to improve the characteristic of some parameter, there is different structure &processes as improved operating current, raising operating voltage, the conducting resistance that reduces, raising switching characteristic etc., forming the structures such as so-called VMOS, DMOS, TMOS.

For common VDMOSEFT (vertical bilateral diffusion metallic oxide field effect pipe), when puncture voltage requires more and more higher, conducting resistance is also more and more higher, and Here it is usual said " silicon limit " for common VDMOSEFT.The structure breaking " silicon limit " is Super-Junction structure, and it is usually replaced the drift region of common VDMOSEFT or part replaces to P/N post to the 3D structure be arranged in order, and PN junction is arranged according to certain rules in this inside configuration.

For high voltage power device, its region of conducting electricity under can being divided into conducting state (i.e. active area) and to turn off and as the region (i.e. termination environment) of active area to chip edge transition under bearing high pressure conditions.Termination environment is most important, and not only can relation device reach specified puncture voltage, is more related to the integrity problem of devices switch process and non-normal working situation.

For the device of a Super-Junction structure, epitaxial layer concentration is about 10 ~ 20 times of the VDMOSEFT of same breakdown voltage grade, and this determines according to process conditions.Known by the Poisson's equation of classics: the width of PN junction side depletion layer follows the square root of this side impurity concentration to be inversely proportional to, so when concentration is increased to 10 times depletion width can be compressed to increase before about 1/3. when critical electric field is substantially constant, effectively must increase depletion width to meet specified breakdown voltage value.In the active area of Super-Junction, the depletion layer tied by adjacent longitudinal P N is together with each other and sets up an enough wide and depletion layer completely.If do not have terminal structure, the PN junction of other longitudinal directions is not being had to combine with it an effective depletion layer completely in the outside of the PN junction of Super-Junction device outermost; Once effectively can not form depletion layer, so electric field is inevitable concentrates at this, realize breakdown voltage rating by impossible.The present invention, by increasing field plate in terminal end surface, introduces additional charge on surface when bearing high voltage, its surface field is distributed to whole terminal, suppresses the electric field of local to be concentrated, thus the puncture voltage that realization requires.

What the terminal structure about Super-Junction device was popular has two kinds: a kind of is adopt the mode changing P/N post width and/or spacing to meet the charge balance of terminal, this patten's design difficulty very, because the change of one of them width or spacing can affect the charge balance state of terminal entirety; And also more difficult about middle realization at deep trouth, because change the depth ratio of groove; Another kind adopts dark and wide groove isolation, generally fills insulating dielectric materials in groove, and this is a huge challenge in technique.

Summary of the invention

Technical problem to be solved by this invention is just to provide a kind of and is easy to design, can not additional process difficulty, cost a kind of semiconductor high-power device advantageously and manufacture method thereof, the high power device made by the present invention is not increased extra processing step and ensures sufficiently high yields, can be solved the terminal problem of Super-Junction device by the present invention.

In order to solve the problems of the technologies described above, present invention employs following technical scheme, the present invention is by introducing the PN post of ring-type in periphery, active area, the active area of positioned proximate central, several wide equally spaced P/N post close-packed arrays successively from inside to outside, the width of P/N post is completely the same with active area P/N post with spacing; The field plate be made up of metal and/or the polycrystalline of one fixed width is also arranged in order by certain spacing from inside to outside, and is connected with corresponding P or N post by contact hole.By suitably increasing or reduce the quantity of terminal P/N post, increasing accordingly or reduce corresponding field plate quantity simultaneously, namely can meet the device of different breakdown voltage rating when slightly adjusting field plate length and spacing.This theory is completely based on charge balance concept, so be not only applicable to Super-Junction device, even SemiSuper-Junction device, this structure is also completely applicable.

Furthermore, in technique scheme, in the structure of high power device, surfaces of active regions structure is the DMOSFET structure comprising planar gate and grooved grid, and P/N posts all in whole device context all has identical width, spacing and the degree of depth.

The first technical scheme that manufacture method of the present invention adopts is: its making step comprises: the first step, at the epitaxial loayer that the Grown of first kind conduction type is identical with substrate conduction type; Second step, adopt ion etching mode to slot in epitaxial loayer, the cell body degree of depth is no more than the thickness of epitaxial loayer; 3rd step, grows the silicon epitaxy layer of Equations of The Second Kind conduction type in groove; 4th step, surface planarisation obtains the semi-finished product with alternate P/N post; 5th step, above-mentioned semi-finished product are processed according to metal oxide layer semiconductor field effect transistor structure, obtain device finished product; Offer several wide equally spaced groove in above-mentioned epitaxial loayer, and groove is arranged in order.

The second technical scheme that manufacture method of the present invention adopts is: its making step comprises: the first step, the epitaxial loayer that repeatedly growth is identical with substrate conduction type on the substrate of first kind conduction type; And after outer layer growth each time, in specific region, implanting impurity ion forms Equations of The Second Kind electric conducting material; Second step, carries out annealing and knot, and the ion diffuse that order is injected also joins together, and forms alternate P/N post semi-finished product; 3rd step, above-mentioned semi-finished product are processed according to metal oxide layer semiconductor field effect transistor structure, obtain device finished product; The region of above-mentioned repeatedly implanting impurity ion is wide, equidistant each other, and is arranged in order.

Furthermore, in the technical scheme of above-mentioned two kinds of manufacture methods, described high power device comprises N type semiconductor device and P type semiconductor device, wherein making the first kind conductivity type material that N type semiconductor device adopts is: other semi-conducting materials of doped type N impurity silicon or doped type N impurity, and described Equations of The Second Kind conductivity type material is: mix p type impurity silicon or mix other semi-conducting materials of p type impurity; The first kind conductivity type material that making P type semiconductor device adopts, Second Type material are contrary with above-mentioned N type semiconductor equipment.

The present invention is a kind of not changing the structure adding field plate under groove depth, groove width and separation prerequisite, and than traditional terminal structure, it all has more advantage in design cost and manufacturing cost two.The state turned off, when device bears large voltage, field plate is stored charge under the effect of electric field, inhibits concentrating of electric field, completes the work of charge balance, thus effectively form depletion layer in the terminal, realize the puncture voltage required; In opening, PN junction depletion layer is very thin, and electric current arrives another electrode through first kind conductive region and raceway groove from an electrode.

Accompanying drawing explanation

Fig. 1 is the first common Super-Junction semiconductor device structure schematic diagram;

Fig. 2 is the second common Super-Junction semiconductor device structure schematic diagram;

Fig. 3 is structural representation of the present invention;

Fig. 4 a-4b is domain schematic diagram of the present invention;

Fig. 5 is simulation result figure of the present invention.

Description of reference numerals:

1 substrate 2 epitaxial loayer 3P columnar region 4Body district

5 grid 7 termination environment, source area 6 Equations of The Second Kind electric conducting material 8 grid BUS

9 field plate 10 insulating material

I represents first kind conductive type semiconductor material;

II represents Equations of The Second Kind conductive type semiconductor material.

Embodiment

High power device of the present invention can be N type semiconductor device or P type semiconductor device, wherein making the first kind conductivity type material that N type semiconductor device adopts is: other semi-conducting materials of doped type N impurity silicon or doped type N impurity, and described Equations of The Second Kind conductivity type material is: mix p type impurity silicon or mix other semi-conducting materials of p type impurity; The first kind conductivity type material that making P type semiconductor device adopts, Second Type material are contrary with above-mentioned N type semiconductor equipment.In below illustrating, assuming that I is n type single crystal silicon material, II is p type single crystal silicon material.

See shown in Fig. 1,2, this is Super-Junction semiconductor device structure schematic diagram common at present, it comprises: substrate 1 and epitaxial loayer 2, the P/N post being arranged in epitaxial loayer 2, source area 5 and P-Body district 4, and 6 grids, screen BUS8 and 10 insulating material.Wherein, I is n type single crystal silicon material, and II is p type single crystal silicon material.

See Fig. 3, device of the present invention adopts MOSFET (metal oxide layer semiconductor field-effect transistor) structure, it comprises: substrate 1 and epitaxial loayer 2, the P/N post being arranged in epitaxial loayer 2, source area 5 and P-Body district 4, wherein, the P/N post of ring-type is introduced in termination environment, the active area of positioned proximate central, several wide equally spaced P/N post is arranged in order from inside to outside; The field plate be made up of metal and/or polysilicon is spaced from inside to outside, and is connected with corresponding P post by contact hole.

Wherein active area comprises: P post region territory 3, P-Body region 4, source area 5 and grid 6; Termination environment comprises: P post region territory 7, grid BUS8 and field plate 9.Grid BUS8 also adopts metal and/or polycrystalline to form.

Embodiment with Super-Junction structure for main body is divided into two kinds.Here for N-type silicon device.The method comprises the following steps:

The first step, at the epitaxial loayer that N+ Grown is identical with substrate conduction type;

Second step, adopt ion etching mode to slot in epitaxial loayer, the cell body degree of depth is no more than the thickness of epitaxial loayer;

3rd step, growing P-type silicon epitaxy layer in groove;

4th step, surface planarisation obtains the semi-finished product with alternate P/N post;

5th step, above-mentioned semi-finished product are processed according to metal oxide layer semiconductor field effect transistor structure, obtain device finished product;

Above-mentioned epitaxial loayer offers several wide equally spaced groove, and groove is arranged in order.

What this method adopted is deep trouth technique, the method is first extension N-type silicon on the N+ substrate 1 of low-resistance in brief, then etch deep trouth and in groove growing P-type silicon, complete after surface planarisation surface common DMOSFET structure, the field plate of terminal belongs to a part for common DMOSFET structure.

The present invention also can adopt alternatively, specifically comprises the steps:

The first step, the epitaxial loayer that repeatedly growth is identical with substrate conduction type on N+ substrate; And after outer layer growth each time, in specific region, implanting impurity ion forms Equations of The Second Kind electric conducting material;

Second step, carries out annealing and knot, and the ion diffuse that order is injected also joins together, and forms alternate P/N post semi-finished product;

3rd step, above-mentioned semi-finished product are processed according to metal oxide layer semiconductor field effect transistor structure, obtain device finished product;

Above-mentioned substrate repeatedly prolongs layer and the region of implanting impurity ion each other for wide, equidistant, and to be arranged in order.

Said method is repeatedly extension repeatedly injection technology, in brief, be divided into extension several times to complete whole Super-Junction structure sheaf, the region implanting p-type impurity needed after extension each time, by annealing and knot after all extensions and injection complete, the p type impurity injected for each time being connected as a single entity and forming P post, has been finally common DMOSFET structure equally.

The present invention makes and adopts the Super-Junction device of field plate termination structure can based on any material that is silica-based and that reach in silica-based identical performance or more superior function.

In making process of the present invention, charge balance is most important in Super-Junction structure, doping content directly can have influence on the maximum voltage and conducting resistance that device can bear, thus to doping content hold need very careful, must within the scope that technique is controlled.

(1) the present invention increases the field plate of some certain lengths by device terminal region, introduce in terminal end surface the charge balance that extra electric charge can reach desirable to make whole device when bearing voltage, complete depletion layer can be set up, reach specified breakdown voltage value.The present invention is except thinking is simply distinct in design; Whole device is to the requirement of Super-Junction structure sheaf without any harshness: the terminal of traditional Super-Junction device must adjust P/N post width or P/N intercolumniation, and this deep trouth technological requirement for main flow is abnormal harsh; On all four groove width and on all four spacing ensure that the requirement of technique minimum, improve the tolerance to technique, thus can ensure high stability, yields and reliability.

(2) the present invention is applicable to different manufacture crafts: in deep trouth technique, have obvious advantage; Simultaneously the present invention is also applicable to the technique with repeatedly extension repeatedly ion implantation, and design can become more simple, the charge balance concerns at easier processing apparatus four angles.

(3) the present invention is applicable to the device of different puncture voltage, only needs suitably increase or reduce the terminal P/N band of column and field plate quantity under the prerequisite that area is economized most.

(4) in structure of the present invention, the quantity of P/N post, concrete width and spacing are determined according to the technological ability of reality and design requirement, and the doping content of P/N post is determined jointly by the width of P/N post, spacing and technique accuracy, general at 1 ~ 4e15/cm at present ³magnitude.The developing direction of Super-Junction is that the width of P/N post and spacing are less, and doping content is higher, thus resistance is less under the prerequisite not affecting puncture voltage.When technological ability improves, such as, when the depth-to-width ratio of deep trouth technique middle slot can do more, or the precision of ion implantation dosage is higher, just can be less for the width of the device P/N post of certain puncture voltage and spacing, and doping content just can be higher.And the terminal of structure of the present invention is only needed to make simple change: first is width and the spacing of scaled field plate; Second is that the quantity increasing terminal P/N post and field plate remains unchanged to meet terminal overall width, keeps Electric Field Distribution substantially constant.

This terminal structure is equally applicable to SemiSuper-Junction device and have employed the IGBT device of Super-Junction structure.

See shown in Fig. 4 a, 4b, this is the domain schematic diagram of structure of the present invention: wherein Fig. 4 a: the domain structure being applicable to bar shaped cellular, and what in Fig. 4 a, color was darker is P type doped region, and light areas represents polycrystalline or/and Metal field plate.Fig. 4 b is the one distortion of Fig. 4 a, and it is applicable to the domain structure of square/circle/hexagonal cells.

As shown in Figure 5, this is structure simulation design sketch of the present invention.

Claims

1. a manufacture method for semiconductor high-power device, is characterized in that: this manufacture method comprises the following steps:

The first step, at the epitaxial loayer that the Grown of first kind conduction type is identical with substrate conduction type;

3rd step, generates the silicon epitaxy layer of Equations of The Second Kind conduction type in groove;

5th step, above-mentioned semi-finished product are processed according to MOSFET structure, obtain device finished product;

Have multiple wide, equally spaced groove in above-mentioned epitaxial loayer, and groove is arranged in order;

Described high power device comprises N type semiconductor device or P type semiconductor device, the first kind conductivity type material that wherein making N type semiconductor device adopts is: other semi-conducting materials of doped type N impurity silicon or doped type N impurity, and described Equations of The Second Kind conductivity type material is: mix p type impurity silicon; Make first kind conductivity type material that P type semiconductor device adopts, Equations of The Second Kind conductivity type material and the first kind conductivity type material that above-mentioned making N type semiconductor device adopts, Equations of The Second Kind conductivity type material are contrary;

In manufactured semiconductor high-power device, the P/N post of ring-type is introduced in periphery, active area, and several wide equally spaced P/N post is arranged in order from inside to outside; The field plate be made up of metal and/or polysilicon is also spaced from inside to outside with P/N post, and is connected with corresponding P or N post by contact hole.

2. a manufacture method for semiconductor high-power device, is characterized in that: this manufacture method comprises the following steps:

The first step, the epitaxial loayer that repeatedly extension is identical with substrate conduction type on the substrate of first kind conduction type; And after outer layer growth each time, in specific region, implanting impurity ion forms Equations of The Second Kind electric conducting material;

3rd step, above-mentioned semi-finished product are processed according to MOSFET structure, obtain device finished product;

The region of above-mentioned implanting impurity ion is wide, equidistant each other, and is arranged in order;

Described high power device comprises N type semiconductor device or P type semiconductor device, the first kind conductivity type material that wherein making N type semiconductor device adopts is: other semi-conducting materials of doped type N impurity silicon or doped type N impurity, and described Equations of The Second Kind conductivity type material is: mix p type impurity silicon or mix other semi-conducting materials of p type impurity; Make first kind conductivity type material that P type semiconductor device adopts, Equations of The Second Kind conductivity type material and the first kind conductivity type material that above-mentioned making N type semiconductor device adopts, Equations of The Second Kind conductivity type material are contrary;

In manufactured semiconductor high-power device, the P/N post of ring-type is introduced in periphery, active area, and several wide equally spaced P/N post is arranged in order from inside to outside; The field plate be made up of metal and/or polysilicon is also spaced from inside to outside with P/N post, and is connected with corresponding P or N post by contact hole;

Said method is repeatedly extension repeatedly injection technology, extension is several times divided into complete the structure sheaf of whole super junction, in the region implanting p-type needed or N-type impurity after extension each time, by annealing and knot after all extensions and injection complete, the P type that injects for each time or N-type impurity are connected as a single entity and form P post or N post, finally complete DMOSFET structure.