CN102446822A - Integration method of dual Damascus - Google Patents
Integration method of dual Damascus Download PDFInfo
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- CN102446822A CN102446822A CN201110265235XA CN201110265235A CN102446822A CN 102446822 A CN102446822 A CN 102446822A CN 201110265235X A CN201110265235X A CN 201110265235XA CN 201110265235 A CN201110265235 A CN 201110265235A CN 102446822 A CN102446822 A CN 102446822A
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Abstract
The invention discloses an integration method of dual Damascus, and the integration method uses a Damascus manufacturing process of digging trenches before vias. The method comprises the following steps: firstly depositing a metal hard mask when the vias are formed, thus effectively avoiding generating drain current and interlinkage between adjacent vias; reducing control difficulty of key sizes of the vias in an advanced copper process, improving the performance and reliability of a semiconductor device; and the technical process is simple and easy to control, and the method is suitable for popularizing application.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field, relate to a kind of integrated approach of dual damascene specifically.
Background technology
In semi-conductive production technology, owing to for example comprise MOSFETS (mos field effect transistor) and by the improving constantly of the device integrated level of MOS or the manufacturing of CMOS technology, the miniaturization of semiconductor device also just is being faced with and is challenging.Not only size of devices needs to reduce its size with the zone, and on quality and rate of finished products, still has very high expectation.The junction depth of the device of this type relates to the high activity of doping, excellent control of junction depth or the like.
So-called dual damascene process is opened through hole and the groove a kind of common technology that material such as row metal fills of going forward side by side exactly on dielectric layer.Double damask structure can be divided into three kinds of technology such as first channel excavation, first through hole excavation and self-aligned formula at present haply if classify according to the difference of dry ecthing mode.For example; At present; The dual damascene manufacturing process of traditional first through hole (Via) back groove (Trench) commonly used in the inherent semi-conductive manufacture process of semiconductor industry, this manufacturing process, at first deposition of dielectric layer; Photoetching via hole image and adopt dry etching through hole depositing metal barrier layer and copper seed layer and fill up through hole with electro-coppering is subsequently then removed excess metal with cmp subsequently; After accomplishing through hole, deposition of dielectric layer and photoetching form groove figure once more on through hole, adopt dry etching groove depositing metal barrier layer and copper seed layer and fill up groove with electro-coppering subsequently, then remove excess metal with cmp once more.
But these methods of the prior art all exist the through hole critical size and are difficult to control, and because the distance between through hole and the through hole is less; And cause through hole bigger easily to the leakage current between the through hole, What is more, the situation that also possibly take place to connect together between the through hole; Above-mentioned situation can make the poor-performing of time breakdown (TDDB), thereby has influenced the reliability of copper-connection, therefore; Need the integrated approach that a kind of new Damascus occurs badly, to overcome the problems referred to above.
Summary of the invention
The object of the present invention is to provide a kind of integrated approach of dual damascene, leakage current and the generation of the interconnection phenomenon between the adjacent through-holes that it can effectively be avoided between the adjacent through-holes have reduced the control difficulty of through hole critical size in the advanced copper wiring.
For realizing above-mentioned purpose, technical scheme provided by the present invention is:
A kind of integrated approach of dual damascene wherein, comprises the steps:
Step S1 a: silicon substrate is provided, is formed with completed anterior layer metal on the said silicon substrate, on said silicon substrate, be deposited with via etch barrier layer, dielectric layer with low dielectric constant and dielectric protection layer from bottom to up successively;
Step S2: on said dielectric protection layer, apply one deck photoresist, and carry out photoetching process, form groove opening;
Step S3: with the photoresist is mask; Through said dielectric protection layer of said groove opening etching successively and said dielectric layer with low dielectric constant; And etching stopping is in said dielectric layer with low dielectric constant; Formation runs through the groove of said dielectric protection layer and said dielectric layer with low dielectric constant, and removes photoresist;
Step S4: the sidewall and the deposit layer of metal hard mask layer of and said groove supreme in said dielectric protection layer, and on said metal hard mask layer the anti-anti-erosion agent layer in deposit bottom;
Step S5: on the anti-anti-erosion agent layer in said bottom, apply one second photoresist, and carry out photoetching, form the via openings that is arranged in said second photoresist, wherein, the width of said opening has defined the width of the through hole of follow-up formation;
Step S6: with said second photoresist is mask; Through the anti-anti-erosion agent layer in the said bottom of said via openings etching successively and said metal hard mask layer and low dielectric coefficient medium layer; And etching stopping is in low dielectric coefficient medium layer; Formation is arranged in the partial through holes structure of said metal hard mask layer and said low dielectric coefficient medium layer, and removes the anti-anti-erosion agent layer of remaining photoresist and bottom;
Step S7: continue said low dielectric coefficient medium layer of etching and said via etch barrier layer through the partial through holes structure; Expose the active area metal silicide on the said silicon substrate, form in the vertical direction and run through the through-hole structure in said metal hard mask layer, said low dielectric coefficient medium layer and the said via etch barrier layer;
Step S8: on said metal hard mask layer and the sidewall of said through-hole structure and deposit metal barrier and copper seed layer, and adopt electrochemistry plating ECP technology growing metal copper, make metallic copper be filled in said groove and the said through-hole structure;
Step S9: carry out chemical mechanical milling tech, remove unnecessary metallic copper.
Above-mentioned method, wherein, the material that constitutes said via etch barrier layer is SiCN.
Above-mentioned method wherein, adopts the described via etch of chemical meteorology deposition method deposit barrier layer.
Above-mentioned method, wherein, the material that constitutes low dielectric coefficient medium layer is SiOCH.
Above-mentioned method wherein, adopts the said low dielectric coefficient medium layer of chemical meteorology deposition method deposit.
Above-mentioned method, wherein, the material that constitutes dielectric protection layer is SiO
2
Above-mentioned method wherein, adopts the said dielectric protection layer of chemical vapour deposition technique deposit.
Above-mentioned method, wherein, the material that constitutes metal hard mask layer is Ta or TaN or Ti or TiN.
Above-mentioned method wherein, adopts chemical vapour deposition technique or the said metal hard mask layer of physical vaporous deposition deposit.
Above-mentioned method, wherein, the material that constitutes said metal barrier is TaN or Ta.
The integrated approach of a kind of dual damascene of the present invention; Use the Damascus manufacturing process of through hole behind the first groove, and when forming through hole the hard mask of at first deposit layer of metal, can effectively avoid leakage current and the generation of the interconnection phenomenon between the adjacent through-holes between the adjacent through-holes; Reduced the control difficulty of through hole critical size in the advanced copper wiring; And improved the Performance And Reliability of semiconductor device, technical process is simple and easy to control, is suitable for penetration and promotion and is suitable for.
Description of drawings
Fig. 1 is the flow chart of the integrated approach of a kind of dual damascene of the present invention;
The cross-sectional view of the formed device architecture of each step in the integrated approach of a kind of dual damascene of the present invention that Fig. 2 A-2I shows for Fig. 2.
Embodiment
Come the contact hole formation method of reduction contact hole resistance of the present invention is done explanation in further detail below in conjunction with Figure of description and embodiment.
Shown in Fig. 1 and Fig. 2 A-2I, the integrated approach of a kind of dual damascene of the present invention, it comprises the steps:
Step S1 a: silicon substrate 101 is provided; Be formed with completed anterior layer metal 101a on the silicon substrate 101, and adopt the chemical vapour deposition technique barrier layer of deposit via etch successively 102, dielectric layer with low dielectric constant 103 and dielectric protection layer 104 from bottom to up on silicon substrate 101 respectively;
Step S2: adopt spin-coating method on dielectric protection layer 104, to apply one deck photoresist 105, and carry out photoetching process (comprising processing steps such as exposure, development), form groove opening 100a;
Step S3: with photoresist 105 is mask; Adopt dry etching etching dielectric protection layer 104 and dielectric layer with low dielectric constant 103 successively through groove opening 100a; And etching stopping is in dielectric layer with low dielectric constant 103; Formation runs through the groove 100 of dielectric protection layer 104 and dielectric layer with low dielectric constant 103, and removes remaining photoresist 105;
Step S4: adopt chemical vapour deposition technique on dielectric protection layer 104 and the sidewall of groove 100 and deposit layer of metal hard mask layer 106, and on metal hard mask layer 106 the anti-agent layer 107 that instead loses in deposit bottom;
Step S5: on the anti-anti-erosion agent layer 107 in bottom, apply one second photoresist 108; And carry out photoetching; Formation is arranged in the via openings 108a and the 108b of second photoresist 108, and wherein, the width of via openings 108a and 108b has defined the through-hole structure 2001 of follow-up formation and 2002 width;
Step S6: with second photoresist 108 is mask; Adopt the dry etching anti-anti-erosion agent layer 107 in etching bottom and metal hard mask layer 106 and low dielectric coefficient medium layer 103 successively through via openings 108a and 108b; And etching stopping is in low dielectric coefficient medium layer 103; Formation is arranged in the partial through holes structure 200a and the 200b of metal hard mask layer 106 and low dielectric coefficient medium layer 103, and removes remaining second photoresist 108 and the anti-anti-erosion agent layer 107 in bottom;
Step S7: continue etching low dielectric constant dielectric layer 103 and via etch barrier layer 102 through partial through holes structure 200a and 200b; Expose the active area metal silicide 101a on the silicon substrate 101, form in the vertical direction and run through the through-hole structure 2001 and 2002 in metal hard mask layer 106, low dielectric coefficient medium layer 103 and the via etch barrier layer 102;
Step S8: on metal hard mask layer 106 and the sidewall of through-hole structure 2001 and 2002 and deposit metal barrier and copper seed layer; And adopt electrochemistry plating ECP technology growing metal copper 109, make metallic copper 109 be filled in groove 100 and the through-hole structure 2001 and 2002;
Step S9: carry out chemical mechanical milling tech, remove unnecessary metallic copper 109.
Further, the material that constitutes said via etch barrier layer is SiCN.
Further, the material of formation low dielectric coefficient medium layer is SiOCH.
Further, the material of formation dielectric protection layer is SiO
2
Further,, the material that constitutes metal hard mask layer is Ta or TaN or Ti or TiN.
In sum, the integrated approach of a kind of dual damascene of the present invention uses the Damascus manufacturing process of through hole behind the first groove; And the hard mask of at first deposit layer of metal when forming through hole; Can effectively avoid leakage current and the generation of the interconnection phenomenon between the adjacent through-holes between the adjacent through-holes, reduce the control difficulty of through hole critical size in the advanced copper wiring, and improved the Performance And Reliability of semiconductor device; Technical process is simple and easy to control, is suitable for penetration and promotion and is suitable for.
Should be pointed out that foregoing is enumerating of specific embodiment of the present invention, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; And above-mentioned specific embodiment is not to be used for limiting practical range of the present invention, and promptly all equivalent transformation and modifications of doing according to content of the patent of the present invention all fall into protection scope of the present invention.
Claims (10)
1. the integrated approach of a dual damascene is characterized in that, comprises the steps:
Step S1 a: silicon substrate is provided, is formed with completed anterior layer metal level on the said silicon substrate, on said silicon substrate, be deposited with via etch barrier layer, dielectric layer with low dielectric constant and dielectric protection layer from bottom to up successively;
Step S2: on said dielectric protection layer, apply one deck photoresist, and carry out photoetching process, form groove opening;
Step S3: with the photoresist is mask; Through said dielectric protection layer of said groove opening etching successively and said dielectric layer with low dielectric constant; And etching stopping is in said dielectric layer with low dielectric constant; Formation runs through the groove of said dielectric protection layer and said dielectric layer with low dielectric constant, and removes photoresist;
Step S4: on said dielectric protection layer and the sidewall of said groove and deposit layer of metal hard mask layer, and on said metal hard mask layer the anti-anti-erosion agent layer in deposit bottom;
Step S5: on the anti-anti-erosion agent layer in said bottom, apply one second photoresist, and carry out photoetching, form the via openings that is arranged in said second photoresist, wherein, the width of said opening has defined the width of the through hole of follow-up formation;
Step S6: with said second photoresist is mask; Through the anti-anti-erosion agent layer in the said bottom of said via openings etching successively and said metal hard mask layer and low dielectric coefficient medium layer; And etching stopping is in low dielectric coefficient medium layer; Formation is arranged in the partial through holes structure of said metal hard mask layer and said low dielectric coefficient medium layer, and removes the anti-anti-erosion agent layer of remaining photoresist and bottom;
Step S7: continue said low dielectric coefficient medium layer of etching and said via etch barrier layer through the partial through holes structure; Expose the completed anterior layer metal level on the said silicon substrate, form in the vertical direction and run through the through-hole structure in said metal hard mask layer, said low dielectric coefficient medium layer and the said via etch barrier layer;
Step S8: on said metal hard mask layer and the sidewall of said through-hole structure and deposit metal barrier and copper seed layer, and adopt electrochemistry plating ECP technology growing metal copper, make metallic copper be filled in said groove and the said through-hole structure;
Step S9: carry out chemical mechanical milling tech, remove unnecessary metallic copper.
2. the method for claim 1 is characterized in that, the material that constitutes said via etch barrier layer is SiCN.
3. according to claim 1 or claim 2 method is characterized in that, adopts the described via etch of chemical meteorology deposition method deposit barrier layer.
4. the method for claim 1 is characterized in that, the material that constitutes low dielectric coefficient medium layer is SiOCH.
5. like claim 1 or 4 described methods, it is characterized in that, adopt the said low dielectric coefficient medium layer of chemical meteorology deposition method deposit.
6. the method for claim 1 is characterized in that, the material that constitutes dielectric protection layer is SiO
2
7. the method for claim 1 is characterized in that, adopts the said dielectric protection layer of chemical vapour deposition technique deposit.
8. the method for claim 1 is characterized in that, the material that constitutes metal hard mask layer is Ta or TaN or Ti or TiN.
9. like claim 1 or 8 described methods, it is characterized in that, adopt chemical vapour deposition technique or the said metal hard mask layer of physical vaporous deposition deposit.
10. the method for claim 1 is characterized in that, the material that constitutes said metal barrier is TaN or Ta.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110265235XA CN102446822A (en) | 2011-09-08 | 2011-09-08 | Integration method of dual Damascus |
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|---|---|---|---|
| CN201110265235XA CN102446822A (en) | 2011-09-08 | 2011-09-08 | Integration method of dual Damascus |
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| CN102446822A true CN102446822A (en) | 2012-05-09 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867810A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Dual damascene structure with porous structure |
| CN102881639A (en) * | 2012-09-17 | 2013-01-16 | 上海华力微电子有限公司 | Method for improving KINK defect in dual damascene process |
| CN109755175A (en) * | 2017-11-03 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | interconnection structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6017817A (en) * | 1999-05-10 | 2000-01-25 | United Microelectronics Corp. | Method of fabricating dual damascene |
| US6211061B1 (en) * | 1999-10-29 | 2001-04-03 | Taiwan Semiconductor Manufactuirng Company | Dual damascene process for carbon-based low-K materials |
| CN1493087A (en) * | 2000-12-26 | 2004-04-28 | ����Τ�����ʹ�˾ | Method for eliminating reaction between photoresist and organosilicate glass (OSG) |
-
2011
- 2011-09-08 CN CN201110265235XA patent/CN102446822A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6017817A (en) * | 1999-05-10 | 2000-01-25 | United Microelectronics Corp. | Method of fabricating dual damascene |
| US6211061B1 (en) * | 1999-10-29 | 2001-04-03 | Taiwan Semiconductor Manufactuirng Company | Dual damascene process for carbon-based low-K materials |
| CN1493087A (en) * | 2000-12-26 | 2004-04-28 | ����Τ�����ʹ�˾ | Method for eliminating reaction between photoresist and organosilicate glass (OSG) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867810A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Dual damascene structure with porous structure |
| CN102881639A (en) * | 2012-09-17 | 2013-01-16 | 上海华力微电子有限公司 | Method for improving KINK defect in dual damascene process |
| CN102867810B (en) * | 2012-09-17 | 2015-06-03 | 上海华力微电子有限公司 | Dual damascene structure with porous structure |
| CN109755175A (en) * | 2017-11-03 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | interconnection structure and forming method thereof |
| CN109755175B (en) * | 2017-11-03 | 2021-08-06 | 中芯国际集成电路制造(上海)有限公司 | Interconnect structure and method of forming the same |
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Application publication date: 20120509 |