CN102426858A - Method and system for detecting leakage current of storage units - Google Patents
Method and system for detecting leakage current of storage units Download PDFInfo
- Publication number
- CN102426858A CN102426858A CN201110391548XA CN201110391548A CN102426858A CN 102426858 A CN102426858 A CN 102426858A CN 201110391548X A CN201110391548X A CN 201110391548XA CN 201110391548 A CN201110391548 A CN 201110391548A CN 102426858 A CN102426858 A CN 102426858A
- Authority
- CN
- China
- Prior art keywords
- storage unit
- bln
- circuit
- bit line
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention discloses a method for detecting leakage current of storage units. The method is applied in and at least comprises a first storage unit, a second storage unit and a third storage unit, which are adjacent in sequence and are positioned in the same row of a storage array. The storage units share the same group of word lines. The method comprises the following steps of: gating bit lines among the storage units and a bit line corresponding to a source electrode of the first storage unit simultaneously; by measurement of a measuring circuit, obtaining a second voltage value; obtaining a channel resistance of the first storage unit and the second storage unit by simulation; obtaining a first voltage value corresponding to a level for reading the bit lines by simulation; and obtaining leakage current of the second storage unit by calculation of voltage difference between the first voltage value and the second voltage value and the channel resistance of the second storage unit, i.e. the leakage current when the first storage unit is read. The invention provides a method and system for detecting the leakage current of the storage units, which can realize effective detection of the leakage current of the storage units.
Description
Technical field
The present invention relates to technical field of information storage, the method and system of leakage current when particularly a kind of detection of stored device storage unit reads.
Background technology
The core of whole flash memories is the array that storage unit constitutes; The read method of location information is referring to Fig. 1 in the array; Storage unit is an example with common metal-oxide-semiconductor, and each storage unit (cell) has three ports, and one of them is a control port; The grid that is equivalent to common metal-oxide-semiconductor, all the other two ports are equivalent to the source electrode and the drain electrode of common metal-oxide-semiconductor.The control port of storage unit connects word line, and the control port with delegation's storage unit connects same word line WL1 in the array, and word line potential is just realized the unlatching of storage unit and shutoff.Source electrode with delegation's storage unit in the storage array joins end to end with drain electrode in order, and the source electrode of two adjacent storage unit and drain electrode are connected on the bit line.When storage unit was in opening, equivalence was a resistance; When storage unit institute canned data is " 0 " or when " 1 ", its resistance value is different.Therefore,, need apply potential difference (PD), the canned data of the electric current that reading flow is crossed storage unit in just can reading cells at the two ends that are read storage unit for canned data in the reading cells.
Usually during the information in the reading cells; Storage unit cell2 is an example among Fig. 1 to read; Word line WL1 level is that high back storage unit cell2 opens; Two bit lines BLa and the BLa+1 that bit line strobe unit gating storage unit cell2 source electrode and drain electrode are connected make bit line BLa and BLa+1 be connected low level generation circuit respectively and electric current reads circuit, apply low-voltage and high voltage respectively at bit line BLa and BLa+1; The electric potential difference at storage unit cell2 two ends causes flowing through the current Ib it of storage unit, and the current value that flows through storage unit cell2 is designated as Ibit.Read electric current I and read circuit by electric current and read, read the current value that reads that circuit reads and be designated as I, when I=Ibit, canned data in this current value of reading reflection storage unit.Usually, storage unit cell2 is being carried out in the process of read operation, and do not applying any signal on the bit line BLa+2 that storage unit cell3 is connected.Apply the moment of low-voltage and high voltage signal for bit line BLa and BLa+1, there is electric potential difference in storage unit cell3 two ends, and the grid of storage unit is high, and it will be equivalent to a resistance, and this can cause the generation of leakage current I leak.
The bit line strobe unit is R1 to the resistance of every bit line on average; Every bit line is C with respect to the electric capacity on ground; Referring to Fig. 2, need electric current to read circuit and be charged to the high voltage that can carry out read operation for bit line BLa+1, just can the information of carrying out read; When not having leakage current I leak, electric current reads circuit, and to give end points D be the product that the time T 1 of bit line BLa+1 charging is proportional to resistance R 1 and C.But the existence of leakage current I leak makes electric charge be delivered to bit line BLa+2 from bit line BLa+1 and gives bit line BLa+2 charging; Be that the high voltage that bit line BLa+1 applies can charge to D, 2 current potentials of A simultaneously; Duration of charging T2 is proportional to the product of resistance R 1 and 2C, delays bit line BLa+1 and arrives the required high-tension time.Read operation reads between time T 1 and the T2 of circuit after beginning high voltage is provided at electric current and carries out; Be under the situation of Ileak existence; The virtual voltage of bit line BLa+1 is not charged to required voltage, reads current precision and is affected, even cause reading information errors.
Along with the increase of high density storage array demand, virtual earth (virtual ground) structure storage array is by being applicable in the memory storage more and more widely.The principal character of virtual address structure storage array comprises: the storage unit of the bit line connectivity port of every array storage unit and adjacent columns is shared same bit lines in the virtual address structure storage array.
Fig. 3 is the rough schematic that prior art is carried out read operation; So that cell1 (first storage unit) is carried out read operation is example: word line is opened cell1; Cell2, cell3, bit line BL (n), BL (n+1), BL (n+2), BL (n+3) are by gating; (figure neutrality line BL (n), BL (n+1), BL (n+2), BL (n+3) exist electric capacity and the resistance that is connected to ground, thereby can produce leakage current).BL (n) is the source electrode of array element Cell1, and low level voltage is provided; BL (n+1) is its drain electrode, provides high level to read voltage A; BL (n+2) is floating empty, and any signal is not provided; BL (n+3) is provided high level signal B, and this signal is in order to reduce the leakage current I leak (being generally instantaneous value) from BL (n+1) to BL (n+3).Because; The grid of Cell1 (promptly connecting word line) is applied in high level with other storage unit with delegation, and it is in opening; It can equivalence be a resistance, and there are electric potential difference in the source electrode of Cell1 and drain electrode, and this will bring the current Ib it that flows through cell1.Through reading flow through the reference current Iref of the electric current I of BL (n+1) and setting compare (for example I than Iref big we define the cell1 canned data and be " 0 "); Can judge the content (" 0 " is " 1 " perhaps) of the storage of Cell1, promptly accomplish the read operation of array element cell1.Memory array is carried out in the process of read operation owing to produce leakage current Ileak, the excessive accuracy that may influence reading of data of its value, thus need measure the leakage current signal.
Common testing apparatus (voltage table, reometer etc.) generally can only obtain quiescent value when chip testing, be difficult to obtain instantaneous value; General testing apparatus signal distortion also occurs when measuring easily, is subject to noise.Therefore, need a kind of can satisfy can the detected transient leakage current time testing apparatus of low noise, high input impedance, suitable characteristics such as passband, electrical isolation and protection and suitable detection method.
Therefore, how the method and system of a kind of effective detection of stored unit leakage current being provided, is those skilled in the art's technical issues that need to address.
Summary of the invention
The technical matters that the present invention will solve provides the method and system of a kind of detection of stored unit leakage current, can realize effective detection of cell leakage current.
The present invention provides the method for a kind of detection of stored unit leakage current, is applied to comprise at least adjacent successively and first storage unit, second storage unit and the 3rd storage unit that be positioned at the same row of storage array, the shared same group of word line of said memory cells;
Said method comprising the steps of:
The bit line (BLn+1, BLn+2) between the while gating said memory cells and the source electrode corresponding bit lines (BLn) of said first storage unit; Wherein
On the said first cell source corresponding bit lines (BLn), apply low level; The bit line (BLn+1) at said first storage unit drain electrode place is gone up and is connected the level that is used for read operation, goes up in said second storage unit drain electrode corresponding bit lines (BLn+2) to connect test circuit;
Said test circuit measures the second magnitude of voltage V BLn+2;
Obtain channel resistance RCell 1, the RCell 2 of said first, second storage unit through emulation;
Obtain to read the first corresponding magnitude of voltage VBLn+1 of level of said bit line (BLn+1) through emulation;
It is the leakage current Ileak1 of said first storage unit when being read that the voltage difference through the first magnitude of voltage VBLn+1 and the second magnitude of voltage VBLn+2 and the channel resistance RCell 2 of said second storage unit calculate said second drain current of storage of flowing through.
Preferably, comprising: the leakage current Ileak2 when the leakage current Ileak1 assignment when said first storage unit is read is read for said second storage unit, i.e. Ileak2=Ileak1.
Preferably, comprise that also the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit connects voltage follower circuit, first storage unit reads the leakage current that level applies side when being used to reduce to read;
The bit line (BLn+1, BLn+2) between the control while gating said memory cells and the source electrode corresponding bit lines (BLn) of said first storage unit, and the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit.
Preferably, said test circuit specifically measures the second magnitude of voltage V BLn+2 through testing apparatus.
Preferably, said testing apparatus comprises prime amplifier, Hi-pass filter, isolated amplifier, the low-pass filter that links to each other successively.
Preferably; Before the said generation circuit that is used for the level of read operation promptly reads level generation circuit working; Said testing apparatus is in the test opening, and when the generation circuit working of the said level that is used for read operation, said testing apparatus is sampled and exported display device to.
Preferably, said channel resistance RCell 1 step that obtains said first storage unit through emulation is specially:
Integrated circuit simulating program electrical model through the storage unit in CMOS and the storage array; It is a setting value that VBLn+1 is set in emulation, tries to achieve the channel resistance RCell 1 of said first storage unit through integrated circuit simulating procedure simulation instrument according to the integrated circuit simulating procedural model of the storage unit in the storage array.
The present invention also provides the system of a kind of detection of stored unit leakage current, comprises that memory cell array, at least one low level produce circuit, read level generation circuit, test circuit, bit line strobe unit, word line strobe unit;
The said level that reads produces the voltage that circuit provides, and is higher than said low level and produces the voltage that circuit provides; Said low level produces circuit, read level produces circuit the circuit synchronous working is provided;
Said memory cell array comprises adjacent successively and first storage unit, second storage unit and the 3rd storage unit that be positioned at the same row of storage array at least;
Said word line strobe unit gating comprises adjacent successively and word line that be positioned at first storage unit, second storage unit and the 3rd storage unit of the same row of storage array at least;
The bit line (BLn+1, BLn+2) between the said bit line strobe unit while gating said memory cells and the source electrode corresponding bit lines (BLn) of said first storage unit;
Said low level produces circuit and is connected with the said first cell source corresponding bit lines (BLn) through the bit line strobe unit; The said level generation circuit that reads is connected through the bit line (BLn+1) that bit line strobe unit and the drain electrode of said first storage unit belong to; Said test circuit is connected through bit line strobe unit and said second storage unit drain electrode corresponding bit lines (BLn+2) and measures the second magnitude of voltage V BLn+2.
Preferably, said system also comprises voltage follower circuit, and said voltage follower circuit is connected with the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit through the bit line strobe unit;
The bit line (BLn+1, BLn+2) between the said bit line strobe unit while gating said memory cells and the source electrode corresponding bit lines (BLn) of said first storage unit, and the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit.
Preferably, said test circuit specifically measures the second magnitude of voltage V BLn+2 through testing apparatus.
Preferably, said read level and produce circuit working before, said testing apparatus is in the test opening, when the generation circuit of the said level that is used for read operation, said testing apparatus is sampled and is exported display device to.
Compared with prior art, the present invention has the following advantages:
The method of the said detection of stored of embodiment of the invention unit leakage current comprises adjacent successively and first storage unit, second storage unit and the 3rd storage unit that be positioned at the same row of storage array, the shared same group of word line of said memory cells at least; The source electrode corresponding bit lines BLn of bit line BLn+1, BLn+2 and said first storage unit between the while gating said memory cells and the drain electrode corresponding bit lines BLn+3 of said the 4th storage unit; Said test circuit measures the second magnitude of voltage V BLn+2; Obtain channel resistance RCell 1, the RCell 2 of said first, second storage unit through emulation; Read the level VBLn+1 of the bit line BLn+1 at said first storage unit drain electrode place; Calculate the said second drain current of storage Ileak2 through the voltage difference of the first magnitude of voltage VBLn+1 and the second magnitude of voltage VBLn+2 and the channel resistance RCell 2 of said second storage unit; Give the said first drain current of storage Ileak1 with the said second drain current of storage Ileak2 assignment.The method of detection of stored provided by the invention unit leakage current is through 4 adjacent strip bit lines of while gating; And wherein one as test port; The voltage of the bit line that is specifically connected through voltage tester device measuring test port; And the ratio of the channel resistance through calculating voltage difference and storage unit obtains leakage current, is a kind of single test port memory array leakage current testing scheme with general applied value.Thereby realize the dynamic drain current value of assessment memory array.
Description of drawings
Fig. 1 reads the synoptic diagram of a storage unit for existing cells of memory arrays information-reading method;
Bit line capacitance synoptic diagram when Fig. 2 reads for existing cells of memory arrays information;
Fig. 3 carries out the rough schematic of read operation for prior art;
Fig. 4 is the method flow diagram of the said detection of stored of embodiment of the invention unit leakage current;
Fig. 5 is the system construction drawing of the said detection of stored of embodiment of the invention unit leakage current;
Fig. 6 is the circuit diagram of the said testing apparatus of the embodiment of the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Referring to Fig. 4, this figure is the method flow diagram of the said detection of stored of embodiment of the invention unit leakage current.
Leakage current when the method for the said detection of stored of embodiment of the invention unit leakage current is used to detect first storage unit and is read.
The method of the said detection of stored of embodiment of the invention unit leakage current is applied to comprise at least the first storage unit Cell 1, the second storage unit Cell 2 and the 3rd storage unit Cell 3 adjacent successively and that be positioned at the same row of storage array, the shared same group of word line of said memory cells.
The method of the said detection of stored of embodiment of the invention unit leakage current comprises:
S100, bit line (BLn+1, BLn+2) and the source electrode corresponding bit lines (BLn) of the said first storage unit Cell 1 and the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit Cell 4 between the gating first storage unit Cell 1, the second storage unit Cell 2 and the 3rd storage unit Cell 3 simultaneously.
Wherein, On the said first storage unit Cell, 1 source electrode corresponding bit lines BLn, apply low level; The bit line BLn+1 at the said first storage unit Cell 1 drain electrode place goes up and connects the level that is used for read operation, on the said second storage unit Cell, 2 drain electrode corresponding bit lines BLn+2, connects test circuit.
S200, test circuit measure the second magnitude of voltage V BLn+2.
Said test circuit specifically can measure the second magnitude of voltage V BLn+2 through testing apparatus.
Referring to Fig. 6, said testing apparatus comprises prime amplifier, Hi-pass filter, isolated amplifier, the low-pass filter that links to each other successively.Prime amplifier can adopt IC chip AD620, INA118 etc.Wave filter can adopt the structure of dual operational amplifier and resistance.Isolated amplifier adopts the amplifier of high-gain high bandwidth.Said testing apparatus adopts this circuit to do the voltage transmission circuit, and low noise, high input impedance, suitable advantages such as passband, electrical isolation and protection are arranged.
Before the said generation circuit that is used for the level of read operation promptly reads level generation circuit working; Said testing apparatus is in the test opening; When the generation circuit working of the said level that is used for read operation, said testing apparatus is sampled and is exported display device to.Display device specifically can be devices such as oscillograph.
S300, obtain said first, second storage unit Cell 1, the channel resistance RCell 1 of Cell 2, RCell 2 through emulation.
The said channel resistance RCell 1 that obtains the said first storage unit Cell 1 through emulation specifically may further comprise the steps:
Through CMOS (Complementary Metal Oxide Semiconductor; Complementary metal oxide semiconductor (CMOS)) and the spice of the storage unit Cell in the storage array (Simulation Program with Integrated Circuit Emphasis; The integrated circuit simulating program) electrical model; It is a settings (said setting value is that empirical value generally can be set at about 1v) that VBLn+1 is set in emulation, can try to achieve the channel resistance RCell 1 of the said first storage unit Cell 1 through the spice emulation tool according to the spice model of the storage unit Cell in the storage array.
In like manner can try to achieve the channel resistance RCell 2 of the second storage unit Cell 2.
Through CMOS (Complementary Metal Oxide Semiconductor; Complementary metal oxide semiconductor (CMOS)) and the spice of the storage unit Cell in the storage array (Simulation Program with Integrated Circuit Emphasis; The integrated circuit simulating program) electrical model; It is a setting value (said setting value is that empirical value generally can be for about 1v) that VBLn+2 is set in emulation, can try to achieve the channel resistance RCell 1 of the said second storage unit Cell2 through the spice emulation tool according to the spice model of the storage unit Cell in the storage array.
S400, obtain to read the first corresponding magnitude of voltage VBLn+1 of level of said bit line (BLn+1) through emulation.
Emulation in like manner can be tried to achieve the first magnitude of voltage VBLn+ 1.
Through CMOS (Complementary Metal Oxide Semiconductor; Complementary metal oxide semiconductor (CMOS)) and the spice of the storage unit Cell in the storage array (Simulation Program with Integrated Circuit Emphasis; The integrated circuit simulating program) electrical model; It is a setting value (said setting value is that empirical value generally can be for about 1v) that VBLn+1 is set in emulation, can try to achieve the first corresponding magnitude of voltage VBLn+1 of level of said bit line (BLn+1) through the spice emulation tool according to the spice model of the storage unit Cell in the storage array.
The leakage current Ileak1 that the channel resistance RCell 2 of S500, the voltage difference through the first magnitude of voltage VBLn+1 and the second magnitude of voltage VBLn+2 and the said second storage unit Cell2 calculates the said second storage unit Cell2 that flows through is the leakage current of said first storage unit when being read.
Said computing formula is: the channel resistance RCell 2 of voltage difference/storage unit of the leakage current Ileak1=first magnitude of voltage VBLn+1 and the second magnitude of voltage VBLn+ 2.
Leakage current when being read in order to obtain second storage unit, said method can comprise:
S600, when said first storage unit is read the leakage current Ileak2 of leakage current Ileak1 assignment when being read for said second storage unit.Be Ileak2=Ileak1.
Because the leakage current Ileak1 when the first storage unit cell1 between bit line BLn and the bit line BLn+ 1 is read approximates the leakage current Ileak2 of the second storage unit cell2 between bit line BLn+1 and the bit line BLn+2.Therefore, leakage current Ileak1 when the leakage current Ileak2 in the time of can the said second storage unit Cell2 being read is read through the said first storage unit Cell of assignment obtains, the leakage current Ileak2 when obtaining the said second storage unit Cell2 and being read.
The method of detection of stored provided by the invention unit leakage current specifically can be through 4 adjacent strip bit lines of while gating; And wherein one as test port; The voltage of the bit line that is specifically connected through voltage tester device measuring test port; And the ratio of the channel resistance through calculating voltage difference and storage unit obtains leakage current, realizes the dynamic drain current value of assessment memory array.The method of detection of stored provided by the invention unit leakage current is a kind of single test port memory array leakage current testing scheme with general applied value.
Referring to Fig. 5; In this programme; Test lead bit line (BLn+2) is on the right side of the bit line that is read (BLn+1); The magnitude of voltage VBLn+2 of testing apparatus probing test end A place bit line (BLn+2), because the channel resistance RCell of Flash Cell and the level of reading bit line (BLn+1), VBLn+1 can obtain through means such as emulation.The leakage current Ileak1 of the storage unit cell2 between bit line BLn+1 and the BLn+2 of flowing through can calculate acquisitions through the voltage difference and the second storage unit cell2 channel resistance RCell 2 of VBLn+1 and VBLn+2.And the leakage current Ileak1 of the first storage unit cell1 between bit line BLn and the BLn+1 when being read is exactly the leakage current Ileak1 of storage unit cell2 of flowing through.Therefore just can accurately judge the size of Ileak1 through the magnitude of voltage VBLn+2 of test b Ln+2.
The method of detection of stored provided by the invention unit leakage current can be connected with voltage follower circuit in the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit, and the said voltage follower circuit electric current that mainly high level signal A (A point shown in Figure 5 is a high level signal) produces in order to prevent to read flows through second follow-up storage unit Cell2 and the 3rd storage unit Cell3 etc.The first storage unit Cell1 read the leakage current (leakage current when the first storage unit Cell1 is read) that level applies side when said voltage follower circuit was used to reduce to read.
When the method for detection of stored provided by the invention unit leakage current is connected with voltage follower circuit at the drain electrode corresponding bit lines BLn+ 3 of said the 4th storage unit; Need the control source electrode corresponding bit lines BLn of bit line BLn+ 1, BLn+2 and the said first storage unit Cell 1 between the gating first storage unit Cell1, the second storage unit Cell 2 and the 3rd storage unit Cell 3 simultaneously, and the drain electrode corresponding bit lines BLn+ 3 of said the 4th storage unit Cell4.
Referring to Fig. 5, this figure is the system construction drawing of the said detection of stored of embodiment of the invention unit leakage current.
The system of a kind of detection of stored unit leakage current comprises that memory cell array, at least one low level produce circuit, read level generation circuit, test circuit, bit line strobe unit, word line strobe unit.(not shown among Fig. 5)
The said level that reads produces the voltage that circuit provides, and is higher than said low level and produces the voltage that circuit provides; Said low level produces circuit, read level produces circuit the circuit synchronous working is provided;
Said memory cell array comprises adjacent successively and the first storage unit Cell1, the second storage unit Cell2 and the 3rd storage unit Cell3 that be positioned at the same row of storage array at least.
Said word line strobe unit gating comprises adjacent successively and word line Cell3 that be positioned at the first storage unit Cell1, the second storage unit Cell2 and the 3rd storage unit of the same row of storage array at least;
Said bit line strobe unit (according to bit line gating control signal) is the gating said memory cells simultaneously---bit line (BLn+1, BLn+2) between the word line Cell3 of the first storage unit Cell1, the second storage unit Cell2 and the 3rd storage unit and the source electrode corresponding bit lines (BLn) of the said first storage unit Cell1;
Said low level produces circuit and is connected with the said first storage unit Cell1 source electrode corresponding bit lines (BLn) through the bit line strobe unit; The said level generation circuit that reads is connected through the bit line (BLn+1) of bit line strobe unit with said first storage unit Cell1 drain electrode place; Said test circuit is connected with said second storage unit Cell2 drain electrode corresponding bit lines (BLn+2) through the bit line strobe unit and measures the second magnitude of voltage V BLn+ 2.
Obtain said first, second storage unit Cell 1, the channel resistance RCell 1 of Cell 2, RCell 2 as preamble is said through emulation.
Like the said first corresponding magnitude of voltage VBLn+1 of level that obtains to read said bit line (BLn+1) through emulation of preamble.
Leakage current Ileak1 that computing formula calculates the said second storage unit Cell2 that obtains to flow through be installed be the leakage current Ileak1 of said first storage unit when being read.
Computing formula is: the channel resistance RCell 2 of voltage difference/storage unit of the leakage current Ileak1=first magnitude of voltage VBLn+1 and the second magnitude of voltage VBLn+ 2.
The said system of the embodiment of the invention is through 4 adjacent strip bit lines of while gating; And wherein one as test port; The voltage of the bit line that is specifically connected through voltage tester device measuring test port; And the ratio of the channel resistance through calculating voltage difference and storage unit obtains leakage current, realizes the dynamic drain current value of assessment memory array.The system of detection of stored provided by the invention unit leakage current is a kind of single test port memory array leakage current testing scheme with general applied value.
Because the leakage current Ileak1 when the first storage unit cell1 between bit line BLn and the bit line BLn+ 1 is read approximates the leakage current Ileak2 of the second storage unit cell2 between bit line BLn+1 and the bit line BLn+2.Therefore, leakage current Ileak1 when the leakage current Ileak2 in the time of can the said second storage unit Cell2 being read is read through the said first storage unit Cell of assignment obtains, the leakage current Ileak2 when obtaining the said second storage unit Cell2 and being read.
The electric current that high level signal A (A point shown in Figure 5 is a high level signal) produces in order to prevent to read flows through second follow-up storage unit Cell2 and the 3rd storage unit Cell3 etc.The said system of the embodiment of the invention also comprises voltage follower circuit, and said voltage follower circuit is connected with the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit through the bit line strobe unit.
The first storage unit Cell1 read the leakage current (leakage current when the first storage unit Cell1 is read) that level applies side when said voltage follower circuit was used to reduce to read.
Said with preamble, said test circuit is specifically measured (referring to Fig. 6) through testing apparatus and is obtained the second magnitude of voltage V BLn+ 2.
Said read level and produce circuit working before, said testing apparatus is in the test opening, when the generation circuit of the said level that is used for read operation, said testing apparatus is sampled and is exported display device (like oscillograph etc.) to.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (11)
1. the method for a detection of stored unit leakage current is characterized in that, is applied to comprise at least adjacent successively and first storage unit, second storage unit and the 3rd storage unit that be positioned at the same row of storage array, the shared same group of word line of said memory cells;
Said method comprising the steps of:
The bit line (BLn+1, BLn+2) between the while gating said memory cells and the source electrode corresponding bit lines (BLn) of said first storage unit; Wherein
On the said first cell source corresponding bit lines (BLn), apply low level; The bit line (BLn+1) at said first storage unit drain electrode place is gone up and is connected the level that is used for read operation, goes up in said second storage unit drain electrode corresponding bit lines (BLn+2) to connect test circuit;
Said test circuit measures the second magnitude of voltage V BLn+2;
Obtain channel resistance RCell 1, the RCell 2 of said first, second storage unit through emulation;
Obtain to read the first corresponding magnitude of voltage VBLn+1 of level of said bit line (BLn+1) through emulation;
It is the leakage current Ileak1 of said first storage unit when being read that the voltage difference through the first magnitude of voltage VBLn+1 and the second magnitude of voltage VBLn+2 and the channel resistance RCell 2 of said second storage unit calculate said second drain current of storage of flowing through.
2. method according to claim 1 is characterized in that, comprising:
Leakage current Ileak2 when the leakage current Ileak1 assignment when said first storage unit is read is read for said second storage unit, i.e. Ileak2=Ileak1.
3. method according to claim 1 and 2 is characterized in that, comprises that also the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit connects voltage follower circuit, and first storage unit reads the leakage current that level applies side when being used to reduce to read;
The bit line (BLn+1, BLn+2) between the control while gating said memory cells and the source electrode corresponding bit lines (BLn) of said first storage unit, and the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit.
4. method according to claim 3 is characterized in that, said test circuit specifically measures the second magnitude of voltage V BLn+2 through testing apparatus.
5. method according to claim 4 is characterized in that, said testing apparatus comprises prime amplifier, Hi-pass filter, isolated amplifier, the low-pass filter that links to each other successively.
6. method according to claim 5; It is characterized in that; Before the said generation circuit that is used for the level of read operation promptly reads level generation circuit working; Said testing apparatus is in the test opening, and when the generation circuit working of the said level that is used for read operation, said testing apparatus is sampled and exported display device to.
7. method according to claim 1 is characterized in that, said channel resistance RCell 1 step that obtains said first storage unit through emulation is specially:
Integrated circuit simulating program electrical model through the storage unit in CMOS and the storage array; It is a setting value that VBLn+1 is set in emulation, tries to achieve the channel resistance RCell 1 of said first storage unit through integrated circuit simulating procedure simulation instrument according to the integrated circuit simulating procedural model of the storage unit in the storage array.
8. the system of a detection of stored unit leakage current is characterized in that,
Comprise that memory cell array, at least one low level produce circuit, read level generation circuit, test circuit, bit line strobe unit, word line strobe unit;
The said level that reads produces the voltage that circuit provides, and is higher than said low level and produces the voltage that circuit provides; Said low level produces circuit, read level produces circuit the circuit synchronous working is provided;
Said memory cell array comprises adjacent successively and first storage unit, second storage unit and the 3rd storage unit that be positioned at the same row of storage array at least;
Said word line strobe unit gating comprises adjacent successively and word line that be positioned at first storage unit, second storage unit and the 3rd storage unit of the same row of storage array at least;
The bit line (BLn+1, BLn+2) between the said bit line strobe unit while gating said memory cells and the source electrode corresponding bit lines (BLn) of said first storage unit;
Said low level produces circuit and is connected with the said first cell source corresponding bit lines (BLn) through the bit line strobe unit; The said level generation circuit that reads is connected through the bit line (BLn+1) that bit line strobe unit and the drain electrode of said first storage unit belong to; Said test circuit is connected through bit line strobe unit and said second storage unit drain electrode corresponding bit lines (BLn+2) and measures the second magnitude of voltage V BLn+2.
9. system according to claim 8 is characterized in that said system also comprises voltage follower circuit, and said voltage follower circuit is connected with the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit through the bit line strobe unit;
The bit line (BLn+1, BLn+2) between the said bit line strobe unit while gating said memory cells and the source electrode corresponding bit lines (BLn) of said first storage unit, and the drain electrode corresponding bit lines (BLn+3) of said the 4th storage unit.
10. method according to claim 8 is characterized in that, said test circuit specifically measures the second magnitude of voltage V BLn+2 through testing apparatus.
11. method according to claim 10; It is characterized in that, said read level and produce circuit working before, said testing apparatus is in the test opening; When the generation circuit of the said level that is used for read operation, said testing apparatus is sampled and is exported display device to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110391548.XA CN102426858B (en) | 2011-11-30 | 2011-11-30 | Method and system for detecting leakage current of storage units |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110391548.XA CN102426858B (en) | 2011-11-30 | 2011-11-30 | Method and system for detecting leakage current of storage units |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102426858A true CN102426858A (en) | 2012-04-25 |
| CN102426858B CN102426858B (en) | 2014-07-23 |
Family
ID=45960830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110391548.XA Active CN102426858B (en) | 2011-11-30 | 2011-11-30 | Method and system for detecting leakage current of storage units |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102426858B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110286293A (en) * | 2019-07-25 | 2019-09-27 | 云南电网有限责任公司电力科学研究院 | A kind of self-energizing electric leakage monitoring method and system based on leakage current |
| CN110286294A (en) * | 2019-07-25 | 2019-09-27 | 云南电网有限责任公司电力科学研究院 | A kind of self-energizing device and method for monitoring of leaking electricity |
| CN113192549A (en) * | 2021-05-14 | 2021-07-30 | 长江存储科技有限责任公司 | Three-dimensional memory, detection device, three-dimensional memory device and detection method |
| WO2022198903A1 (en) * | 2021-03-23 | 2022-09-29 | 长鑫存储技术有限公司 | Detection method and detection apparatus for memory |
| US11609705B2 (en) | 2021-03-23 | 2023-03-21 | Changxin Memory Technologies, Inc. | Memory detection method and detection apparatus |
| WO2023159714A1 (en) * | 2022-02-24 | 2023-08-31 | 长鑫存储技术有限公司 | Detection method for leakage current of memory |
| US11990174B2 (en) | 2022-02-24 | 2024-05-21 | Changxin Memory Technologies, Inc. | Method for detecting memory device, computer storage medium, and electronic device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378273A (en) * | 2001-03-30 | 2002-11-06 | 华邦电子股份有限公司 | Method for modularizing integrated circuit of DRAM unit |
| US20030214844A1 (en) * | 2002-05-15 | 2003-11-20 | Fujitsu Limited | Nonvolatile semiconductor memory device of virtual-ground memory array with reliable data reading |
| US20040190351A1 (en) * | 2003-03-24 | 2004-09-30 | Kabushiki Kaisha Toshiba | Leak immune semiconductor memory |
| US20050248976A1 (en) * | 2004-05-06 | 2005-11-10 | Chien-Hua Huang | Dynamic random access memory cell leakage current detector |
| EP1612806A2 (en) * | 2004-07-02 | 2006-01-04 | Sharp Kabushiki Kaisha | Semiconductor memory device |
| CN101226778A (en) * | 2007-01-16 | 2008-07-23 | 松下电器产业株式会社 | Semiconductor memory having function to determine semiconductor low current |
| US20100302866A1 (en) * | 2009-05-29 | 2010-12-02 | Jae Won Cha | Method of testing for a leakage current between bit lines of nonvolatile memory device |
-
2011
- 2011-11-30 CN CN201110391548.XA patent/CN102426858B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378273A (en) * | 2001-03-30 | 2002-11-06 | 华邦电子股份有限公司 | Method for modularizing integrated circuit of DRAM unit |
| US20030214844A1 (en) * | 2002-05-15 | 2003-11-20 | Fujitsu Limited | Nonvolatile semiconductor memory device of virtual-ground memory array with reliable data reading |
| US20040190351A1 (en) * | 2003-03-24 | 2004-09-30 | Kabushiki Kaisha Toshiba | Leak immune semiconductor memory |
| US20050248976A1 (en) * | 2004-05-06 | 2005-11-10 | Chien-Hua Huang | Dynamic random access memory cell leakage current detector |
| EP1612806A2 (en) * | 2004-07-02 | 2006-01-04 | Sharp Kabushiki Kaisha | Semiconductor memory device |
| CN101226778A (en) * | 2007-01-16 | 2008-07-23 | 松下电器产业株式会社 | Semiconductor memory having function to determine semiconductor low current |
| US20100302866A1 (en) * | 2009-05-29 | 2010-12-02 | Jae Won Cha | Method of testing for a leakage current between bit lines of nonvolatile memory device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110286293A (en) * | 2019-07-25 | 2019-09-27 | 云南电网有限责任公司电力科学研究院 | A kind of self-energizing electric leakage monitoring method and system based on leakage current |
| CN110286294A (en) * | 2019-07-25 | 2019-09-27 | 云南电网有限责任公司电力科学研究院 | A kind of self-energizing device and method for monitoring of leaking electricity |
| WO2022198903A1 (en) * | 2021-03-23 | 2022-09-29 | 长鑫存储技术有限公司 | Detection method and detection apparatus for memory |
| US11609705B2 (en) | 2021-03-23 | 2023-03-21 | Changxin Memory Technologies, Inc. | Memory detection method and detection apparatus |
| CN113192549A (en) * | 2021-05-14 | 2021-07-30 | 长江存储科技有限责任公司 | Three-dimensional memory, detection device, three-dimensional memory device and detection method |
| CN113192549B (en) * | 2021-05-14 | 2022-05-20 | 长江存储科技有限责任公司 | Three-dimensional memory, detection device, three-dimensional memory device and detection method |
| WO2023159714A1 (en) * | 2022-02-24 | 2023-08-31 | 长鑫存储技术有限公司 | Detection method for leakage current of memory |
| US11990174B2 (en) | 2022-02-24 | 2024-05-21 | Changxin Memory Technologies, Inc. | Method for detecting memory device, computer storage medium, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102426858B (en) | 2014-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102426858B (en) | Method and system for detecting leakage current of storage units | |
| CN105548895B (en) | A kind of battery performance test method and device | |
| CN103278693A (en) | Probe contact resistance measuring method | |
| CN101783183A (en) | Current-limiting circuit for testing performance indexes of resistive random access memory (RRAM) | |
| CN103631690A (en) | Electric power collecting and copying device RS485 interface handheld type tester and testing method thereof | |
| CN109961823A (en) | Test macro and its operating method | |
| CN102436850B (en) | Method for detecting interference of reading operation on neighboring cell | |
| CN108051722A (en) | The lifetime estimation method and system of hot carrier injection effect | |
| CN104991214A (en) | Digital integrated circuit direct current parameter standard reproducing method and standard apparatus | |
| CN104390728B (en) | Measuring method for thermocouple weldering before spacecraft thermal test even correctness | |
| CN105093087A (en) | ESD characteristic test system | |
| CN103063976A (en) | Method and system of fault detection of silicon through holes by using bisection method | |
| CN101571570B (en) | Testing method of continuity of integrated circuit and measuring method of contact resistance of integrated circuit | |
| CN111693821A (en) | Testing method and device for traveling wave fault location device of cable-overhead mixed line | |
| CN113156242A (en) | Relay protection outlet matrix detection equipment | |
| CN106200623B (en) | The semi-physical simulation test device of reactor core measuring system logic module | |
| CN102426859B (en) | Method for detecting reading speed interference, and method for detecting programming interference | |
| CN104637541B (en) | Method for testing memory | |
| CN216646688U (en) | Volt-ampere characteristic analysis and test device for semiconductor laser | |
| CN109900970A (en) | A kind of multi channel detector capacitor automatic measurement system | |
| CN102426860B (en) | Method for detecting interference of programming operation with adjacent storage unit | |
| CN204334563U (en) | A kind of device of automatic detection LVDS signalling channel number | |
| CN103714863B (en) | System and method for testing distribution of current of flash memory unit | |
| CN105301320A (en) | Alternating current impedance bridge | |
| CN102982847A (en) | Testing system and testing method for parasitic parameters of static random access memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |