CN102421022A - Multipath digital television descrambling interface chip and digital television signal monitoring equipment - Google Patents
Multipath digital television descrambling interface chip and digital television signal monitoring equipment Download PDFInfo
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Abstract
The invention relates to a multipath digital television descrambling interface chip and digital television signal monitoring equipment, aiming to increase the integration degree for digital television descrambling and simultaneously descramble at least two paths digital television signals. The chip comprises an I2C (Inter Integrated Circuit) control interface, a TS (Transport Stream) interface, a PCMCIA (Personal Computer Memory Card International Association) bus interface, and a TS selection module, wherein the TS interface and the PCMCIA bus interface constitute a physical link layer of a DVB-CI (Digital Video Broadcasting-Common Interface ); the TS selection module can perform selection on at least two paths of different TS input signals and sending the selected TS input signals to the TS interface; the TS interface processes at least two paths of TS signals; and the PCMCIA bus interface and the TS interface can be externally connected with at least two CAM (Conditional Access Module) cards, and external master control microcomputer can control the at least two paths of CAM cards through the PCMCIA bus interface to complete the descrambling for at least two paths of TS digital television signals. The invention further provides the digital television signal monitoring equipment with application of the chip, and the digital television signal monitoring equipment is used for completing the monitoring for the at least two paths of digital television signals.
Description
Technical field
The present invention relates to the digital television techniques field, be specifically related to a kind of multi-path digital TV descrambling interface chip and digital television signal monitoring equipment.
Background technology
In order to guarantee that DTV can provide information service personalized, secret to the user; And the charge channel of foundation safety; Must adopt condition receiving system (CAS) that DTV is encrypted control, and adopt Conditional Access Module (CAM) card to accomplish the mode of deciphering and realize separation between machine and card, " machine " is that digital television receiver or STB provide functions such as digital television signal reception, decoding, processing; " card " is the CAM card, and functions such as CA system descrambling, deciphering, authentication are provided.
In broadcast television signal monitoring field, the signal that need encrypt operator is deciphered digital signal under the mode that does not adopt digital television or STB, realizes the unified quality-monitoring of multiple signals.Relatively more current at present mode is to adopt the mode and the CAM of devices at full hardware (as: CIMaX chip) to stick into the descrambling that line interface is realized the digital TV encryption program alternately; The TS stream of encrypting is flowed through the TS that becomes non-scrambling after the CA module; This mode is because the restriction of current hardware chip; Flexibility ratio is low, and single chip can't process multi-channel be encrypted the TS signal; Adopt under the mode of a plurality of chips, can cause the veneer volume excessive, integrated level is lower, and cost is higher.Departments such as broadcast television monitoring center, earth station are in order to improve usage ratio of equipment at present; Hope to adopt a set of equipment just can monitor two-way or multi-path digital television high frequency signal; CAM card decryption portion just becomes the bottleneck on the whole monitoring link like this, has reduced the integrated level of monitoring equipment.(annotate: TS stream: Transport Stream transmits stream, and a kind of code stream of Moving Picture Experts Group-2 is a kind of communication protocol that audio-video signal and data are used.）
The CIMaX chip T90FJR of atmel corp's issue discloses a kind of single channel DTV descrambling interface chip, comprises the I2C control interface, is used for the configuration of register in the sheet; The TS stream interface is used to import the TS stream of encryption and the TS stream behind the output descrambling; The pcmcia bus interface is used for resetting, detects the CAM card, receives the interruption of CAM card, and CAM is sticked into capable read-write operation; TS stream interface and pcmcia bus interface constitute the physical link layer of DVB_CI general-purpose interface; Can external CAM card; External main control microprocessor can be accomplished the descrambling of digital television signal through pcmcia bus interface control CAM card; Through the clear stream behind the TS stream interface output descrambling, its shortcoming is exactly low with this device integration of making; Patentee Hengtong Visual Signal Science and Technology Development Co., Ltd., Beijing one Chinese patent application numbers 200710304124.9; Denomination of invention: " based on the multichannel monitoring host platform of digital television whole thread monitoring " discloses a kind of digital television monitoring equipment, do not relate to the technology of multi-path digital TV signal descrambling; Patentee Beijing Bohui Science and Technology Co., Ltd. one Chinese patent application numbers 200720148127.3; Utility model title: " based on IP main broadcaster's embedded digital TV code flow monitoring equipment "; Disclose a kind of digital television monitoring equipment, that wherein the TV signal descrambling uses is the CIMaX chip T90FJR of above-mentioned atmel corp issue.
Summary of the invention
The objective of the invention is, a kind of multi-path digital TV descrambling interface chip is provided, improve the integrated level of DTV descrambling, simultaneously to two-way digital television signal descrambling at least.
For realizing above-mentioned purpose, the technical scheme that the present invention takes is: a kind of multi-path digital TV descrambling interface chip, comprise the I2C control interface, and be used for the configuration of register in the sheet; The TS stream interface is used to import the TS stream of encryption and the TS stream behind the output descrambling; The pcmcia bus interface is used for resetting, detects the CAM card, receives the interruption of CAM card, and CAM is sticked into capable read-write operation; TS stream interface and pcmcia bus interface constitute the physical link layer of DVB_CI general-purpose interface; Can external CAM card; External main control microprocessor can be accomplished the descrambling of digital television signal through said pcmcia bus interface control CAM card, through the clear stream behind the said TS stream interface output descrambling; Comprise that TS stream selects module, can select, send into the TS stream interface the different TS stream of two-way input signal at least; The TS stream interface comprises at least two passages, can handle the identical or different TS stream signal of the two-way at least that TS stream selects module to send into; Pcmcia bus interface and TS stream interface can external at least two CAM cards; External main control microprocessor can be controlled at least two-way CAM card through the pcmcia bus interface and accomplish the descrambling of two-way TS streaming digital TV signal at least, exports the clear stream behind the two-way descrambling at least through the TS stream interface.
The present invention has following beneficial effect: increased TS stream and selected module can select two-way TS stream signal entering TS stream interface at least; The TS stream interface can pass through two-way TS stream signal at least simultaneously; Through external CAM card while descrambling; Export at least that two-way TS clear stream satisfies user's use, improved the efficient of DTV descrambling greatly.
One of optimal way of the present invention: a kind of multi-path digital TV descrambling interface chip also comprises main control microprocessor; Main control microprocessor makes up operating system; Accomplish the initialization and read-write control of two-way CAM card at least through the pcmcia bus interface, realize the descrambling of two-way TS streaming digital TV signal at least.Because the chip built-in main control microprocessor has further improved the integrated level of chip.
Two of optimal way of the present invention: a kind of multi-path digital TV descrambling interface chip, make up with the FPGA of altera corp and to form, main control microprocessor is the NIOS microprocessor, operating system is uClinux operating system.Owing to be to make up with the FPGA of altera corp to form, not necessarily advance the flow of chip factory, practice thrift cost, also make things convenient for equipment manufacturers' design and use, the while, the exploitation of operating system uClinux also was familiar with by vast equipment manufacturers based on the NIOS microprocessor.
One purpose more of the present invention is, a kind of digital television signal monitoring equipment is provided, and can be simultaneously the above digital television signal of two-way be at least carried out descrambling, improves the integrated level of headend equipment, saves monitoring machine room space.
Be to realize above-mentioned purpose, the technical scheme that the present invention takes is: a kind of digital television signal monitoring equipment, comprise module card, and realize the input of high-frequency digital TV signal, carry out the frequency locking of high-frequency digital TV signal and to the demodulation of high-frequency digital TV signal; Motherboard, the TS stream of receiver module card output, the TS that perhaps directly imports ASI flows, and realizes encrypting the descrambling of TS stream, the output clear stream; CPU board is realized controlled function, and the TS clear stream behind the descrambling is exported to follow-up equipment use; Motherboard uses a kind of multi-path digital TV descrambling interface chip; Can handle the identical or different TS streaming digital TV signal of two-way at least; External at least two CAM cards are accomplished the descrambling of two-way TS streaming digital TV signal at least, export the clear stream behind the two-way descrambling at least.
Foregoing invention has following beneficial effect: owing to used a kind of multi-path digital TV descrambling interface chip; May be done to the descrambling of few two-way TS streaming digital TV signal; Export the clear stream behind the two-way descrambling at least; Whole monitoring equipment integrated level is high, has realized monitoring and other application of multi-path digital TV signal in limited space.
Description of drawings
Fig. 1 is said a kind of multi-path digital TV descrambling interface chip embodiment 1 theory diagram.
Fig. 2 is that the TS of said a kind of multi-path digital TV descrambling interface chip embodiment 1 flows to sketch map.
Fig. 3 is the pcmcia interface bus structures sketch map of said a kind of multi-path digital TV descrambling interface chip embodiment 1.
Fig. 4 is said a kind of multi-path digital TV descrambling interface chip embodiment 1 main control microprocessor Organization Chart.
Fig. 5 is said a kind of digital television signal monitoring equipment embodiment 4 theory diagrams.
Fig. 6 is said a kind of digital television signal monitoring equipment embodiment 4 module card structural representations.
Embodiment
Below in conjunction with embodiment and with reference to accompanying drawing the present invention is further described.
Present embodiment provides a kind of two-way DTV descrambling interface chip, utilizes the fpga chip EP4CE15F23C8 structure of ALTERA to form.Accompanying drawing 1 said a kind of multi-path digital TV descrambling interface chip embodiment 1 theory diagram, the Reference numeral and the part that wherein relate to are as follows:
1.TS stream is selected module
11.TS import 1 12.TS input 2
13.TS import 3 14.TS input 4
(15.TS1 TS stream is selected module output) 16.TS2 (TS stream is selected module output)
2.TS stream interface
21.TS export 1 22.TS output 2
23.TS in1 (connecing CAM card 1) 24.TS out1 (connecing CAM card 1)
25.TS in2 (connecing CAM card 2) 26.TS out2 (connecing CAM card 2)
3.PCMCIA EBI
31.CAM block 1 control interface 32.CAM2 control interface
4. main control microprocessor
41. CAM interface (CAM interface) 42.I2C control interface
43. Flash/Sdram control interface 44.UART interface (serial port)
5.ASI to the SPI modular converter
51.ASI import 1 52.ASI input 2
TS stream is selected module 1; Importing 4 road TS stream signal is respectively TS input 1-11, TS input 2-12, TS input 3-13 and TS input 4-14; Can select above-mentioned four road TS stream input signal; Output TS1 (TS stream is selected module output) 15 and TS2 (TS stream is selected module output) 16 send into TS stream interface 2; Wherein TS input 1-13 and TS input 1-14 are that ASI imports 2 conversion to the input signal ASI input 1 of SPI modular converter 5 with ASI; TS stream interface 2 is used to import the TS stream of encryption and the TS stream behind the output descrambling, comprises two passages, can TS1 (TS stream is selected module output) 15 and the TS2 (TS stream is selected module output) 16 that TS stream selects module 1 to send into be handled; Pcmcia bus interface 3 is used for resetting, detects the CAM card, receives the interruption of CAM card, and CAM is sticked into capable read-write operation, can form CAM card 1 control interface 31 and CAM card 2 control interfaces 32; The physical link layer of TS stream interface 2 and pcmcia bus interface 3 formation DVB_CI general-purpose interfaces; Through CAM card 1 control interface 31 and TS in1 (connecing CAM card 1) 23; TS out1 (connecing CAM card 1) 24 external CAM cards 1; Through CAM card 2 control interfaces 32 and TS in2 (connecing CAM card 2) 25, TS out2 (connecing CAM card 2) 26 external CAM cards 2; Main control microprocessor 4 is through the descrambling of pcmcia bus interface 3 control CAM cards 1 with CAM card 2 completion two-way digital television signal TS1 (TS stream is selected module output) 15 and TS2 (output of TS stream selection module) 16, through clear stream TS output 1-21 behind the TS stream interface 2 output descramblings and TS output 2-22; Main control microprocessor 4; Comprise CAM interface41, I2C control interface 42, Flash/Sdram control interface 43; UART interface (serial port) 44; Register in I2C control interface 42 and UART interface (serial port) the 44 configuration sheets, Flash/Sdram control interface 43 plug-in memories make up operating systems, connect the data/address bus of main control microprocessor self and initialization and the read-write control that pcmcia bus interface 3 is accomplished two-way CAM cards through CAM interface (CAM interface) 41.
Accompanying drawing 2 is that the TS of said a kind of multi-path digital TV descrambling interface chip embodiment 1 flows to sketch map.
Table 1 TS flows to the sketch map interface signal
Functional description: ASI mainly is to utilize the IP kernel of Altera to accomplish the SPI signal that serial ASI conversion of signals becomes to walk abreast to SPI modular converter 5, then parallel signal is sent into CAM as required and sticks into the row deciphering.
It is the value that is written to port select register ts_channel according to main control microprocessor 4 that TS selects the function of module 1, selects 2 road TS signals appointment wherein is sent in the corresponding TS circulation road.
TS channel module is the value of the register ts_stream that writes according to main control microprocessor 4, selects which piece CAM the TS stream of admission passage is sent into and sticks into the row deciphering, and the stream after the deciphering is exported from spi_out_1 and spi_out_2.
ASI mainly is the function of utilizing the IP kernel completion transformation from serial to parallel data of ASI in the Altera storehouse to SPI modular converter 5; Three clock signals need be provided in this module; Generate the 337.5M clock with pll (phase-locked loop) among the design, the clock of 337.5M phase shift 90 degree and a 135M is as the input clock of ASI nuclear; Through what export behind the IP kernel is exactly standard SPI signal, can directly send into CAM and stick into the row deciphering.
It is that the TS stream of importing is assigned to corresponding TS circulation road that TS selects module 1.The input interface of TS stream has 6 the tunnel in module board; But in actual use, according to application scenario customization a road or two-way wherein the signal input is arranged, other several roads interfaces are unsettled; So this module according to the value of TS_channel register, corresponds to two-way TS stream in two TS passages.
The definition of table 2 TS_channel port select register position
Position explanation: the signal source of low 4 respective channel 1, the signal source of high 4 respective channel 2.SPI1, SPI2 signal are the TS stream of optional outside input.Be the value defined of four of IN1, IN2 below.
1), register IN1 everybody the definition, ts_ch_1 is a TS1 feeder connection signal.
0x0: free of data source.
0x1：ts1->?ts_ch_1。
0x2：ts2->?ts_ch_1。
0x3：ASI1->?ts_ch_1。
0x4：ASI2->?ts_ch_1。
0x5：SPI1->?ts_ch_1。
0x6：SPI2->?ts_ch_1。
Its residual value is invalid
2), register IN2 everybody the definition, ts_ch_2 is a TS1 feeder connection signal.
0x0: free of data source.
0x1：ts1->?ts_ch_2。
0x2：ts2->?ts_ch_2。
0x3：ASI1->?ts_ch_2。
0x4：ASI2->?ts_ch_2。
0x5：SPI1->?ts_ch_2。
0x6：SPI2->?ts_ch_2。
Its residual value is invalid
The function of TS_channel module mainly is the signal in the entering TS passage to be assigned to corresponding C AM card see the TS passage then off.The flow direction of concrete TS stream in passage is that the value according to the ts_stream register is provided with, and sees the following form:
TS stream flows to register ts_stream is set in table 3 passage
Position explanation: 1.0x00:ts_ch_1->do not decipher-spi_out_1; Ts_ch_2->do not decipher-spi_out_2
2.0x01:ts_ch_1-CAM1->spi_out_1; Ts_ch_2->do not decipher-spi_out_2
3.0x02:ts_ch_1-CAM2->spi_out_1; Ts_ch_2->do not decipher-spi_out_2
4.0x03:ts_ch_1-do not decipher-spi_out_1; Ts_ch_2->CAM1->spi_out_2
5.0x04:ts_ch_1-do not decipher-spi_out_1; Ts_ch_2->CAM2->spi_out_2
6.0x05:?ts_ch_1->CAM1->?spi_out_1；ts_ch_2->CAM2->?spi_out_2
7.0x06:?ts_ch_1->CAM2->?spi_out_1；ts_ch_2->CAM1->?spi_out_2
8.0x07:ts_ch_1-CAM1->CAM2->spi_out_1; Ts_ch_2->do not decipher-spi_out_2
9.0x08:ts_ch_1-do not decipher-spi_out_1; Ts_ch_2->CAM1->CAM2->spi_out_2
8.0x09:ts_ch_1-CAM2->CAM1->spi_out_1; Ts_ch_2->do not decipher-spi_out_2: reserve
9.0x0a:ts_ch_1-do not decipher-spi_out_1; Ts_ch_2->CAM2->CAM1->spi_out_2: reserve
10. its residual value is invalid.
Accompanying drawing 3 is pcmcia interface bus structures sketch mapes of said a kind of multi-path digital TV descrambling interface chip embodiment 1.
Table 4 pcmcia bus interface module interface signal
Functional description: this module realizes pcmcia bus interface 3 sequential, realizes the input/output space read/write operation of CAM card, four sequential of memory read/write operations.Two CAM cards are to hang on the bus in the module, when read-write, need choose wherein card, and ce1a_n and ce1b_n that the Cam_add signal of being imported by main control microprocessor 4 generates are used for choosing a CAM card wherein.The read/write operation of CAM card: at first main control microprocessor 4 is given RD/WR signal of this module; Write the Acs_a/Acs_b register through the I2C bus simultaneously; Confirm I/O read/write or memory read/write; The sequential generating module is started working simultaneously, according to read-write mode and type a module by signal in four tfi modules is outputed to pcmcia bus interface 3 then.
Accompanying drawing 4 is said a kind of multi-path digital TV descrambling interface chip embodiment 1 main control microprocessor Organization Charts.
Table 5 main control microprocessor interface signal
| The interface signal title | Direction | Describe |
| Clk_0 | I | System's master clock |
| Reset_n | I | Cpu reset signal |
| export_addr_from_the_CAM | O | 26bit cam address bus |
| export_data_to_and_from_the_CAM | I/O | 8bit Cam data bus signal |
| export_rd_from_the_CAM | O | CAM card read signal |
| export_wr_from_the_CAM | O | CAM card write signal |
| scl_pad_io_to_and_from_the_i2c_0 | O | The I2C clock signal |
| sda_pad_io_to_and_from_the_i2c_ | I/O | The I2C data-signal |
| out_port_from_the_PIO_OUT | O | 8bit parallel port output signal |
| read_n_to_the_ext_FLASH | O | The Flash read signal |
| select_n_to_the_ext_FLASH | O | The Flash chip selection signal |
| FALSH_SDRAM_address | O | Sdram and flash address interface |
| FALSH_SDRAM_byteenablen | O | ? |
| FALSH_SDRAM_data | I/O | Sdram and flash data-interface |
| write_n_to_the_ext_FLASH | O | The Flash write signal |
| zs_ba_to_the_ext_SDRAM_test_component | O | ? |
| zs_cas_n_to_the_ext_SDRAM_test_component | O | Sdram column selection messenger |
| zs_cke_to_the_ext_SDRAM_test_component | O | ? |
| zs_cs_n_to_the_ext_SDRAM_test_component | O | The Sdram chip selection signal |
| zs_ras_n_to_the_ext_SDRAM_test_component | O | The capable gating signal of Sdram |
| zs_we_n_to_the_ext_SDRAM_test_component | O | The Sdram read signal |
| rxd_to_the_UART | I | Serial ports receives signal |
| txd_from_the_UART | O | Serial ports sends signal |
Functional description: this module mainly be make up a NIOS with the sopc of Altera CPU and peripheral hardware thereof as main control microprocessor 4; Operation uClinux operating system on this CPU is carried out deinitialization of pcmcia bus interface protocol and read-write CAM card in system then.
Table 6 CAM interface (CAM interface) interface signal
| The interface signal title | Direction | Describe |
| sys_clk | I | System's master clock |
| reset_n | I | Reset signal |
| chipselect | I | Avalon bus chip selection signal |
| read | I | Avalon bus read signal |
| write | I | Avalon bus write signal |
| Avalon_in_data | I | The input of 8bit Avalon bus data |
| Avalon_out_data | O | The output of 8bit Avalon bus |
| Avalon_addr | I | The input of 26bit Avalon bus address |
| export_data | I/O | 8bit CAM data I/O mouth |
| export_addr | O | 26bit CAM card address bus |
| export_rd | O | CAM card read signal |
| export_wr | O | CAM card write signal |
| export_oe | O | The CAM card selects signal |
The major function of CAM interface (CAM interface) 41 is that the Avalon-MM bus of the pcmcia bus interface of main control microprocessor 4 outsides and main control microprocessor 4 inside is interconnected.Because the signal definition basically identical of two kinds of buses; So can pcmcia bus interface IP address line directly be linked to each other with the Avalon address wire; The reading writing signal line of pcmcia bus interface reading writing signal line and Avalon directly links to each other, and the chipselect signal of Avalon links to each other with the export_oe of pcmcia bus interface.
Data wire input and output for Avalon are two buses, and the data wire of pcmcia bus interface is an input/output bus.Here need come the direction of transfer of data on the control bus with write signal write.When the Write signal is " 1 ", the Avalon_in_data data are sent on the export_data bus, when the write signal is " 0 ", the data on the export_data bus are sent on the Avalon_out_data bus.
Present embodiment provides a kind of four way word TV descrambling interface chips, utilizes the fpga chip EP4CE15F23C8 structure of ALTERA to form.The input of making following change: TS selection module 1 on the basis based on embodiment 1 increases to the input of octuple TS stream, can export four road TS stream through TS stream selection module, promptly increases TS3 (TS stream is selected module output) and TS4 (TS flows and selects module output); TS stream interface 2 comprises that four passages promptly increase TS in3 (connecing CAM card 3), TS out3 (connecing CAM card 3), TS in4 (connecing CAM card 4), TS out4 (connecing CAM card 4); Pcmcia bus interface 3 can external four CAM cards, promptly increase CAM card 3 control interfaces, the CAM4 control interface; The physical link layer of TS stream interface 2 and pcmcia bus interface 3 formation DVB_CI general-purpose interfaces; In addition can be through CAM card 3 control interfaces and TS in3 (connecing CAM card 3); The external CAM card 3 of TS out3 (connecing CAM card 3); Through CAM card 4 control interfaces and TS in4 (connecing CAM card 4), the external CAM card 4 of TS out4 (connecing CAM card 4); Main control microprocessor 4 also can be accomplished the descrambling of two-way digital television signal TS3 (TS stream is selected module output) and TS4 (TS stream is selected module output) through pcmcia bus interface 3 control CAM cards 3 and CAM card 4.Logical design is done corresponding change based on above-mentioned change.
Present embodiment provides a kind of two-way DTV descrambling interface chip, is designed to asic chip.Logic is with embodiment 1, through the top layer design of ASIC, module level design, module implementation phase; The subsystem simulation stage, system emulation synthesis phase, rear end layout design stage; The silicon test vector preparatory stage, rear end gate leve simulation stage finally is designed to asic chip, advances factory's flow and produces.
Embodiment 4
Present embodiment provides a kind of two-way digital television signal monitoring equipment, uses a kind of two-way DTV descrambling interface chip shown in the embodiment 1.Accompanying drawing 5 is said a kind of digital television signal monitoring equipment embodiment 4 theory diagrams, and the Reference numeral and the part that wherein relate to are as follows:
1. module card
2. motherboard
21. two-way DTV descrambling interface chip 22.CAM card 1 and CAM card 2
3. CPU board
A kind of two-way digital television signal monitoring equipment comprises module card 1, realizes the input of high-frequency digital TV signal, carries out the frequency locking of high-frequency digital TV signal and to the demodulation of high-frequency digital TV signal; Motherboard 2 is supported various digital television protocol, comprising: DVB-C, DVB-S, DVB-T, DVB-S2, CTTB, ABS-S, and the TS stream of receiver module card output, the TS that perhaps directly imports ASI flows, and realizes encrypting the descrambling of TS stream, the output clear stream; CPU board 3 is realized controlled function, and the TS clear stream behind the descrambling is exported to follow-up equipment use; Motherboard 2 uses a kind of two-way DTV descrambling interface chip 21; Can handle the identical or different TS streaming digital TV signal of two-way; External two CAM cards are CAM card 1 and CAM card 2-22; Accomplish the descrambling of two-way TS streaming digital TV signal, the clear stream behind the output two-way descrambling supplies to monitor or use to follow-up equipment.
Comprise two module card, realize the frequency locking of two-way high-frequency digital TV signal and the demodulation of two-way high-frequency digital TV signal.
Table 7 two-way digital television signal monitoring equipment chip type selecting table
| The main chip type selecting | The chip functions explanation |
| RT8011/APQW | Give 3.3V 1.2V 2.5V power supply |
| A8292 | Give the satellite antenna feed |
| AIC1526-1 | Be used for CAM card power supply control |
| AOZ1016AI | 12V changes the 5V power supply |
| EP4CE15F23C8N | FPGA is used for handling and stream switches |
| EPCS4SI8N | The FPGA configuring chip |
| EP4CE15F23C8 | Fpga chip |
| MT48LC16M16A2P-75 | The SDRAM chip is used to cooperate FPGA to handle |
| LMH0002MA | Be used for ASI output |
| LMH0034MA | Be used for the ASI input |
| M29W640GB70NA6E | FLASH is used for stored program |
Accompanying drawing 6 is said a kind of digital television signal monitoring equipment embodiment 4 module card structural representations.Mainly comprise high frequency lock phase and demodulator circuit.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and replenish, these improvement and replenish and also should be regarded as protection scope of the present invention.
Claims (7)
1. a multi-path digital TV descrambling interface chip comprises the I2C control interface, is used for the configuration of register in the sheet; The TS stream interface is used to import the TS stream of encryption and the TS stream behind the output descrambling; The pcmcia bus interface is used for resetting, detects the CAM card, receives the interruption of CAM card, and CAM is sticked into capable read-write operation; TS stream interface and pcmcia bus interface constitute the physical link layer of DVB_CI general-purpose interface; Can external CAM card; External main control microprocessor can pass through the descrambling that said pcmcia bus interface control CAM card is accomplished digital television signal, and the clear stream through behind the said TS stream interface output descrambling is characterized in that: comprise TS stream selection module; Can select the different TS stream of two-way at least input signal, send into said TS stream interface; Said TS stream interface comprises at least two passages, can handle the identical or different TS stream signal of the two-way at least that TS stream selects module to send into; Said pcmcia bus interface and said TS stream interface can external at least two CAM cards; External main control microprocessor can be controlled at least two-way CAM card through said pcmcia bus interface and accomplish the descrambling of two-way TS streaming digital TV signal at least, exports the clear stream behind the two-way descrambling at least through said TS stream interface.
2. a kind of multi-path digital TV descrambling interface chip according to claim 1, it is characterized in that: said chip is designed by FPGA.
3. a kind of multi-path digital TV descrambling interface chip according to claim 1; It is characterized in that: comprise said main control microprocessor; Said main control microprocessor makes up operating system; Accomplish the initialization and read-write control of two-way CAM card at least through said pcmcia bus interface, realize the descrambling of two-way TS streaming digital TV signal at least.
4. a kind of multi-path digital TV descrambling interface chip according to claim 3, it is characterized in that: said chip is designed by FPGA.
5. a kind of multi-path digital TV descrambling interface chip according to claim 4, it is characterized in that: said FPGA is altera corp's product, and said main control microprocessor is the NIOS microprocessor, and said operating system is uClinux operating system.
6. use a kind of digital television signal monitoring equipment of the arbitrary said a kind of multi-path digital TV descrambling interface chip of claim 1 to 5; Comprise module card; Realize the input of high-frequency digital TV signal, carry out the frequency locking of high-frequency digital TV signal and the demodulation of high-frequency digital TV signal; Motherboard, the TS stream of receiver module card output, the TS that perhaps directly imports ASI flows, and realizes encrypting the descrambling of TS stream, the output clear stream; CPU board; Realize controlled function, and the TS clear stream behind the descrambling exported to follow-up equipment use that it is characterized in that: said motherboard uses a kind of multi-path digital TV descrambling interface chip; Can handle the identical or different TS streaming digital TV signal of two-way at least; External at least two CAM cards are accomplished the descrambling of two-way TS streaming digital TV signal at least, export the clear stream behind the two-way descrambling at least.
7. a kind of digital television signal monitoring equipment according to claim 6 is characterized in that: comprise at least two module card, realize the frequency locking of two-way high-frequency digital TV signal at least and to two-way high-frequency digital TV signal demodulation at least.
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