CN102412249B - Power device structure capable of decreasing latch-up effect and fabrication method thereof - Google Patents
Power device structure capable of decreasing latch-up effect and fabrication method thereof Download PDFInfo
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- CN102412249B CN102412249B CN201110310518.1A CN201110310518A CN102412249B CN 102412249 B CN102412249 B CN 102412249B CN 201110310518 A CN201110310518 A CN 201110310518A CN 102412249 B CN102412249 B CN 102412249B
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Abstract
The invention discloses a power device structure capable of decreasing the latch-up effect, which is provided with a high voltage-withstanding first type semiconductor substrate region, a second type semiconductor base region and a first type semiconductor source region, the second type semiconductor base region and the first type semiconductor source region are positioned on the first type semiconductor substrate region, and a drain region is led out from the back; the front of a silicon wafer is provided with an embedded trench, which is a second type semiconductor polycrystalline silicon and is connected with the source region and the base region through gate oxide isolation and isolated from the source region by a sidewall; a second type semiconductor polycrystalline silicon is embedded in the base region, and is connected with the base region and the source region; and the embedded polycrystalline silicon is connected with the source region through metal silicide. The invention reduces the cell area, decreases the latch-up effect, and reduces the fabrication cost.
Description
Technical field
The present invention relates to power unit structure and manufacture method in a kind microelectronic chip manufacture field
Background technology
For power component, conventionally wish that transistorized conducting resistance is less, saturation voltage drop is lower, current driving ability is larger, for identical technological level, the area that how to dwindle cellular is most important.The Impurity Diffusion effect that can not exempt from due to traditional doping process, add repeatedly in photoetching process to alignment request, to must setting between each doped region must safe distance, therefore traditional power component area is conventionally all larger, entirety conducting resistance Rsp(Rsp=on-resistance per unit Rdson* device area) can not effectively reduce, photoetching alignment also be there are certain requirements.
In addition, when the hole current of well region acquires a certain degree, can raise well region current potential, source-trap junction barrier is declined, cause the unlatching of parasitic bipolar transistor,, there is latch-up in now just uncontrollable current switch of grid.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of power unit structure that reduces latch-up, and it can dwindle cell density, reduces latch-up, reduces manufacturing cost.
In order to solve above technical problem, the invention provides a kind of power unit structure that reduces latch-up: comprising: there is a high voltage bearing first type semiconductor substrate region, Second-Type semiconductor base on it and the first type semiconductor source region, draw from the back side in drain region; At front side of silicon wafer, there is a groove of imbedding in body, be Second-Type polycrystalline silicon semiconductor, be connected with base with source region by the isolation of grid oxygen, by side wall and source region isolation; Imbed a Second-Type polycrystalline silicon semiconductor in base, be connected with source region with base; The polysilicon of imbedding is connected with source region by metal silicide.
Beneficial effect of the present invention is: dwindle cell density, reduce latch-up, reduce manufacturing cost.
The present invention also provides a kind of manufacture method of the power unit structure that reduces latch-up, comprises the following steps:
On substrate, form base by epitaxy technique, and first hard mask layer of growing up;
Photoetching produces groove grid region, utilizes the first hard mask layer etch silicon substrate to form groove;
Grid oxygen is grown up and is filled polysilicon;
Anti-carve polysilicon to the first hard mask layer, photoetching forms source region, and etching the first hard mask layer, carries out source region injection;
Second hard mask layer of growing up;
Photoetching forms polysilicon and imbeds region, and etching opens the second hard mask layer, then utilizes the second hard mask layer etching groove;
Fill polysilicon and anti-carve to the second hard mask layer;
Return comprehensively and carve the second hard mask layer, form side wall;
Metal silicide is grown up and is removed the metal silicide on side wall;
Described the first hard mask layer and the second hard mask layer, its material can be identical.The first hard mask layer and the second hard mask layer, in etching process, needing has selection ratio with silicon, can be SiO2, SiN or SiC and other Si containing doping, O, N, the compound of C etc.
Brief description of the drawings
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the power unit structure schematic diagram of this patent;
Fig. 2 is the manufacture method schematic diagram of this patent.
Description of reference numerals in figure: 1, substrate, 2, base, 3, source region, 4, p-type polysilicon, 5, grid oxygen, 6, N-shaped polysilicon, 9, the first hard mask layer, 10, the second hard mask layer.
Embodiment
This patent adopts self-alignment structure, by imbed p-type polycrystalline in p trap, and use metal silicide technology to make it to be connected with source region, the hole stream that is conducive to well region flows out and the accumulation in minimizing hole rapidly, improve the ability of anti-breech lock to reach, be conducive to obtain the power device of less conducting resistance, lower saturation voltage drop and larger current driving ability.Take self-registered technology to be connected p-type polycrystalline and source region with metal silicide simultaneously, can effectively dwindle cell density.
Adopt self-registered technology simultaneously, and connected with metal silicide, simplified manufacturing process, reduced production cost.
This patent is taking the first type semiconductor as n, and Second-Type semiconductor is that p gives an example
1) choose N-shaped substrate, utilize epitaxy technique on substrate, to form p shape base, its thickness is chosen according to device property, be typically 0.5～10um, its doping can be B or BF, and bulk concentration is 1e12～1e20atom/cm3, first hard mask layer of growing up, can be SiO2, SiN, the Si of SiC or other doping, C, O, the compounds such as N, its thickness be 200A～10um not etc., depending on the etching groove degree of depth.
2) photoetching produces groove grid region, utilizes the first hard mask layer etch silicon substrate to form groove, its degree of depth be 0.5～10um not etc., depending on device property, its etching is dry etching.
3) grid oxygen is grown up and is filled heavy doping N-shaped polysilicon, and its doping can be P, As etc., bulk concentration 1e14～1e24atom/cm
3
4) dry method anti-carves polysilicon to the first hard mask layer, photoetching forms source region, its region can expand 0.2～10um than the region of requirement on devices, to reduce the demand of photoetching alignment, and etching the first hard mask layer, can be dry method or the etching of excuting a law, and carry out source region injection, its implanted dopant is P or As, and Implantation Energy is 10～500kev, and implantation dosage is 1e12～1e16atom/cm
3, can add appropriate activation annealing, make it activation, finally form the degree of depth and be less than the base degree of depth.
5) second hard mask layer of growing up, its material can be identical with the first mask layer, thickness be 200A～10um not etc., depending on the etching groove degree of depth.
6) photoetching forms polysilicon and imbeds region, graph area can greatly to 0.2～10um with source region overlapping region, to reduce photoetching process difficulty, first taking silicon as barrier layer, etching is opened the second hard mask layer, and then switch etching carrier, and utilizing the second hard mask layer etching groove, gash depth is to be no more than the base degree of depth as good.
7) fill p-type polysilicon, it is doped to B or BF, bulk concentration 1e18～1e24atom/cm
3, return and carve to the second hard mask layer comprehensively.
8) return comprehensively and carve the second hard mask layer, form side wall, now to silicon substrate loss <1000A.
9) metal silicide is grown up and is removed the metal silicide on side wall, can choose the materials such as Ti, Co, Ni, forms low-resistance metal silicide the polysilicon region of imbedding is connected with source region, and draw as electrode.
The present invention is not limited to execution mode discussed above.Above the description of embodiment is intended in order to describe and illustrate the technical scheme the present invention relates to.Apparent conversion based on the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, to make those of ordinary skill in the art can apply numerous embodiments of the present invention and multiple alternative reaches object of the present invention.
Claims (4)
1. one kind is reduced the power unit structure of latch-up: it is characterized in that, comprising:
There is a high voltage bearing first type semiconductor substrate region, the Second-Type semiconductor base on it and the first type semiconductor source region, draw from the back side in drain region;
At front side of silicon wafer, there is a groove of imbedding in body, fill Second-Type polycrystalline silicon semiconductor, be connected with base with source region by the isolation of grid oxygen, by side wall and source region isolation;
Imbed a Second-Type polycrystalline silicon semiconductor in base, be connected with source region with base;
The polysilicon of imbedding is connected with source region by metal silicide.
2. the manufacture method of the power unit structure of reduction latch-up as claimed in claim 1, is characterized in that, comprises the following steps:
On substrate, form base by epitaxy technique, and first hard mask layer of growing;
Photoetching produces groove grid region, utilizes the first hard mask layer etched substrate to form groove;
Grid oxygen is grown up and is filled polysilicon;
Anti-carve polysilicon to the first hard mask layer, photoetching forms source region, and etching the first hard mask layer, carries out source region injection;
Second hard mask layer of growing up;
Photoetching forms polysilicon and imbeds region, and etching opens the second hard mask layer, then utilizes the second hard mask layer etching groove;
Fill polysilicon and anti-carve to the second hard mask layer;
Return comprehensively and carve the second hard mask layer, form side wall;
Metal silicide is grown up and is removed the metal silicide on side wall.
3. the manufacture method of the power unit structure of reduction latch-up according to claim 2, is characterized in that, the first hard mask layer and the second hard mask layer, and its material is identical, or different.
4. the manufacture method of the power unit structure of reduction latch-up according to claim 2, is characterized in that, the first hard mask layer and the second hard mask layer, and in etching process, needing has selection ratio with silicon, can be SiO
2, SiN or SiC and other Si containing doping, O, N, the compound of C.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110310518.1A CN102412249B (en) | 2011-10-13 | 2011-10-13 | Power device structure capable of decreasing latch-up effect and fabrication method thereof |
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| CN201110310518.1A CN102412249B (en) | 2011-10-13 | 2011-10-13 | Power device structure capable of decreasing latch-up effect and fabrication method thereof |
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| CN102412249A CN102412249A (en) | 2012-04-11 |
| CN102412249B true CN102412249B (en) | 2014-10-08 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574397A (en) * | 2003-06-24 | 2005-02-02 | 精工电子有限公司 | Vertical mos transistor |
| CN102130015A (en) * | 2006-10-03 | 2011-07-20 | 电力集成公司 | Trench-gate vertical mosfet manufacturing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3298472B2 (en) * | 1997-09-26 | 2002-07-02 | 関西日本電気株式会社 | Method for manufacturing insulated gate semiconductor device |
| TW200713579A (en) * | 2005-09-26 | 2007-04-01 | Fwu-Iuan Hshieh | Structure for avalanche improvement of ultra high density trench MOSFET |
| CN201904342U (en) * | 2011-01-05 | 2011-07-20 | 西安后羿半导体科技有限公司 | Medium-pressure heavy-current N-path enhanced power MOS tube |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574397A (en) * | 2003-06-24 | 2005-02-02 | 精工电子有限公司 | Vertical mos transistor |
| CN102130015A (en) * | 2006-10-03 | 2011-07-20 | 电力集成公司 | Trench-gate vertical mosfet manufacturing method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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