CN102376689A - Through silicon hole structure with step and manufacture process of through silicon hole - Google Patents
Through silicon hole structure with step and manufacture process of through silicon hole Download PDFInfo
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- CN102376689A CN102376689A CN2011102662864A CN201110266286A CN102376689A CN 102376689 A CN102376689 A CN 102376689A CN 2011102662864 A CN2011102662864 A CN 2011102662864A CN 201110266286 A CN201110266286 A CN 201110266286A CN 102376689 A CN102376689 A CN 102376689A
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Abstract
The invention discloses a through silicon hole structure with a step, which comprises a semiconductor substrate and a through hole penetrating through the semiconductor substrate and having the step, wherein an insulation layer, an adhesion layer and a barrier layer are sequentially deposited on the side wall of the step through hole; a metal conductor is filled in the through hole; an interconnecting structure formed by sequential deposition of the insulation layer, the adhesion layer, the barrier layer and a conductive layer is deposited on the surface of the semiconductor substrate; and the conductive layer in the interconnecting structure is connected with the metal conductor. The invention also provides a manufacture process of the through silicon hole structure. The step in the through silicon hole can allow copper cylinder protruding height difference caused by local electroplating rate difference in an electroplating hole-filling process, and avoids silicon wafer breakage caused by the problem in a chemical mechanical polishing (MCP) process and a bonding process.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to through-silicon via structure and preparation technology thereof in the vertical interconnecting structure in the three-dimensional systematic encapsulation.
Background technology
At the beginning of the integrated circuit industry development, people just pass through reduce critical dimensions constantly, continue to improve the integrated level of chip, to obtain high performance semiconductor chip.After critical size reaches several nanometers, continue reduce critical dimensions and brought problems such as sharp increase of photoetching process implementation cost and physical characteristics of materials limitation.
More existing mode through the chip edge pin interconnection forms three-dimensional stacked encapsulation, silicon through hole technology will bring have higher transmission speed, shorter RC postpones, the three-dimensional stacked encapsulation of littler energy consumption, littler chip area.This technology can also technology is different integrated circuit and MEMS chip integrated, make encapsulation have more function.
The silicon through hole is formed on the Semiconductor substrate, and total comprises insulating barrier, adhesion layer, barrier layer in the through hole and the transverse interconnection structure that links to each other with substrate devices.
Fig. 1 shows a kind of existing ordinary silicon through-hole structure, and this structure comprises Semiconductor substrate 100, and integrated circuit 101 (not marking details), integrated circuit pad 102 are arranged on the substrate, and is formed at two through-silicon via structures in the substrate 100.Through-silicon via structure comprises the insulating barrier 107 that is deposited on through-hole side wall, adhesion layer, barrier layer 108, and Seed Layer 109 is filled metal 110,111.Seed Layer 109 also couples together integrated circuit pad 102 and filling metal 110.Seed metal layer 109 is through adhesion barrier layer 108 good being bonded on the insulating barrier 107.
Fig. 1 obviously shows the uneven phenomenon of rate of deposition between each through hole.Because the difference of micro-structure in the through hole; The difference of internal structure behind the opening is dwindled in plating, and the difference of electroplating process itself will cause rate of deposition to be not quite similar; It is different just very likely to occur electroplating the back protrusion height; This problem will cause in cmp (CMP), bonding technology that stress is concentrated, cause silicon chip to break, and make whole silicon wafer scrap.
Summary of the invention
The object of the present invention is to provide a kind of through-silicon via structure with step; Can tolerate and electroplate the copper post protrusion height difference that parcel plating speed difference causes in the filling perforation process, the silicon chip of avoiding in chemico-mechanical polishing (CMP) technology, bonding technology, causing owing to foregoing problems breaks.
Another object of the present invention is to provide above-mentioned preparation technology with through-silicon via structure of step.
A kind of through-silicon via structure with step; Comprise Semiconductor substrate and the through hole that runs through said Semiconductor substrate with step; Said step through-hole sidewall deposits insulating barrier, adhesion layer, barrier layer successively; Be filled with metallic conductor in the through hole, also deposit the interconnection structure that is made up of insulating barrier, adhesion layer, barrier layer, conductive layer deposition on the semiconductor substrate surface successively, the conductive layer in the interconnection structure is connected with metallic conductor.
Further, comprise that also the pad that links to each other with described metallic conductor surface is or/and soldered ball.
Said pad or/and soldered ball link to each other with metallic conductor is vertical.
Said pad or/and soldered ball link to each other with filling conductor out of plumb.
Said pad is or/and soldered ball adopts any one in copper, tungsten, the aluminium.
A kind of through-hole structure preparation technology with step comprises step:
(1) two-sided etching forms the through hole with step on Semiconductor substrate;
(2) depositing insulating layer, adhesion layer, barrier layer and Seed Layer successively on described through-hole side wall and semiconductor substrate surface;
(3) at first electroplate sealing through hole small diameter ports, electroplate from through hole major diameter port again and fill metallic conductor;
(4) remove unnecessary insulating barrier, adhesion layer, barrier layer and the Seed Layer of substrate surface and be formed for the interconnection structure that device links to each other with through hole.
Said etching adopts the deep reaction ion etching method.
The mask that said deep reaction ion etching adopts is from photoresist, aluminium, SiO
2, silicon nitride combination in choose;
Said insulating barrier is chosen from the set of silica and silicon nitride, and thickness is 200nm to 2 μ m.
Technique effect of the present invention is embodied in: the invention discloses a kind of through-silicon via structure with step; This structure is through increasing the size of the low stomidium of substrate; Electroplate in the process of filler opening, under same condition, reduced the current density on the copper post that first completion fills; Also just reduce speed that it increases downwards, can tolerate the influence that the substrate lower surface copper post protrusion height difference that causes because of rate of deposition difference causes follow-up cmp or bonding technology preferably.
Description of drawings
Fig. 1 is a kind of existing ordinary silicon through-hole structure figure.
Fig. 2 is through-silicon via structure figure of the present invention.
Fig. 3 is the preparation technology of through-silicon via structure of the present invention.
Embodiment
The typical implementation method of description explanation invention.
As shown in Figure 2, this structure comprises semiconductor silicon substrate 100, and integrated circuit 101 (not marking details), integrated circuit pad 102 are arranged on the substrate, and is formed at two through-silicon via structures with step in the substrate 100.Through-silicon via structure comprises the insulating barrier SiO2107 that is deposited on through-hole side wall, Ti adhesion barrier layer 108, and copper seed layer 109 is filled metallic copper 110,111.Part copper Seed Layer 109 at substrate 100 upper surfaces also couples together integrated circuit pad 102 and filling metal 110 as transverse interconnects.In the copper seed metal layer 109 of substrate 100 upper surfaces through adhesion barrier layer 108 good being bonded on the insulating barrier 107 on the substrate.
Fig. 3 is for making the typical method sketch map of this through-silicon via structure.Its basic step is:
A deposits one deck mask lithography glue 103 at the upper and lower surface of the Semiconductor substrate that provides, and comes out through dual surface lithography technology and the feasible substrate of desiring etching;
B use deep reaction ion etching equipment to certain depth, forms through hole 112,113 from following etching from top etched substrate again;
C uses thermal oxidation technology to form insulating barrier 107 on through-hole side wall, Semiconductor substrate two surfaces, and the partial insulative layer on the integrated circuit pad 102 is removed in photoetching, uses sputtering technology at through-hole side wall, upper surface deposition adhesion barrier layer Ti108, Seed Layer Cu109;
D protects through the Seed Layer that photoetching process makes photoresist 104 need not electroplate at the Semiconductor substrate upper surface, makes anode and upper surface relative, through electroplating technology the ring around the electroplated metal layer with closure of openings;
E is relative with anode and lower surface, accomplishes the metal filled of through hole through electroplating technology, forms to fill metal 110,111;
Unnecessary Seed Layer is removed in f photoetching protection, stays transverse interconnection structure.
Claims (9)
1. through-silicon via structure with step; Comprise Semiconductor substrate and the through hole that runs through said Semiconductor substrate with step; Said step through-hole sidewall deposits insulating barrier, adhesion layer, barrier layer successively; Be filled with metallic conductor in the through hole, also deposit the interconnection structure that is made up of insulating barrier, adhesion layer, barrier layer, conductive layer deposition on the semiconductor substrate surface successively, the conductive layer in the interconnection structure is connected with metallic conductor.
2. the through-silicon via structure with step as claimed in claim 1 is characterized in that, comprises that also the pad that links to each other with described metallic conductor surface is or/and soldered ball.
3. the through-silicon via structure with step as claimed in claim 2 is characterized in that, said pad or/and soldered ball link to each other with metallic conductor is vertical.
4. the through-silicon via structure with step as claimed in claim 2 is characterized in that, said pad or/and soldered ball link to each other with filling conductor out of plumb.
5. like claim 2 or 3 or 4 described through-silicon via structures, it is characterized in that said pad is or/and soldered ball adopts any one in copper, tungsten, the aluminium with step.
6. through-hole structure preparation technology with step comprises step:
(1) two-sided etching forms the through hole with step on Semiconductor substrate;
(2) depositing insulating layer, adhesion layer, barrier layer and Seed Layer successively on described through-hole side wall and semiconductor substrate surface;
(3) at first electroplate sealing through hole small diameter ports, electroplate from through hole major diameter port again and fill metallic conductor;
(5) remove unnecessary insulating barrier, adhesion layer, barrier layer and the Seed Layer of substrate surface and be formed for the interconnection structure that device links to each other with through hole.
7. the through-hole structure preparation technology who requires like right 6 is characterized in that said etching adopts the deep reaction ion etching method.
8. through-hole structure preparation technology as claimed in claim 7 is characterized in that, the mask that deep reaction ion etching adopts is from photoresist, aluminium, SiO
2, silicon nitride combination in choose.
9. through-hole structure preparation technology as claimed in claim 7 is characterized in that said insulating barrier is chosen from the set of silica and silicon nitride, thickness is 200nm to 2 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2011102662864A CN102376689A (en) | 2011-09-09 | 2011-09-09 | Through silicon hole structure with step and manufacture process of through silicon hole |
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| CN2011102662864A CN102376689A (en) | 2011-09-09 | 2011-09-09 | Through silicon hole structure with step and manufacture process of through silicon hole |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103077932A (en) * | 2013-02-05 | 2013-05-01 | 江苏物联网研究发展中心 | High-depth-to-width-ratio via interconnecting structure and production method |
| CN103367285A (en) * | 2013-07-26 | 2013-10-23 | 中国科学院微电子研究所 | Through via structure and manufacturing method thereof |
| CN103456772A (en) * | 2012-06-04 | 2013-12-18 | 南亚科技股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
| CN104952789A (en) * | 2015-04-29 | 2015-09-30 | 中国电子科技集团公司第三十八研究所 | Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) |
| CN106057757A (en) * | 2016-07-08 | 2016-10-26 | 桂林电子科技大学 | Silicon through hole structure and manufacturing method thereeof |
| CN107706173A (en) * | 2017-09-30 | 2018-02-16 | 成都嘉纳海威科技有限责任公司 | Silicon hole interconnection architecture and preparation method thereof and silicon hole RF transmitting structures |
| CN108878296A (en) * | 2018-06-27 | 2018-11-23 | 华中科技大学 | A kind of preparation method of three-dimensional micro convex point |
| CN109300877A (en) * | 2018-08-27 | 2019-02-01 | 北京大学 | Through-hole structure and its manufacturing method in a kind of semiconductor substrate |
| CN109378300A (en) * | 2016-11-27 | 2019-02-22 | 乐清市风杰电子科技有限公司 | Wafer packaging structure |
| CN111599749A (en) * | 2020-06-01 | 2020-08-28 | 联合微电子中心有限责任公司 | High-depth-width-ratio through type TSV structure, preparation method thereof and silicon adapter plate |
| CN112397445A (en) * | 2020-11-17 | 2021-02-23 | 联合微电子中心有限责任公司 | TSV conductive structure, semiconductor structure and preparation method |
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微***科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
| CN115132654A (en) * | 2022-09-01 | 2022-09-30 | 苏州臻芯微电子有限公司 | Preparation method of metalized through silicon via, metalized through silicon via and filter |
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| CN202332839U (en) * | 2011-12-01 | 2012-07-11 | 华中科技大学 | Silicon through hole structure |
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| CN1528018A (en) * | 2001-02-08 | 2004-09-08 | 微米技术有限公司 | High performance silicon contact for flip chip |
| CN101483150A (en) * | 2009-02-13 | 2009-07-15 | 华中科技大学 | Process for treating through wafer interconnection construction |
| CN202332839U (en) * | 2011-12-01 | 2012-07-11 | 华中科技大学 | Silicon through hole structure |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456772A (en) * | 2012-06-04 | 2013-12-18 | 南亚科技股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN103077932A (en) * | 2013-02-05 | 2013-05-01 | 江苏物联网研究发展中心 | High-depth-to-width-ratio via interconnecting structure and production method |
| CN103077932B (en) * | 2013-02-05 | 2015-10-14 | 华进半导体封装先导技术研发中心有限公司 | The interconnection structure of high aspect ratio vias and manufacture method |
| CN103367285A (en) * | 2013-07-26 | 2013-10-23 | 中国科学院微电子研究所 | Through via structure and manufacturing method thereof |
| CN103367285B (en) * | 2013-07-26 | 2015-10-14 | 华进半导体封装先导技术研发中心有限公司 | A kind of through-hole structure and preparation method thereof |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
| CN104952789A (en) * | 2015-04-29 | 2015-09-30 | 中国电子科技集团公司第三十八研究所 | Manufacturing method of adapter plate comprising high-aspect-ratio TSV (through silicon vias) |
| CN106057757A (en) * | 2016-07-08 | 2016-10-26 | 桂林电子科技大学 | Silicon through hole structure and manufacturing method thereeof |
| CN109378300B (en) * | 2016-11-27 | 2020-05-15 | 乐清市风杰电子科技有限公司 | Wafer packaging structure |
| CN109378300A (en) * | 2016-11-27 | 2019-02-22 | 乐清市风杰电子科技有限公司 | Wafer packaging structure |
| CN107706173A (en) * | 2017-09-30 | 2018-02-16 | 成都嘉纳海威科技有限责任公司 | Silicon hole interconnection architecture and preparation method thereof and silicon hole RF transmitting structures |
| CN108878296A (en) * | 2018-06-27 | 2018-11-23 | 华中科技大学 | A kind of preparation method of three-dimensional micro convex point |
| CN109300877A (en) * | 2018-08-27 | 2019-02-01 | 北京大学 | Through-hole structure and its manufacturing method in a kind of semiconductor substrate |
| CN111599749A (en) * | 2020-06-01 | 2020-08-28 | 联合微电子中心有限责任公司 | High-depth-width-ratio through type TSV structure, preparation method thereof and silicon adapter plate |
| CN111599749B (en) * | 2020-06-01 | 2022-06-24 | 联合微电子中心有限责任公司 | High-depth-width-ratio through type TSV structure, preparation method thereof and silicon adapter plate |
| CN112397445A (en) * | 2020-11-17 | 2021-02-23 | 联合微电子中心有限责任公司 | TSV conductive structure, semiconductor structure and preparation method |
| CN112397445B (en) * | 2020-11-17 | 2023-08-01 | 联合微电子中心有限责任公司 | TSV conductive structure, semiconductor structure and preparation method |
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微***科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
| CN115132654A (en) * | 2022-09-01 | 2022-09-30 | 苏州臻芯微电子有限公司 | Preparation method of metalized through silicon via, metalized through silicon via and filter |
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Application publication date: 20120314 |
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